async_tx.c 7.6 KB

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  1. /*
  2. * core routines for the asynchronous memory transfer/transform api
  3. *
  4. * Copyright © 2006, Intel Corporation.
  5. *
  6. * Dan Williams <dan.j.williams@intel.com>
  7. *
  8. * with architecture considerations by:
  9. * Neil Brown <neilb@suse.de>
  10. * Jeff Garzik <jeff@garzik.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms and conditions of the GNU General Public License,
  14. * version 2, as published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program; if not, write to the Free Software Foundation, Inc.,
  23. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24. *
  25. */
  26. #include <linux/rculist.h>
  27. #include <linux/kernel.h>
  28. #include <linux/async_tx.h>
  29. #ifdef CONFIG_DMA_ENGINE
  30. static int __init async_tx_init(void)
  31. {
  32. async_dmaengine_get();
  33. printk(KERN_INFO "async_tx: api initialized (async)\n");
  34. return 0;
  35. }
  36. static void __exit async_tx_exit(void)
  37. {
  38. async_dmaengine_put();
  39. }
  40. module_init(async_tx_init);
  41. module_exit(async_tx_exit);
  42. /**
  43. * __async_tx_find_channel - find a channel to carry out the operation or let
  44. * the transaction execute synchronously
  45. * @submit: transaction dependency and submission modifiers
  46. * @tx_type: transaction type
  47. */
  48. struct dma_chan *
  49. __async_tx_find_channel(struct async_submit_ctl *submit,
  50. enum dma_transaction_type tx_type)
  51. {
  52. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  53. /* see if we can keep the chain on one channel */
  54. if (depend_tx &&
  55. dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
  56. return depend_tx->chan;
  57. return async_dma_find_channel(tx_type);
  58. }
  59. EXPORT_SYMBOL_GPL(__async_tx_find_channel);
  60. #endif
  61. /**
  62. * async_tx_channel_switch - queue an interrupt descriptor with a dependency
  63. * pre-attached.
  64. * @depend_tx: the operation that must finish before the new operation runs
  65. * @tx: the new operation
  66. */
  67. static void
  68. async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
  69. struct dma_async_tx_descriptor *tx)
  70. {
  71. struct dma_chan *chan = depend_tx->chan;
  72. struct dma_device *device = chan->device;
  73. struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
  74. /* first check to see if we can still append to depend_tx */
  75. txd_lock(depend_tx);
  76. if (txd_parent(depend_tx) && depend_tx->chan == tx->chan) {
  77. txd_chain(depend_tx, tx);
  78. intr_tx = NULL;
  79. }
  80. txd_unlock(depend_tx);
  81. /* attached dependency, flush the parent channel */
  82. if (!intr_tx) {
  83. device->device_issue_pending(chan);
  84. return;
  85. }
  86. /* see if we can schedule an interrupt
  87. * otherwise poll for completion
  88. */
  89. if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  90. intr_tx = device->device_prep_dma_interrupt(chan, 0);
  91. else
  92. intr_tx = NULL;
  93. if (intr_tx) {
  94. intr_tx->callback = NULL;
  95. intr_tx->callback_param = NULL;
  96. /* safe to chain outside the lock since we know we are
  97. * not submitted yet
  98. */
  99. txd_chain(intr_tx, tx);
  100. /* check if we need to append */
  101. txd_lock(depend_tx);
  102. if (txd_parent(depend_tx)) {
  103. txd_chain(depend_tx, intr_tx);
  104. async_tx_ack(intr_tx);
  105. intr_tx = NULL;
  106. }
  107. txd_unlock(depend_tx);
  108. if (intr_tx) {
  109. txd_clear_parent(intr_tx);
  110. intr_tx->tx_submit(intr_tx);
  111. async_tx_ack(intr_tx);
  112. }
  113. device->device_issue_pending(chan);
  114. } else {
  115. if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
  116. panic("%s: DMA_ERROR waiting for depend_tx\n",
  117. __func__);
  118. tx->tx_submit(tx);
  119. }
  120. }
  121. /**
  122. * submit_disposition - flags for routing an incoming operation
  123. * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
  124. * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
  125. * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
  126. *
  127. * while holding depend_tx->lock we must avoid submitting new operations
  128. * to prevent a circular locking dependency with drivers that already
  129. * hold a channel lock when calling async_tx_run_dependencies.
  130. */
  131. enum submit_disposition {
  132. ASYNC_TX_SUBMITTED,
  133. ASYNC_TX_CHANNEL_SWITCH,
  134. ASYNC_TX_DIRECT_SUBMIT,
  135. };
  136. void
  137. async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
  138. struct async_submit_ctl *submit)
  139. {
  140. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  141. tx->callback = submit->cb_fn;
  142. tx->callback_param = submit->cb_param;
  143. if (depend_tx) {
  144. enum submit_disposition s;
  145. /* sanity check the dependency chain:
  146. * 1/ if ack is already set then we cannot be sure
  147. * we are referring to the correct operation
  148. * 2/ dependencies are 1:1 i.e. two transactions can
  149. * not depend on the same parent
  150. */
  151. BUG_ON(async_tx_test_ack(depend_tx) || txd_next(depend_tx) ||
  152. txd_parent(tx));
  153. /* the lock prevents async_tx_run_dependencies from missing
  154. * the setting of ->next when ->parent != NULL
  155. */
  156. txd_lock(depend_tx);
  157. if (txd_parent(depend_tx)) {
  158. /* we have a parent so we can not submit directly
  159. * if we are staying on the same channel: append
  160. * else: channel switch
  161. */
  162. if (depend_tx->chan == chan) {
  163. txd_chain(depend_tx, tx);
  164. s = ASYNC_TX_SUBMITTED;
  165. } else
  166. s = ASYNC_TX_CHANNEL_SWITCH;
  167. } else {
  168. /* we do not have a parent so we may be able to submit
  169. * directly if we are staying on the same channel
  170. */
  171. if (depend_tx->chan == chan)
  172. s = ASYNC_TX_DIRECT_SUBMIT;
  173. else
  174. s = ASYNC_TX_CHANNEL_SWITCH;
  175. }
  176. txd_unlock(depend_tx);
  177. switch (s) {
  178. case ASYNC_TX_SUBMITTED:
  179. break;
  180. case ASYNC_TX_CHANNEL_SWITCH:
  181. async_tx_channel_switch(depend_tx, tx);
  182. break;
  183. case ASYNC_TX_DIRECT_SUBMIT:
  184. txd_clear_parent(tx);
  185. tx->tx_submit(tx);
  186. break;
  187. }
  188. } else {
  189. txd_clear_parent(tx);
  190. tx->tx_submit(tx);
  191. }
  192. if (submit->flags & ASYNC_TX_ACK)
  193. async_tx_ack(tx);
  194. if (depend_tx)
  195. async_tx_ack(depend_tx);
  196. }
  197. EXPORT_SYMBOL_GPL(async_tx_submit);
  198. /**
  199. * async_trigger_callback - schedules the callback function to be run
  200. * @submit: submission and completion parameters
  201. *
  202. * honored flags: ASYNC_TX_ACK
  203. *
  204. * The callback is run after any dependent operations have completed.
  205. */
  206. struct dma_async_tx_descriptor *
  207. async_trigger_callback(struct async_submit_ctl *submit)
  208. {
  209. struct dma_chan *chan;
  210. struct dma_device *device;
  211. struct dma_async_tx_descriptor *tx;
  212. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  213. if (depend_tx) {
  214. chan = depend_tx->chan;
  215. device = chan->device;
  216. /* see if we can schedule an interrupt
  217. * otherwise poll for completion
  218. */
  219. if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  220. device = NULL;
  221. tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
  222. } else
  223. tx = NULL;
  224. if (tx) {
  225. pr_debug("%s: (async)\n", __func__);
  226. async_tx_submit(chan, tx, submit);
  227. } else {
  228. pr_debug("%s: (sync)\n", __func__);
  229. /* wait for any prerequisite operations */
  230. async_tx_quiesce(&submit->depend_tx);
  231. async_tx_sync_epilog(submit);
  232. }
  233. return tx;
  234. }
  235. EXPORT_SYMBOL_GPL(async_trigger_callback);
  236. /**
  237. * async_tx_quiesce - ensure tx is complete and freeable upon return
  238. * @tx - transaction to quiesce
  239. */
  240. void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
  241. {
  242. if (*tx) {
  243. /* if ack is already set then we cannot be sure
  244. * we are referring to the correct operation
  245. */
  246. BUG_ON(async_tx_test_ack(*tx));
  247. if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
  248. panic("DMA_ERROR waiting for transaction\n");
  249. async_tx_ack(*tx);
  250. *tx = NULL;
  251. }
  252. }
  253. EXPORT_SYMBOL_GPL(async_tx_quiesce);
  254. MODULE_AUTHOR("Intel Corporation");
  255. MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
  256. MODULE_LICENSE("GPL");