setup.c 10 KB

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  1. /*
  2. * arch/xtensa/kernel/setup.c
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1995 Linus Torvalds
  9. * Copyright (C) 2001 - 2005 Tensilica Inc.
  10. *
  11. * Chris Zankel <chris@zankel.net>
  12. * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  13. * Kevin Chea
  14. * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/init.h>
  18. #include <linux/mm.h>
  19. #include <linux/proc_fs.h>
  20. #include <linux/screen_info.h>
  21. #include <linux/bootmem.h>
  22. #include <linux/kernel.h>
  23. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  24. # include <linux/console.h>
  25. #endif
  26. #ifdef CONFIG_RTC
  27. # include <linux/timex.h>
  28. #endif
  29. #ifdef CONFIG_PROC_FS
  30. # include <linux/seq_file.h>
  31. #endif
  32. #include <asm/system.h>
  33. #include <asm/bootparam.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/processor.h>
  36. #include <asm/timex.h>
  37. #include <asm/platform.h>
  38. #include <asm/page.h>
  39. #include <asm/setup.h>
  40. #include <asm/param.h>
  41. #include <platform/hardware.h>
  42. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  43. struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
  44. #endif
  45. #ifdef CONFIG_BLK_DEV_FD
  46. extern struct fd_ops no_fd_ops;
  47. struct fd_ops *fd_ops;
  48. #endif
  49. extern struct rtc_ops no_rtc_ops;
  50. struct rtc_ops *rtc_ops;
  51. #ifdef CONFIG_BLK_DEV_INITRD
  52. extern void *initrd_start;
  53. extern void *initrd_end;
  54. extern void *__initrd_start;
  55. extern void *__initrd_end;
  56. int initrd_is_mapped = 0;
  57. extern int initrd_below_start_ok;
  58. #endif
  59. unsigned char aux_device_present;
  60. extern unsigned long loops_per_jiffy;
  61. /* Command line specified as configuration option. */
  62. static char __initdata command_line[COMMAND_LINE_SIZE];
  63. #ifdef CONFIG_CMDLINE_BOOL
  64. static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  65. #endif
  66. sysmem_info_t __initdata sysmem;
  67. #ifdef CONFIG_BLK_DEV_INITRD
  68. int initrd_is_mapped;
  69. #endif
  70. #ifdef CONFIG_MMU
  71. extern void init_mmu(void);
  72. #else
  73. static inline void init_mmu(void) { }
  74. #endif
  75. extern void zones_init(void);
  76. /*
  77. * Boot parameter parsing.
  78. *
  79. * The Xtensa port uses a list of variable-sized tags to pass data to
  80. * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
  81. * to be recognised. The list is terminated with a zero-sized
  82. * BP_TAG_LAST tag.
  83. */
  84. typedef struct tagtable {
  85. u32 tag;
  86. int (*parse)(const bp_tag_t*);
  87. } tagtable_t;
  88. #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
  89. __attribute__((unused, __section__(".taglist"))) = { tag, fn }
  90. /* parse current tag */
  91. static int __init parse_tag_mem(const bp_tag_t *tag)
  92. {
  93. meminfo_t *mi = (meminfo_t*)(tag->data);
  94. if (mi->type != MEMORY_TYPE_CONVENTIONAL)
  95. return -1;
  96. if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
  97. printk(KERN_WARNING
  98. "Ignoring memory bank 0x%08lx size %ldKB\n",
  99. (unsigned long)mi->start,
  100. (unsigned long)mi->end - (unsigned long)mi->start);
  101. return -EINVAL;
  102. }
  103. sysmem.bank[sysmem.nr_banks].type = mi->type;
  104. sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(mi->start);
  105. sysmem.bank[sysmem.nr_banks].end = mi->end & PAGE_SIZE;
  106. sysmem.nr_banks++;
  107. return 0;
  108. }
  109. __tagtable(BP_TAG_MEMORY, parse_tag_mem);
  110. #ifdef CONFIG_BLK_DEV_INITRD
  111. static int __init parse_tag_initrd(const bp_tag_t* tag)
  112. {
  113. meminfo_t* mi;
  114. mi = (meminfo_t*)(tag->data);
  115. initrd_start = (void*)(mi->start);
  116. initrd_end = (void*)(mi->end);
  117. return 0;
  118. }
  119. __tagtable(BP_TAG_INITRD, parse_tag_initrd);
  120. #endif /* CONFIG_BLK_DEV_INITRD */
  121. static int __init parse_tag_cmdline(const bp_tag_t* tag)
  122. {
  123. strncpy(command_line, (char*)(tag->data), COMMAND_LINE_SIZE);
  124. command_line[COMMAND_LINE_SIZE - 1] = '\0';
  125. return 0;
  126. }
  127. __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
  128. static int __init parse_bootparam(const bp_tag_t* tag)
  129. {
  130. extern tagtable_t __tagtable_begin, __tagtable_end;
  131. tagtable_t *t;
  132. /* Boot parameters must start with a BP_TAG_FIRST tag. */
  133. if (tag->id != BP_TAG_FIRST) {
  134. printk(KERN_WARNING "Invalid boot parameters!\n");
  135. return 0;
  136. }
  137. tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
  138. /* Parse all tags. */
  139. while (tag != NULL && tag->id != BP_TAG_LAST) {
  140. for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
  141. if (tag->id == t->tag) {
  142. t->parse(tag);
  143. break;
  144. }
  145. }
  146. if (t == &__tagtable_end)
  147. printk(KERN_WARNING "Ignoring tag "
  148. "0x%08x\n", tag->id);
  149. tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
  150. }
  151. return 0;
  152. }
  153. /*
  154. * Initialize architecture. (Early stage)
  155. */
  156. void __init init_arch(bp_tag_t *bp_start)
  157. {
  158. #ifdef CONFIG_BLK_DEV_INITRD
  159. initrd_start = &__initrd_start;
  160. initrd_end = &__initrd_end;
  161. #endif
  162. sysmem.nr_banks = 0;
  163. #ifdef CONFIG_CMDLINE_BOOL
  164. strcpy(command_line, default_command_line);
  165. #endif
  166. /* Parse boot parameters */
  167. if (bp_start)
  168. parse_bootparam(bp_start);
  169. if (sysmem.nr_banks == 0) {
  170. sysmem.nr_banks = 1;
  171. sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
  172. sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
  173. + PLATFORM_DEFAULT_MEM_SIZE;
  174. }
  175. /* Early hook for platforms */
  176. platform_init(bp_start);
  177. /* Initialize MMU. */
  178. init_mmu();
  179. }
  180. /*
  181. * Initialize system. Setup memory and reserve regions.
  182. */
  183. extern char _end;
  184. extern char _stext;
  185. extern char _WindowVectors_text_start;
  186. extern char _WindowVectors_text_end;
  187. extern char _DebugInterruptVector_literal_start;
  188. extern char _DebugInterruptVector_text_end;
  189. extern char _KernelExceptionVector_literal_start;
  190. extern char _KernelExceptionVector_text_end;
  191. extern char _UserExceptionVector_literal_start;
  192. extern char _UserExceptionVector_text_end;
  193. extern char _DoubleExceptionVector_literal_start;
  194. extern char _DoubleExceptionVector_text_end;
  195. void __init setup_arch(char **cmdline_p)
  196. {
  197. extern int mem_reserve(unsigned long, unsigned long, int);
  198. extern void bootmem_init(void);
  199. memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
  200. boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
  201. *cmdline_p = command_line;
  202. /* Reserve some memory regions */
  203. #ifdef CONFIG_BLK_DEV_INITRD
  204. if (initrd_start < initrd_end) {
  205. initrd_is_mapped = mem_reserve(__pa(initrd_start),
  206. __pa(initrd_end), 0);
  207. initrd_below_start_ok = 1;
  208. } else {
  209. initrd_start = 0;
  210. }
  211. #endif
  212. mem_reserve(__pa(&_stext),__pa(&_end), 1);
  213. mem_reserve(__pa(&_WindowVectors_text_start),
  214. __pa(&_WindowVectors_text_end), 0);
  215. mem_reserve(__pa(&_DebugInterruptVector_literal_start),
  216. __pa(&_DebugInterruptVector_text_end), 0);
  217. mem_reserve(__pa(&_KernelExceptionVector_literal_start),
  218. __pa(&_KernelExceptionVector_text_end), 0);
  219. mem_reserve(__pa(&_UserExceptionVector_literal_start),
  220. __pa(&_UserExceptionVector_text_end), 0);
  221. mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
  222. __pa(&_DoubleExceptionVector_text_end), 0);
  223. bootmem_init();
  224. platform_setup(cmdline_p);
  225. paging_init();
  226. zones_init();
  227. #ifdef CONFIG_VT
  228. # if defined(CONFIG_VGA_CONSOLE)
  229. conswitchp = &vga_con;
  230. # elif defined(CONFIG_DUMMY_CONSOLE)
  231. conswitchp = &dummy_con;
  232. # endif
  233. #endif
  234. #ifdef CONFIG_PCI
  235. platform_pcibios_init();
  236. #endif
  237. }
  238. void machine_restart(char * cmd)
  239. {
  240. platform_restart();
  241. }
  242. void machine_halt(void)
  243. {
  244. platform_halt();
  245. while (1);
  246. }
  247. void machine_power_off(void)
  248. {
  249. platform_power_off();
  250. while (1);
  251. }
  252. #ifdef CONFIG_PROC_FS
  253. /*
  254. * Display some core information through /proc/cpuinfo.
  255. */
  256. static int
  257. c_show(struct seq_file *f, void *slot)
  258. {
  259. /* high-level stuff */
  260. seq_printf(f,"processor\t: 0\n"
  261. "vendor_id\t: Tensilica\n"
  262. "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
  263. "core ID\t\t: " XCHAL_CORE_ID "\n"
  264. "build ID\t: 0x%x\n"
  265. "byte order\t: %s\n"
  266. "cpu MHz\t\t: %lu.%02lu\n"
  267. "bogomips\t: %lu.%02lu\n",
  268. XCHAL_BUILD_UNIQUE_ID,
  269. XCHAL_HAVE_BE ? "big" : "little",
  270. CCOUNT_PER_JIFFY/(1000000/HZ),
  271. (CCOUNT_PER_JIFFY/(10000/HZ)) % 100,
  272. loops_per_jiffy/(500000/HZ),
  273. (loops_per_jiffy/(5000/HZ)) % 100);
  274. seq_printf(f,"flags\t\t: "
  275. #if XCHAL_HAVE_NMI
  276. "nmi "
  277. #endif
  278. #if XCHAL_HAVE_DEBUG
  279. "debug "
  280. # if XCHAL_HAVE_OCD
  281. "ocd "
  282. # endif
  283. #endif
  284. #if XCHAL_HAVE_DENSITY
  285. "density "
  286. #endif
  287. #if XCHAL_HAVE_BOOLEANS
  288. "boolean "
  289. #endif
  290. #if XCHAL_HAVE_LOOPS
  291. "loop "
  292. #endif
  293. #if XCHAL_HAVE_NSA
  294. "nsa "
  295. #endif
  296. #if XCHAL_HAVE_MINMAX
  297. "minmax "
  298. #endif
  299. #if XCHAL_HAVE_SEXT
  300. "sext "
  301. #endif
  302. #if XCHAL_HAVE_CLAMPS
  303. "clamps "
  304. #endif
  305. #if XCHAL_HAVE_MAC16
  306. "mac16 "
  307. #endif
  308. #if XCHAL_HAVE_MUL16
  309. "mul16 "
  310. #endif
  311. #if XCHAL_HAVE_MUL32
  312. "mul32 "
  313. #endif
  314. #if XCHAL_HAVE_MUL32_HIGH
  315. "mul32h "
  316. #endif
  317. #if XCHAL_HAVE_FP
  318. "fpu "
  319. #endif
  320. "\n");
  321. /* Registers. */
  322. seq_printf(f,"physical aregs\t: %d\n"
  323. "misc regs\t: %d\n"
  324. "ibreak\t\t: %d\n"
  325. "dbreak\t\t: %d\n",
  326. XCHAL_NUM_AREGS,
  327. XCHAL_NUM_MISC_REGS,
  328. XCHAL_NUM_IBREAK,
  329. XCHAL_NUM_DBREAK);
  330. /* Interrupt. */
  331. seq_printf(f,"num ints\t: %d\n"
  332. "ext ints\t: %d\n"
  333. "int levels\t: %d\n"
  334. "timers\t\t: %d\n"
  335. "debug level\t: %d\n",
  336. XCHAL_NUM_INTERRUPTS,
  337. XCHAL_NUM_EXTINTERRUPTS,
  338. XCHAL_NUM_INTLEVELS,
  339. XCHAL_NUM_TIMERS,
  340. XCHAL_DEBUGLEVEL);
  341. /* Cache */
  342. seq_printf(f,"icache line size: %d\n"
  343. "icache ways\t: %d\n"
  344. "icache size\t: %d\n"
  345. "icache flags\t: "
  346. #if XCHAL_ICACHE_LINE_LOCKABLE
  347. "lock"
  348. #endif
  349. "\n"
  350. "dcache line size: %d\n"
  351. "dcache ways\t: %d\n"
  352. "dcache size\t: %d\n"
  353. "dcache flags\t: "
  354. #if XCHAL_DCACHE_IS_WRITEBACK
  355. "writeback"
  356. #endif
  357. #if XCHAL_DCACHE_LINE_LOCKABLE
  358. "lock"
  359. #endif
  360. "\n",
  361. XCHAL_ICACHE_LINESIZE,
  362. XCHAL_ICACHE_WAYS,
  363. XCHAL_ICACHE_SIZE,
  364. XCHAL_DCACHE_LINESIZE,
  365. XCHAL_DCACHE_WAYS,
  366. XCHAL_DCACHE_SIZE);
  367. return 0;
  368. }
  369. /*
  370. * We show only CPU #0 info.
  371. */
  372. static void *
  373. c_start(struct seq_file *f, loff_t *pos)
  374. {
  375. return (void *) ((*pos == 0) ? (void *)1 : NULL);
  376. }
  377. static void *
  378. c_next(struct seq_file *f, void *v, loff_t *pos)
  379. {
  380. return NULL;
  381. }
  382. static void
  383. c_stop(struct seq_file *f, void *v)
  384. {
  385. }
  386. const struct seq_operations cpuinfo_op =
  387. {
  388. start: c_start,
  389. next: c_next,
  390. stop: c_stop,
  391. show: c_show
  392. };
  393. #endif /* CONFIG_PROC_FS */