setup-sh7705.c 5.5 KB

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  1. /*
  2. * SH7705 Setup
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2007 Nobuhiro Iwamatsu
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/init.h>
  13. #include <linux/irq.h>
  14. #include <linux/serial.h>
  15. #include <linux/serial_sci.h>
  16. #include <linux/sh_timer.h>
  17. #include <asm/rtc.h>
  18. enum {
  19. UNUSED = 0,
  20. /* interrupt sources */
  21. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  22. PINT07, PINT815,
  23. DMAC, SCIF0, SCIF2, ADC_ADI, USB,
  24. TPU0, TPU1, TPU2, TPU3,
  25. TMU0, TMU1, TMU2,
  26. RTC, WDT, REF_RCMI,
  27. };
  28. static struct intc_vect vectors[] __initdata = {
  29. /* IRQ0->5 are handled in setup-sh3.c */
  30. INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  31. INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
  32. INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
  33. INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
  34. INTC_VECT(SCIF0, 0x8e0),
  35. INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
  36. INTC_VECT(SCIF2, 0x960),
  37. INTC_VECT(ADC_ADI, 0x980),
  38. INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
  39. INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
  40. INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
  41. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  42. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  43. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  44. INTC_VECT(RTC, 0x4c0),
  45. INTC_VECT(WDT, 0x560),
  46. INTC_VECT(REF_RCMI, 0x580),
  47. };
  48. static struct intc_prio_reg prio_registers[] __initdata = {
  49. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  50. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
  51. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  52. { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
  53. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
  54. { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
  55. { 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
  56. { 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
  57. };
  58. static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
  59. NULL, prio_registers, NULL);
  60. static struct plat_sci_port scif0_platform_data = {
  61. .mapbase = 0xa4410000,
  62. .flags = UPF_BOOT_AUTOCONF,
  63. .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
  64. SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
  65. .scbrr_algo_id = SCBRR_ALGO_4,
  66. .type = PORT_SCIF,
  67. .irqs = { 56, 56, 56 },
  68. };
  69. static struct platform_device scif0_device = {
  70. .name = "sh-sci",
  71. .id = 0,
  72. .dev = {
  73. .platform_data = &scif0_platform_data,
  74. },
  75. };
  76. static struct plat_sci_port scif1_platform_data = {
  77. .mapbase = 0xa4400000,
  78. .flags = UPF_BOOT_AUTOCONF,
  79. .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
  80. .scbrr_algo_id = SCBRR_ALGO_4,
  81. .type = PORT_SCIF,
  82. .irqs = { 52, 52, 52 },
  83. };
  84. static struct platform_device scif1_device = {
  85. .name = "sh-sci",
  86. .id = 1,
  87. .dev = {
  88. .platform_data = &scif1_platform_data,
  89. },
  90. };
  91. static struct resource rtc_resources[] = {
  92. [0] = {
  93. .start = 0xfffffec0,
  94. .end = 0xfffffec0 + 0x1e,
  95. .flags = IORESOURCE_IO,
  96. },
  97. [1] = {
  98. .start = 20,
  99. .flags = IORESOURCE_IRQ,
  100. },
  101. };
  102. static struct sh_rtc_platform_info rtc_info = {
  103. .capabilities = RTC_CAP_4_DIGIT_YEAR,
  104. };
  105. static struct platform_device rtc_device = {
  106. .name = "sh-rtc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(rtc_resources),
  109. .resource = rtc_resources,
  110. .dev = {
  111. .platform_data = &rtc_info,
  112. },
  113. };
  114. static struct sh_timer_config tmu0_platform_data = {
  115. .channel_offset = 0x02,
  116. .timer_bit = 0,
  117. .clockevent_rating = 200,
  118. };
  119. static struct resource tmu0_resources[] = {
  120. [0] = {
  121. .start = 0xfffffe94,
  122. .end = 0xfffffe9f,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = 16,
  127. .flags = IORESOURCE_IRQ,
  128. },
  129. };
  130. static struct platform_device tmu0_device = {
  131. .name = "sh_tmu",
  132. .id = 0,
  133. .dev = {
  134. .platform_data = &tmu0_platform_data,
  135. },
  136. .resource = tmu0_resources,
  137. .num_resources = ARRAY_SIZE(tmu0_resources),
  138. };
  139. static struct sh_timer_config tmu1_platform_data = {
  140. .channel_offset = 0xe,
  141. .timer_bit = 1,
  142. .clocksource_rating = 200,
  143. };
  144. static struct resource tmu1_resources[] = {
  145. [0] = {
  146. .start = 0xfffffea0,
  147. .end = 0xfffffeab,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. [1] = {
  151. .start = 17,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static struct platform_device tmu1_device = {
  156. .name = "sh_tmu",
  157. .id = 1,
  158. .dev = {
  159. .platform_data = &tmu1_platform_data,
  160. },
  161. .resource = tmu1_resources,
  162. .num_resources = ARRAY_SIZE(tmu1_resources),
  163. };
  164. static struct sh_timer_config tmu2_platform_data = {
  165. .channel_offset = 0x1a,
  166. .timer_bit = 2,
  167. };
  168. static struct resource tmu2_resources[] = {
  169. [0] = {
  170. .start = 0xfffffeac,
  171. .end = 0xfffffebb,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. [1] = {
  175. .start = 18,
  176. .flags = IORESOURCE_IRQ,
  177. },
  178. };
  179. static struct platform_device tmu2_device = {
  180. .name = "sh_tmu",
  181. .id = 2,
  182. .dev = {
  183. .platform_data = &tmu2_platform_data,
  184. },
  185. .resource = tmu2_resources,
  186. .num_resources = ARRAY_SIZE(tmu2_resources),
  187. };
  188. static struct platform_device *sh7705_devices[] __initdata = {
  189. &scif0_device,
  190. &scif1_device,
  191. &tmu0_device,
  192. &tmu1_device,
  193. &tmu2_device,
  194. &rtc_device,
  195. };
  196. static int __init sh7705_devices_setup(void)
  197. {
  198. return platform_add_devices(sh7705_devices,
  199. ARRAY_SIZE(sh7705_devices));
  200. }
  201. arch_initcall(sh7705_devices_setup);
  202. static struct platform_device *sh7705_early_devices[] __initdata = {
  203. &scif0_device,
  204. &scif1_device,
  205. &tmu0_device,
  206. &tmu1_device,
  207. &tmu2_device,
  208. };
  209. void __init plat_early_device_setup(void)
  210. {
  211. early_platform_add_devices(sh7705_early_devices,
  212. ARRAY_SIZE(sh7705_early_devices));
  213. }
  214. void __init plat_irq_setup(void)
  215. {
  216. register_intc_controller(&intc_desc);
  217. plat_irq_setup_sh3();
  218. }