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amlogic-aml8726-mx-kernel
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amlogic-aml8...
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arch
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sh
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include
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asm
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dma-sh.h

dma-sh.h 2.2 KB
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  1. /*
    2. 

  2.  * arch/sh/include/asm/dma-sh.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2000  Takashi YOSHII
    5. 

  5.  * Copyright (C) 2003  Paul Mundt
    6. 

  6.  *
    7. 

  7.  * This file is subject to the terms and conditions of the GNU General Public
    8. 

  8.  * License.  See the file "COPYING" in the main directory of this archive
    9. 

  9.  * for more details.
    10. 

  10.  */
    11. 

  11. #ifndef __DMA_SH_H
    12. 

  12. #define __DMA_SH_H
    13. 

  13. 

  14. #include <asm/dma-register.h>
    15. 

  15. #include <cpu/dma-register.h>
    16. 

  16. #include <cpu/dma.h>
    17. 

  17. 

  18. /* DMAOR contorl: The DMAOR access size is different by CPU.*/
    19. 

  19. #if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
    20. 

  20.     defined(CONFIG_CPU_SUBTYPE_SH7724)	|| \
    21. 

  21.     defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
    22. 

  22.     defined(CONFIG_CPU_SUBTYPE_SH7785)
    23. 

  23. #define dmaor_read_reg(n) \
    24. 

  24.     (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
    25. 

  25. 	: __raw_readw(SH_DMAC_BASE0 + DMAOR))
    26. 

  26. #define dmaor_write_reg(n, data) \
    27. 

  27.     (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
    28. 

  28.     : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
    29. 

  29. #else /* Other CPU */
    30. 

  30. #define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
    31. 

  31. #define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
    32. 

  32. #endif
    33. 

  33. 

  34. static int dmte_irq_map[] __maybe_unused = {
    35. 

  35. #if (MAX_DMA_CHANNELS >= 4)
    36. 

  36.     DMTE0_IRQ,
    37. 

  37.     DMTE0_IRQ + 1,
    38. 

  38.     DMTE0_IRQ + 2,
    39. 

  39.     DMTE0_IRQ + 3,
    40. 

  40. #endif
    41. 

  41. #if (MAX_DMA_CHANNELS >= 6)
    42. 

  42.     DMTE4_IRQ,
    43. 

  43.     DMTE4_IRQ + 1,
    44. 

  44. #endif
    45. 

  45. #if (MAX_DMA_CHANNELS >= 8)
    46. 

  46.     DMTE6_IRQ,
    47. 

  47.     DMTE6_IRQ + 1,
    48. 

  48. #endif
    49. 

  49. #if (MAX_DMA_CHANNELS >= 12)
    50. 

  50.     DMTE8_IRQ,
    51. 

  51.     DMTE9_IRQ,
    52. 

  52.     DMTE10_IRQ,
    53. 

  53.     DMTE11_IRQ,
    54. 

  54. #endif
    55. 

  55. };
    56. 

  56. 

  57. /*
    58. 

  58.  * Define the default configuration for dual address memory-memory transfer.
    59. 

  59.  * The 0x400 value represents auto-request, external->external.
    60. 

  60.  */
    61. 

  61. #define RS_DUAL	(DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
    62. 

  62. 

  63. /* DMA base address */
    64. 

  64. static u32 dma_base_addr[] __maybe_unused = {
    65. 

  65. #if (MAX_DMA_CHANNELS >= 4)
    66. 

  66. 	SH_DMAC_BASE0 + 0x00,	/* channel 0 */
    67. 

  67. 	SH_DMAC_BASE0 + 0x10,
    68. 

  68. 	SH_DMAC_BASE0 + 0x20,
    69. 

  69. 	SH_DMAC_BASE0 + 0x30,
    70. 

  70. #endif
    71. 

  71. #if (MAX_DMA_CHANNELS >= 6)
    72. 

  72. 	SH_DMAC_BASE0 + 0x50,
    73. 

  73. 	SH_DMAC_BASE0 + 0x60,
    74. 

  74. #endif
    75. 

  75. #if (MAX_DMA_CHANNELS >= 8)
    76. 

  76. 	SH_DMAC_BASE1 + 0x00,
    77. 

  77. 	SH_DMAC_BASE1 + 0x10,
    78. 

  78. #endif
    79. 

  79. #if (MAX_DMA_CHANNELS >= 12)
    80. 

  80. 	SH_DMAC_BASE1 + 0x20,
    81. 

  81. 	SH_DMAC_BASE1 + 0x30,
    82. 

  82. 	SH_DMAC_BASE1 + 0x50,
    83. 

  83. 	SH_DMAC_BASE1 + 0x60, /* channel 11 */
    84. 

  84. #endif
    85. 

  85. };
    86. 

  86. 

  87. #endif /* __DMA_SH_H */
    88. 

  88.