sbc8560.c 7.6 KB

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  1. /*
  2. * Wind River SBC8560 setup and early boot code.
  3. *
  4. * Copyright 2007 Wind River Systems Inc.
  5. *
  6. * By Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/stddef.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/delay.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/system.h>
  23. #include <asm/time.h>
  24. #include <asm/machdep.h>
  25. #include <asm/pci-bridge.h>
  26. #include <asm/mpic.h>
  27. #include <mm/mmu_decl.h>
  28. #include <asm/udbg.h>
  29. #include <sysdev/fsl_soc.h>
  30. #include <sysdev/fsl_pci.h>
  31. #ifdef CONFIG_CPM2
  32. #include <asm/cpm2.h>
  33. #include <sysdev/cpm2_pic.h>
  34. #endif
  35. #ifdef CONFIG_CPM2
  36. static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
  37. {
  38. struct irq_chip *chip = irq_desc_get_chip(desc);
  39. int cascade_irq;
  40. while ((cascade_irq = cpm2_get_irq()) >= 0)
  41. generic_handle_irq(cascade_irq);
  42. chip->irq_eoi(&desc->irq_data);
  43. }
  44. #endif /* CONFIG_CPM2 */
  45. static void __init sbc8560_pic_init(void)
  46. {
  47. struct mpic *mpic;
  48. struct resource r;
  49. struct device_node *np = NULL;
  50. #ifdef CONFIG_CPM2
  51. int irq;
  52. #endif
  53. np = of_find_node_by_type(np, "open-pic");
  54. if (!np) {
  55. printk(KERN_ERR "Could not find open-pic node\n");
  56. return;
  57. }
  58. if (of_address_to_resource(np, 0, &r)) {
  59. printk(KERN_ERR "Could not map mpic register space\n");
  60. of_node_put(np);
  61. return;
  62. }
  63. mpic = mpic_alloc(np, r.start,
  64. MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  65. 0, 256, " OpenPIC ");
  66. BUG_ON(mpic == NULL);
  67. of_node_put(np);
  68. mpic_init(mpic);
  69. #ifdef CONFIG_CPM2
  70. /* Setup CPM2 PIC */
  71. np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
  72. if (np == NULL) {
  73. printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
  74. return;
  75. }
  76. irq = irq_of_parse_and_map(np, 0);
  77. cpm2_pic_init(np);
  78. of_node_put(np);
  79. irq_set_chained_handler(irq, cpm2_cascade);
  80. #endif
  81. }
  82. /*
  83. * Setup the architecture
  84. */
  85. #ifdef CONFIG_CPM2
  86. struct cpm_pin {
  87. int port, pin, flags;
  88. };
  89. static const struct cpm_pin sbc8560_pins[] = {
  90. /* SCC1 */
  91. {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  92. {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  93. {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  94. /* SCC2 */
  95. {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  96. {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  97. {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  98. /* FCC2 */
  99. {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  100. {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  101. {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  102. {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  103. {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  104. {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  105. {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  106. {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  107. {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  108. {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  109. {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  110. {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  111. {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  112. {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  113. {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  114. {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
  115. /* FCC3 */
  116. {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  117. {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  118. {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  119. {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  120. {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  121. {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  122. {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  123. {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  124. {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  125. {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  126. {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  127. {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  128. {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  129. {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  130. {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
  131. {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
  132. };
  133. static void __init init_ioports(void)
  134. {
  135. int i;
  136. for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
  137. const struct cpm_pin *pin = &sbc8560_pins[i];
  138. cpm2_set_pin(pin->port, pin->pin, pin->flags);
  139. }
  140. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
  141. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
  142. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
  143. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
  144. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
  145. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
  146. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
  147. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
  148. }
  149. #endif
  150. static void __init sbc8560_setup_arch(void)
  151. {
  152. #ifdef CONFIG_PCI
  153. struct device_node *np;
  154. #endif
  155. if (ppc_md.progress)
  156. ppc_md.progress("sbc8560_setup_arch()", 0);
  157. #ifdef CONFIG_CPM2
  158. cpm2_reset();
  159. init_ioports();
  160. #endif
  161. #ifdef CONFIG_PCI
  162. for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
  163. fsl_add_bridge(np, 1);
  164. #endif
  165. }
  166. static void sbc8560_show_cpuinfo(struct seq_file *m)
  167. {
  168. uint pvid, svid, phid1;
  169. pvid = mfspr(SPRN_PVR);
  170. svid = mfspr(SPRN_SVR);
  171. seq_printf(m, "Vendor\t\t: Wind River\n");
  172. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  173. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  174. /* Display cpu Pll setting */
  175. phid1 = mfspr(SPRN_HID1);
  176. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  177. }
  178. static struct of_device_id __initdata of_bus_ids[] = {
  179. { .name = "soc", },
  180. { .type = "soc", },
  181. { .name = "cpm", },
  182. { .name = "localbus", },
  183. { .compatible = "simple-bus", },
  184. { .compatible = "gianfar", },
  185. {},
  186. };
  187. static int __init declare_of_platform_devices(void)
  188. {
  189. of_platform_bus_probe(NULL, of_bus_ids, NULL);
  190. return 0;
  191. }
  192. machine_device_initcall(sbc8560, declare_of_platform_devices);
  193. /*
  194. * Called very early, device-tree isn't unflattened
  195. */
  196. static int __init sbc8560_probe(void)
  197. {
  198. unsigned long root = of_get_flat_dt_root();
  199. return of_flat_dt_is_compatible(root, "SBC8560");
  200. }
  201. #ifdef CONFIG_RTC_DRV_M48T59
  202. static int __init sbc8560_rtc_init(void)
  203. {
  204. struct device_node *np;
  205. struct resource res;
  206. struct platform_device *rtc_dev;
  207. np = of_find_compatible_node(NULL, NULL, "m48t59");
  208. if (np == NULL) {
  209. printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
  210. return -ENODEV;
  211. }
  212. of_address_to_resource(np, 0, &res);
  213. of_node_put(np);
  214. printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
  215. rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
  216. if (IS_ERR(rtc_dev)) {
  217. printk("Registering sbc8560 RTC device failed\n");
  218. return PTR_ERR(rtc_dev);
  219. }
  220. return 0;
  221. }
  222. arch_initcall(sbc8560_rtc_init);
  223. #endif /* M48T59 */
  224. static __u8 __iomem *brstcr;
  225. static int __init sbc8560_bdrstcr_init(void)
  226. {
  227. struct device_node *np;
  228. struct resource res;
  229. np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
  230. if (np == NULL) {
  231. printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
  232. return -ENODEV;
  233. }
  234. of_address_to_resource(np, 0, &res);
  235. printk(KERN_INFO "sbc8560: Found BRSTCR at i/o 0x%x\n", res.start);
  236. brstcr = ioremap(res.start, res.end - res.start);
  237. if(!brstcr)
  238. printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
  239. of_node_put(np);
  240. return 0;
  241. }
  242. arch_initcall(sbc8560_bdrstcr_init);
  243. void sbc8560_rstcr_restart(char * cmd)
  244. {
  245. local_irq_disable();
  246. if(brstcr)
  247. clrbits8(brstcr, 0x80);
  248. while(1);
  249. }
  250. define_machine(sbc8560) {
  251. .name = "SBC8560",
  252. .probe = sbc8560_probe,
  253. .setup_arch = sbc8560_setup_arch,
  254. .init_IRQ = sbc8560_pic_init,
  255. .show_cpuinfo = sbc8560_show_cpuinfo,
  256. .get_irq = mpic_get_irq,
  257. .restart = sbc8560_rstcr_restart,
  258. .calibrate_decr = generic_calibrate_decr,
  259. .progress = udbg_progress,
  260. };