sbc8641d.dts 10 KB

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  1. /*
  2. * SBC8641D Device Tree Source
  3. *
  4. * Copyright 2008 Wind River Systems Inc.
  5. *
  6. * Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. /dts-v1/;
  16. / {
  17. model = "SBC8641D";
  18. compatible = "wind,sbc8641";
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. aliases {
  22. ethernet0 = &enet0;
  23. ethernet1 = &enet1;
  24. ethernet2 = &enet2;
  25. ethernet3 = &enet3;
  26. serial0 = &serial0;
  27. serial1 = &serial1;
  28. pci0 = &pci0;
  29. pci1 = &pci1;
  30. };
  31. cpus {
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. PowerPC,8641@0 {
  35. device_type = "cpu";
  36. reg = <0>;
  37. d-cache-line-size = <32>;
  38. i-cache-line-size = <32>;
  39. d-cache-size = <32768>; // L1
  40. i-cache-size = <32768>; // L1
  41. timebase-frequency = <0>; // From uboot
  42. bus-frequency = <0>; // From uboot
  43. clock-frequency = <0>; // From uboot
  44. };
  45. PowerPC,8641@1 {
  46. device_type = "cpu";
  47. reg = <1>;
  48. d-cache-line-size = <32>;
  49. i-cache-line-size = <32>;
  50. d-cache-size = <32768>;
  51. i-cache-size = <32768>;
  52. timebase-frequency = <0>; // From uboot
  53. bus-frequency = <0>; // From uboot
  54. clock-frequency = <0>; // From uboot
  55. };
  56. };
  57. memory {
  58. device_type = "memory";
  59. reg = <0x00000000 0x20000000>; // 512M at 0x0
  60. };
  61. localbus@f8005000 {
  62. #address-cells = <2>;
  63. #size-cells = <1>;
  64. compatible = "fsl,mpc8641-localbus", "simple-bus";
  65. reg = <0xf8005000 0x1000>;
  66. interrupts = <19 2>;
  67. interrupt-parent = <&mpic>;
  68. ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
  69. 1 0 0xf0000000 0x00010000 // 64KB EEPROM
  70. 2 0 0xf1000000 0x00100000 // EPLD (1MB)
  71. 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
  72. 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
  73. 6 0 0xf4000000 0x00100000 // LCD display (1MB)
  74. 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
  75. flash@0,0 {
  76. compatible = "cfi-flash";
  77. reg = <0 0 0x01000000>;
  78. bank-width = <2>;
  79. device-width = <2>;
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. partition@0 {
  83. label = "dtb";
  84. reg = <0x00000000 0x00100000>;
  85. read-only;
  86. };
  87. partition@300000 {
  88. label = "kernel";
  89. reg = <0x00100000 0x00400000>;
  90. read-only;
  91. };
  92. partition@400000 {
  93. label = "fs";
  94. reg = <0x00500000 0x00a00000>;
  95. };
  96. partition@700000 {
  97. label = "firmware";
  98. reg = <0x00f00000 0x00100000>;
  99. read-only;
  100. };
  101. };
  102. epld@2,0 {
  103. compatible = "wrs,epld-localbus";
  104. #address-cells = <2>;
  105. #size-cells = <1>;
  106. reg = <2 0 0x100000>;
  107. ranges = <0 0 5 0 1 // User switches
  108. 1 0 5 1 1 // Board ID/Rev
  109. 3 0 5 3 1>; // LEDs
  110. };
  111. };
  112. soc@f8000000 {
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. device_type = "soc";
  116. compatible = "simple-bus";
  117. ranges = <0x00000000 0xf8000000 0x00100000>;
  118. bus-frequency = <0>;
  119. mcm-law@0 {
  120. compatible = "fsl,mcm-law";
  121. reg = <0x0 0x1000>;
  122. fsl,num-laws = <10>;
  123. };
  124. mcm@1000 {
  125. compatible = "fsl,mpc8641-mcm", "fsl,mcm";
  126. reg = <0x1000 0x1000>;
  127. interrupts = <17 2>;
  128. interrupt-parent = <&mpic>;
  129. };
  130. i2c@3000 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. cell-index = <0>;
  134. compatible = "fsl-i2c";
  135. reg = <0x3000 0x100>;
  136. interrupts = <43 2>;
  137. interrupt-parent = <&mpic>;
  138. dfsrr;
  139. };
  140. i2c@3100 {
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. cell-index = <1>;
  144. compatible = "fsl-i2c";
  145. reg = <0x3100 0x100>;
  146. interrupts = <43 2>;
  147. interrupt-parent = <&mpic>;
  148. dfsrr;
  149. };
  150. dma@21300 {
  151. #address-cells = <1>;
  152. #size-cells = <1>;
  153. compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
  154. reg = <0x21300 0x4>;
  155. ranges = <0x0 0x21100 0x200>;
  156. cell-index = <0>;
  157. dma-channel@0 {
  158. compatible = "fsl,mpc8641-dma-channel",
  159. "fsl,eloplus-dma-channel";
  160. reg = <0x0 0x80>;
  161. cell-index = <0>;
  162. interrupt-parent = <&mpic>;
  163. interrupts = <20 2>;
  164. };
  165. dma-channel@80 {
  166. compatible = "fsl,mpc8641-dma-channel",
  167. "fsl,eloplus-dma-channel";
  168. reg = <0x80 0x80>;
  169. cell-index = <1>;
  170. interrupt-parent = <&mpic>;
  171. interrupts = <21 2>;
  172. };
  173. dma-channel@100 {
  174. compatible = "fsl,mpc8641-dma-channel",
  175. "fsl,eloplus-dma-channel";
  176. reg = <0x100 0x80>;
  177. cell-index = <2>;
  178. interrupt-parent = <&mpic>;
  179. interrupts = <22 2>;
  180. };
  181. dma-channel@180 {
  182. compatible = "fsl,mpc8641-dma-channel",
  183. "fsl,eloplus-dma-channel";
  184. reg = <0x180 0x80>;
  185. cell-index = <3>;
  186. interrupt-parent = <&mpic>;
  187. interrupts = <23 2>;
  188. };
  189. };
  190. enet0: ethernet@24000 {
  191. #address-cells = <1>;
  192. #size-cells = <1>;
  193. cell-index = <0>;
  194. device_type = "network";
  195. model = "TSEC";
  196. compatible = "gianfar";
  197. reg = <0x24000 0x1000>;
  198. ranges = <0x0 0x24000 0x1000>;
  199. local-mac-address = [ 00 00 00 00 00 00 ];
  200. interrupts = <29 2 30 2 34 2>;
  201. interrupt-parent = <&mpic>;
  202. tbi-handle = <&tbi0>;
  203. phy-handle = <&phy0>;
  204. phy-connection-type = "rgmii-id";
  205. mdio@520 {
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. compatible = "fsl,gianfar-mdio";
  209. reg = <0x520 0x20>;
  210. phy0: ethernet-phy@1f {
  211. interrupt-parent = <&mpic>;
  212. interrupts = <10 1>;
  213. reg = <0x1f>;
  214. device_type = "ethernet-phy";
  215. };
  216. phy1: ethernet-phy@0 {
  217. interrupt-parent = <&mpic>;
  218. interrupts = <10 1>;
  219. reg = <0>;
  220. device_type = "ethernet-phy";
  221. };
  222. phy2: ethernet-phy@1 {
  223. interrupt-parent = <&mpic>;
  224. interrupts = <10 1>;
  225. reg = <1>;
  226. device_type = "ethernet-phy";
  227. };
  228. phy3: ethernet-phy@2 {
  229. interrupt-parent = <&mpic>;
  230. interrupts = <10 1>;
  231. reg = <2>;
  232. device_type = "ethernet-phy";
  233. };
  234. tbi0: tbi-phy@11 {
  235. reg = <0x11>;
  236. device_type = "tbi-phy";
  237. };
  238. };
  239. };
  240. enet1: ethernet@25000 {
  241. #address-cells = <1>;
  242. #size-cells = <1>;
  243. cell-index = <1>;
  244. device_type = "network";
  245. model = "TSEC";
  246. compatible = "gianfar";
  247. reg = <0x25000 0x1000>;
  248. ranges = <0x0 0x25000 0x1000>;
  249. local-mac-address = [ 00 00 00 00 00 00 ];
  250. interrupts = <35 2 36 2 40 2>;
  251. interrupt-parent = <&mpic>;
  252. tbi-handle = <&tbi1>;
  253. phy-handle = <&phy1>;
  254. phy-connection-type = "rgmii-id";
  255. mdio@520 {
  256. #address-cells = <1>;
  257. #size-cells = <0>;
  258. compatible = "fsl,gianfar-tbi";
  259. reg = <0x520 0x20>;
  260. tbi1: tbi-phy@11 {
  261. reg = <0x11>;
  262. device_type = "tbi-phy";
  263. };
  264. };
  265. };
  266. enet2: ethernet@26000 {
  267. #address-cells = <1>;
  268. #size-cells = <1>;
  269. cell-index = <2>;
  270. device_type = "network";
  271. model = "TSEC";
  272. compatible = "gianfar";
  273. reg = <0x26000 0x1000>;
  274. ranges = <0x0 0x26000 0x1000>;
  275. local-mac-address = [ 00 00 00 00 00 00 ];
  276. interrupts = <31 2 32 2 33 2>;
  277. interrupt-parent = <&mpic>;
  278. tbi-handle = <&tbi2>;
  279. phy-handle = <&phy2>;
  280. phy-connection-type = "rgmii-id";
  281. mdio@520 {
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. compatible = "fsl,gianfar-tbi";
  285. reg = <0x520 0x20>;
  286. tbi2: tbi-phy@11 {
  287. reg = <0x11>;
  288. device_type = "tbi-phy";
  289. };
  290. };
  291. };
  292. enet3: ethernet@27000 {
  293. #address-cells = <1>;
  294. #size-cells = <1>;
  295. cell-index = <3>;
  296. device_type = "network";
  297. model = "TSEC";
  298. compatible = "gianfar";
  299. reg = <0x27000 0x1000>;
  300. ranges = <0x0 0x27000 0x1000>;
  301. local-mac-address = [ 00 00 00 00 00 00 ];
  302. interrupts = <37 2 38 2 39 2>;
  303. interrupt-parent = <&mpic>;
  304. tbi-handle = <&tbi3>;
  305. phy-handle = <&phy3>;
  306. phy-connection-type = "rgmii-id";
  307. mdio@520 {
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. compatible = "fsl,gianfar-tbi";
  311. reg = <0x520 0x20>;
  312. tbi3: tbi-phy@11 {
  313. reg = <0x11>;
  314. device_type = "tbi-phy";
  315. };
  316. };
  317. };
  318. serial0: serial@4500 {
  319. cell-index = <0>;
  320. device_type = "serial";
  321. compatible = "ns16550";
  322. reg = <0x4500 0x100>;
  323. clock-frequency = <0>;
  324. interrupts = <42 2>;
  325. interrupt-parent = <&mpic>;
  326. };
  327. serial1: serial@4600 {
  328. cell-index = <1>;
  329. device_type = "serial";
  330. compatible = "ns16550";
  331. reg = <0x4600 0x100>;
  332. clock-frequency = <0>;
  333. interrupts = <28 2>;
  334. interrupt-parent = <&mpic>;
  335. };
  336. mpic: pic@40000 {
  337. clock-frequency = <0>;
  338. interrupt-controller;
  339. #address-cells = <0>;
  340. #interrupt-cells = <2>;
  341. reg = <0x40000 0x40000>;
  342. compatible = "chrp,open-pic";
  343. device_type = "open-pic";
  344. big-endian;
  345. };
  346. global-utilities@e0000 {
  347. compatible = "fsl,mpc8641-guts";
  348. reg = <0xe0000 0x1000>;
  349. fsl,has-rstcr;
  350. };
  351. };
  352. pci0: pcie@f8008000 {
  353. compatible = "fsl,mpc8641-pcie";
  354. device_type = "pci";
  355. #interrupt-cells = <1>;
  356. #size-cells = <2>;
  357. #address-cells = <3>;
  358. reg = <0xf8008000 0x1000>;
  359. bus-range = <0x0 0xff>;
  360. ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  361. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  362. clock-frequency = <33333333>;
  363. interrupt-parent = <&mpic>;
  364. interrupts = <24 2>;
  365. interrupt-map-mask = <0xff00 0 0 7>;
  366. interrupt-map = <
  367. /* IDSEL 0x0 */
  368. 0x0000 0 0 1 &mpic 0 1
  369. 0x0000 0 0 2 &mpic 1 1
  370. 0x0000 0 0 3 &mpic 2 1
  371. 0x0000 0 0 4 &mpic 3 1
  372. >;
  373. pcie@0 {
  374. reg = <0 0 0 0 0>;
  375. #size-cells = <2>;
  376. #address-cells = <3>;
  377. device_type = "pci";
  378. ranges = <0x02000000 0x0 0x80000000
  379. 0x02000000 0x0 0x80000000
  380. 0x0 0x20000000
  381. 0x01000000 0x0 0x00000000
  382. 0x01000000 0x0 0x00000000
  383. 0x0 0x00100000>;
  384. };
  385. };
  386. pci1: pcie@f8009000 {
  387. compatible = "fsl,mpc8641-pcie";
  388. device_type = "pci";
  389. #interrupt-cells = <1>;
  390. #size-cells = <2>;
  391. #address-cells = <3>;
  392. reg = <0xf8009000 0x1000>;
  393. bus-range = <0 0xff>;
  394. ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
  395. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
  396. clock-frequency = <33333333>;
  397. interrupt-parent = <&mpic>;
  398. interrupts = <25 2>;
  399. interrupt-map-mask = <0xf800 0 0 7>;
  400. interrupt-map = <
  401. /* IDSEL 0x0 */
  402. 0x0000 0 0 1 &mpic 4 1
  403. 0x0000 0 0 2 &mpic 5 1
  404. 0x0000 0 0 3 &mpic 6 1
  405. 0x0000 0 0 4 &mpic 7 1
  406. >;
  407. pcie@0 {
  408. reg = <0 0 0 0 0>;
  409. #size-cells = <2>;
  410. #address-cells = <3>;
  411. device_type = "pci";
  412. ranges = <0x02000000 0x0 0xa0000000
  413. 0x02000000 0x0 0xa0000000
  414. 0x0 0x20000000
  415. 0x01000000 0x0 0x00000000
  416. 0x01000000 0x0 0x00000000
  417. 0x0 0x00100000>;
  418. };
  419. };
  420. };