mpc8308rdb.dts 6.7 KB

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  1. /*
  2. * MPC8308RDB Device Tree Source
  3. *
  4. * Copyright 2009 Freescale Semiconductor Inc.
  5. * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. compatible = "fsl,mpc8308rdb";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8308@0 {
  28. device_type = "cpu";
  29. reg = <0x0>;
  30. d-cache-line-size = <32>;
  31. i-cache-line-size = <32>;
  32. d-cache-size = <16384>;
  33. i-cache-size = <16384>;
  34. timebase-frequency = <0>; // from bootloader
  35. bus-frequency = <0>; // from bootloader
  36. clock-frequency = <0>; // from bootloader
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x08000000>; // 128MB at 0
  42. };
  43. localbus@e0005000 {
  44. #address-cells = <2>;
  45. #size-cells = <1>;
  46. compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
  47. reg = <0xe0005000 0x1000>;
  48. interrupts = <77 0x8>;
  49. interrupt-parent = <&ipic>;
  50. // CS0 and CS1 are swapped when
  51. // booting from nand, but the
  52. // addresses are the same.
  53. ranges = <0x0 0x0 0xfe000000 0x00800000
  54. 0x1 0x0 0xe0600000 0x00002000
  55. 0x2 0x0 0xf0000000 0x00020000
  56. 0x3 0x0 0xfa000000 0x00008000>;
  57. flash@0,0 {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. compatible = "cfi-flash";
  61. reg = <0x0 0x0 0x800000>;
  62. bank-width = <2>;
  63. device-width = <1>;
  64. u-boot@0 {
  65. reg = <0x0 0x60000>;
  66. read-only;
  67. };
  68. env@60000 {
  69. reg = <0x60000 0x10000>;
  70. };
  71. env1@70000 {
  72. reg = <0x70000 0x10000>;
  73. };
  74. kernel@80000 {
  75. reg = <0x80000 0x200000>;
  76. };
  77. dtb@280000 {
  78. reg = <0x280000 0x10000>;
  79. };
  80. ramdisk@290000 {
  81. reg = <0x290000 0x570000>;
  82. };
  83. };
  84. nand@1,0 {
  85. #address-cells = <1>;
  86. #size-cells = <1>;
  87. compatible = "fsl,mpc8315-fcm-nand",
  88. "fsl,elbc-fcm-nand";
  89. reg = <0x1 0x0 0x2000>;
  90. jffs2@0 {
  91. reg = <0x0 0x2000000>;
  92. };
  93. };
  94. };
  95. immr@e0000000 {
  96. #address-cells = <1>;
  97. #size-cells = <1>;
  98. device_type = "soc";
  99. compatible = "fsl,mpc8308-immr", "simple-bus";
  100. ranges = <0 0xe0000000 0x00100000>;
  101. reg = <0xe0000000 0x00000200>;
  102. bus-frequency = <0>;
  103. i2c@3000 {
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. cell-index = <0>;
  107. compatible = "fsl-i2c";
  108. reg = <0x3000 0x100>;
  109. interrupts = <14 0x8>;
  110. interrupt-parent = <&ipic>;
  111. dfsrr;
  112. rtc@68 {
  113. compatible = "dallas,ds1339";
  114. reg = <0x68>;
  115. };
  116. };
  117. usb@23000 {
  118. compatible = "fsl-usb2-dr";
  119. reg = <0x23000 0x1000>;
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. interrupt-parent = <&ipic>;
  123. interrupts = <38 0x8>;
  124. dr_mode = "peripheral";
  125. phy_type = "ulpi";
  126. };
  127. enet0: ethernet@24000 {
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. ranges = <0x0 0x24000 0x1000>;
  131. cell-index = <0>;
  132. device_type = "network";
  133. model = "eTSEC";
  134. compatible = "gianfar";
  135. reg = <0x24000 0x1000>;
  136. local-mac-address = [ 00 00 00 00 00 00 ];
  137. interrupts = <32 0x8 33 0x8 34 0x8>;
  138. interrupt-parent = <&ipic>;
  139. tbi-handle = < &tbi0 >;
  140. phy-handle = < &phy2 >;
  141. fsl,magic-packet;
  142. mdio@520 {
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. compatible = "fsl,gianfar-mdio";
  146. reg = <0x520 0x20>;
  147. phy2: ethernet-phy@2 {
  148. interrupt-parent = <&ipic>;
  149. interrupts = <17 0x8>;
  150. reg = <0x2>;
  151. device_type = "ethernet-phy";
  152. };
  153. tbi0: tbi-phy@11 {
  154. reg = <0x11>;
  155. device_type = "tbi-phy";
  156. };
  157. };
  158. };
  159. enet1: ethernet@25000 {
  160. #address-cells = <1>;
  161. #size-cells = <1>;
  162. cell-index = <1>;
  163. device_type = "network";
  164. model = "eTSEC";
  165. compatible = "gianfar";
  166. reg = <0x25000 0x1000>;
  167. ranges = <0x0 0x25000 0x1000>;
  168. local-mac-address = [ 00 00 00 00 00 00 ];
  169. interrupts = <35 0x8 36 0x8 37 0x8>;
  170. interrupt-parent = <&ipic>;
  171. tbi-handle = < &tbi1 >;
  172. /* Vitesse 7385 isn't on the MDIO bus */
  173. fixed-link = <1 1 1000 0 0>;
  174. fsl,magic-packet;
  175. mdio@520 {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. compatible = "fsl,gianfar-tbi";
  179. reg = <0x520 0x20>;
  180. tbi1: tbi-phy@11 {
  181. reg = <0x11>;
  182. device_type = "tbi-phy";
  183. };
  184. };
  185. };
  186. serial0: serial@4500 {
  187. cell-index = <0>;
  188. device_type = "serial";
  189. compatible = "ns16550";
  190. reg = <0x4500 0x100>;
  191. clock-frequency = <133333333>;
  192. interrupts = <9 0x8>;
  193. interrupt-parent = <&ipic>;
  194. };
  195. serial1: serial@4600 {
  196. cell-index = <1>;
  197. device_type = "serial";
  198. compatible = "ns16550";
  199. reg = <0x4600 0x100>;
  200. clock-frequency = <133333333>;
  201. interrupts = <10 0x8>;
  202. interrupt-parent = <&ipic>;
  203. };
  204. gpio@c00 {
  205. #gpio-cells = <2>;
  206. device_type = "gpio";
  207. compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
  208. reg = <0xc00 0x18>;
  209. interrupts = <74 0x8>;
  210. interrupt-parent = <&ipic>;
  211. gpio-controller;
  212. };
  213. /* IPIC
  214. * interrupts cell = <intr #, sense>
  215. * sense values match linux IORESOURCE_IRQ_* defines:
  216. * sense == 8: Level, low assertion
  217. * sense == 2: Edge, high-to-low change
  218. */
  219. ipic: interrupt-controller@700 {
  220. compatible = "fsl,ipic";
  221. interrupt-controller;
  222. #address-cells = <0>;
  223. #interrupt-cells = <2>;
  224. reg = <0x700 0x100>;
  225. device_type = "ipic";
  226. };
  227. ipic-msi@7c0 {
  228. compatible = "fsl,ipic-msi";
  229. reg = <0x7c0 0x40>;
  230. msi-available-ranges = <0x0 0x100>;
  231. interrupts = < 0x43 0x8
  232. 0x4 0x8
  233. 0x51 0x8
  234. 0x52 0x8
  235. 0x56 0x8
  236. 0x57 0x8
  237. 0x58 0x8
  238. 0x59 0x8 >;
  239. interrupt-parent = < &ipic >;
  240. };
  241. dma@2c000 {
  242. compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
  243. reg = <0x2c000 0x1800>;
  244. interrupts = <3 0x8
  245. 94 0x8>;
  246. interrupt-parent = < &ipic >;
  247. };
  248. };
  249. pci0: pcie@e0009000 {
  250. #address-cells = <3>;
  251. #size-cells = <2>;
  252. #interrupt-cells = <1>;
  253. device_type = "pci";
  254. compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
  255. reg = <0xe0009000 0x00001000
  256. 0xb0000000 0x01000000>;
  257. ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
  258. 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
  259. bus-range = <0 0>;
  260. interrupt-map-mask = <0xf800 0 0 7>;
  261. interrupt-map = <0 0 0 1 &ipic 1 8
  262. 0 0 0 2 &ipic 1 8
  263. 0 0 0 3 &ipic 1 8
  264. 0 0 0 4 &ipic 1 8>;
  265. interrupts = <0x1 0x8>;
  266. interrupt-parent = <&ipic>;
  267. clock-frequency = <0>;
  268. pcie@0 {
  269. #address-cells = <3>;
  270. #size-cells = <2>;
  271. device_type = "pci";
  272. reg = <0 0 0 0 0>;
  273. ranges = <0x02000000 0 0xa0000000
  274. 0x02000000 0 0xa0000000
  275. 0 0x10000000
  276. 0x01000000 0 0x00000000
  277. 0x01000000 0 0x00000000
  278. 0 0x00800000>;
  279. };
  280. };
  281. };