mgcoge.dts 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233
  1. /*
  2. * Device Tree for the MGCOGE plattform from keymile
  3. *
  4. * Copyright 2008 DENX Software Engineering GmbH
  5. * Heiko Schocher <hs@denx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. model = "MGCOGE";
  15. compatible = "keymile,km82xx";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. ethernet0 = &eth0;
  20. serial0 = &smc2;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. PowerPC,8247@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <32>;
  29. i-cache-line-size = <32>;
  30. d-cache-size = <16384>;
  31. i-cache-size = <16384>;
  32. timebase-frequency = <0>; /* Filled in by U-Boot */
  33. clock-frequency = <0>; /* Filled in by U-Boot */
  34. bus-frequency = <0>; /* Filled in by U-Boot */
  35. };
  36. };
  37. localbus@f0010100 {
  38. compatible = "fsl,mpc8247-localbus",
  39. "fsl,pq2-localbus",
  40. "simple-bus";
  41. #address-cells = <2>;
  42. #size-cells = <1>;
  43. reg = <0xf0010100 0x40>;
  44. ranges = <0 0 0xfe000000 0x00400000
  45. 1 0 0x30000000 0x00010000
  46. 2 0 0x40000000 0x00010000
  47. 5 0 0x50000000 0x04000000
  48. >;
  49. flash@0,0 {
  50. compatible = "cfi-flash";
  51. reg = <0 0x0 0x400000>;
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. bank-width = <1>;
  55. device-width = <1>;
  56. partition@0 {
  57. label = "u-boot";
  58. reg = <0x00000 0xC0000>;
  59. };
  60. partition@1 {
  61. label = "env";
  62. reg = <0xC0000 0x20000>;
  63. };
  64. partition@2 {
  65. label = "envred";
  66. reg = <0xE0000 0x20000>;
  67. };
  68. partition@3 {
  69. label = "free";
  70. reg = <0x100000 0x300000>;
  71. };
  72. };
  73. flash@5,0 {
  74. compatible = "cfi-flash";
  75. reg = <5 0x00000000 0x02000000
  76. 5 0x02000000 0x02000000>;
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. bank-width = <2>;
  80. partition@app { /* 64 MBytes */
  81. label = "ubi0";
  82. reg = <0x00000000 0x04000000>;
  83. };
  84. };
  85. };
  86. memory {
  87. device_type = "memory";
  88. reg = <0 0>; /* Filled in by U-Boot */
  89. };
  90. soc@f0000000 {
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus";
  94. ranges = <0x00000000 0xf0000000 0x00053000>;
  95. // Temporary until code stops depending on it.
  96. device_type = "soc";
  97. cpm@119c0 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. #interrupt-cells = <2>;
  101. compatible = "fsl,mpc8247-cpm", "fsl,cpm2",
  102. "simple-bus";
  103. reg = <0x119c0 0x30>;
  104. ranges;
  105. muram {
  106. compatible = "fsl,cpm-muram";
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. ranges = <0 0 0x10000>;
  110. data@0 {
  111. compatible = "fsl,cpm-muram-data";
  112. reg = <0x80 0x1f80 0x9800 0x800>;
  113. };
  114. };
  115. brg@119f0 {
  116. compatible = "fsl,mpc8247-brg",
  117. "fsl,cpm2-brg",
  118. "fsl,cpm-brg";
  119. reg = <0x119f0 0x10 0x115f0 0x10>;
  120. };
  121. /* Monitor port/SMC2 */
  122. smc2: serial@11a90 {
  123. device_type = "serial";
  124. compatible = "fsl,mpc8247-smc-uart",
  125. "fsl,cpm2-smc-uart";
  126. reg = <0x11a90 0x20 0x88fc 0x02>;
  127. interrupts = <5 8>;
  128. interrupt-parent = <&PIC>;
  129. fsl,cpm-brg = <2>;
  130. fsl,cpm-command = <0x21200000>;
  131. current-speed = <0>; /* Filled in by U-Boot */
  132. };
  133. eth0: ethernet@11a60 {
  134. device_type = "network";
  135. compatible = "fsl,mpc8247-scc-enet",
  136. "fsl,cpm2-scc-enet";
  137. reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>;
  138. local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
  139. interrupts = <43 8>;
  140. interrupt-parent = <&PIC>;
  141. linux,network-index = <0>;
  142. fsl,cpm-command = <0xce00000>;
  143. fixed-link = <0 0 10 0 0>;
  144. };
  145. i2c@11860 {
  146. compatible = "fsl,mpc8272-i2c",
  147. "fsl,cpm2-i2c";
  148. reg = <0x11860 0x20 0x8afc 0x2>;
  149. interrupts = <1 8>;
  150. interrupt-parent = <&PIC>;
  151. fsl,cpm-command = <0x29600000>;
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. };
  155. mdio@10d40 {
  156. compatible = "fsl,cpm2-mdio-bitbang";
  157. reg = <0x10d00 0x14>;
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. fsl,mdio-pin = <12>;
  161. fsl,mdc-pin = <13>;
  162. phy0: ethernet-phy@0 {
  163. reg = <0x0>;
  164. };
  165. phy1: ethernet-phy@1 {
  166. reg = <0x1>;
  167. };
  168. };
  169. /* FCC1 management to switch */
  170. ethernet@11300 {
  171. device_type = "network";
  172. compatible = "fsl,cpm2-fcc-enet";
  173. reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
  174. local-mac-address = [ 00 01 02 03 04 07 ];
  175. interrupts = <32 8>;
  176. interrupt-parent = <&PIC>;
  177. phy-handle = <&phy0>;
  178. linux,network-index = <1>;
  179. fsl,cpm-command = <0x12000300>;
  180. };
  181. /* FCC2 to redundant core unit over backplane */
  182. ethernet@11320 {
  183. device_type = "network";
  184. compatible = "fsl,cpm2-fcc-enet";
  185. reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
  186. local-mac-address = [ 00 01 02 03 04 08 ];
  187. interrupts = <33 8>;
  188. interrupt-parent = <&PIC>;
  189. phy-handle = <&phy1>;
  190. linux,network-index = <2>;
  191. fsl,cpm-command = <0x16200300>;
  192. };
  193. };
  194. cpm2_pio_c: gpio-controller@10d40 {
  195. #gpio-cells = <2>;
  196. compatible = "fsl,cpm2-pario-bank";
  197. reg = <0x10d40 0x14>;
  198. gpio-controller;
  199. };
  200. PIC: interrupt-controller@10c00 {
  201. #interrupt-cells = <2>;
  202. interrupt-controller;
  203. reg = <0x10c00 0x80>;
  204. compatible = "fsl,mpc8247-pic", "fsl,pq2-pic";
  205. };
  206. };
  207. };