irqflags.h 2.2 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
  7. * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
  8. */
  9. #ifndef _ASM_M32R_IRQFLAGS_H
  10. #define _ASM_M32R_IRQFLAGS_H
  11. #include <linux/types.h>
  12. static inline unsigned long arch_local_save_flags(void)
  13. {
  14. unsigned long flags;
  15. asm volatile("mvfc %0,psw" : "=r"(flags));
  16. return flags;
  17. }
  18. static inline void arch_local_irq_disable(void)
  19. {
  20. #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
  21. asm volatile (
  22. "clrpsw #0x40 -> nop"
  23. : : : "memory");
  24. #else
  25. unsigned long tmpreg0, tmpreg1;
  26. asm volatile (
  27. "ld24 %0, #0 ; Use 32-bit insn. \n\t"
  28. "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
  29. "mvtc %0, psw \n\t"
  30. "and3 %0, %1, #0xffbf \n\t"
  31. "mvtc %0, psw \n\t"
  32. : "=&r" (tmpreg0), "=&r" (tmpreg1)
  33. :
  34. : "cbit", "memory");
  35. #endif
  36. }
  37. static inline void arch_local_irq_enable(void)
  38. {
  39. #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
  40. asm volatile (
  41. "setpsw #0x40 -> nop"
  42. : : : "memory");
  43. #else
  44. unsigned long tmpreg;
  45. asm volatile (
  46. "mvfc %0, psw; \n\t"
  47. "or3 %0, %0, #0x0040; \n\t"
  48. "mvtc %0, psw; \n\t"
  49. : "=&r" (tmpreg)
  50. :
  51. : "cbit", "memory");
  52. #endif
  53. }
  54. static inline unsigned long arch_local_irq_save(void)
  55. {
  56. unsigned long flags;
  57. #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
  58. asm volatile (
  59. "mvfc %0, psw; \n\t"
  60. "clrpsw #0x40 -> nop; \n\t"
  61. : "=r" (flags)
  62. :
  63. : "memory");
  64. #else
  65. unsigned long tmpreg;
  66. asm volatile (
  67. "ld24 %1, #0 \n\t"
  68. "mvfc %0, psw \n\t"
  69. "mvtc %1, psw \n\t"
  70. "and3 %1, %0, #0xffbf \n\t"
  71. "mvtc %1, psw \n\t"
  72. : "=r" (flags), "=&r" (tmpreg)
  73. :
  74. : "cbit", "memory");
  75. #endif
  76. return flags;
  77. }
  78. static inline void arch_local_irq_restore(unsigned long flags)
  79. {
  80. asm volatile("mvtc %0,psw"
  81. :
  82. : "r" (flags)
  83. : "cbit", "memory");
  84. }
  85. static inline bool arch_irqs_disabled_flags(unsigned long flags)
  86. {
  87. return !(flags & 0x40);
  88. }
  89. static inline bool arch_irqs_disabled(void)
  90. {
  91. return arch_irqs_disabled_flags(arch_local_save_flags());
  92. }
  93. #endif /* _ASM_M32R_IRQFLAGS_H */