mpc5200_dma.c 15 KB

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  1. /*
  2. * Freescale MPC5200 PSC DMA
  3. * ALSA SoC Platform driver
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. * Copyright (C) 2009 Jon Smirl, Digispeaker
  7. */
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/of_platform.h>
  12. #include <sound/soc.h>
  13. #include <sysdev/bestcomm/bestcomm.h>
  14. #include <sysdev/bestcomm/gen_bd.h>
  15. #include <asm/mpc52xx_psc.h>
  16. #include "mpc5200_dma.h"
  17. /*
  18. * Interrupt handlers
  19. */
  20. static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
  21. {
  22. struct psc_dma *psc_dma = _psc_dma;
  23. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  24. u16 isr;
  25. isr = in_be16(&regs->mpc52xx_psc_isr);
  26. /* Playback underrun error */
  27. if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
  28. psc_dma->stats.underrun_count++;
  29. /* Capture overrun error */
  30. if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
  31. psc_dma->stats.overrun_count++;
  32. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  33. return IRQ_HANDLED;
  34. }
  35. /**
  36. * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
  37. * @s: pointer to stream private data structure
  38. *
  39. * Enqueues another audio period buffer into the bestcomm queue.
  40. *
  41. * Note: The routine must only be called when there is space available in
  42. * the queue. Otherwise the enqueue will fail and the audio ring buffer
  43. * will get out of sync
  44. */
  45. static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
  46. {
  47. struct bcom_bd *bd;
  48. /* Prepare and enqueue the next buffer descriptor */
  49. bd = bcom_prepare_next_buffer(s->bcom_task);
  50. bd->status = s->period_bytes;
  51. bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
  52. bcom_submit_next_buffer(s->bcom_task, NULL);
  53. /* Update for next period */
  54. s->period_next = (s->period_next + 1) % s->runtime->periods;
  55. }
  56. /* Bestcomm DMA irq handler */
  57. static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
  58. {
  59. struct psc_dma_stream *s = _psc_dma_stream;
  60. spin_lock(&s->psc_dma->lock);
  61. /* For each finished period, dequeue the completed period buffer
  62. * and enqueue a new one in it's place. */
  63. while (bcom_buffer_done(s->bcom_task)) {
  64. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  65. s->period_current = (s->period_current+1) % s->runtime->periods;
  66. s->period_count++;
  67. psc_dma_bcom_enqueue_next_buffer(s);
  68. }
  69. spin_unlock(&s->psc_dma->lock);
  70. /* If the stream is active, then also inform the PCM middle layer
  71. * of the period finished event. */
  72. if (s->active)
  73. snd_pcm_period_elapsed(s->stream);
  74. return IRQ_HANDLED;
  75. }
  76. static int psc_dma_hw_free(struct snd_pcm_substream *substream)
  77. {
  78. snd_pcm_set_runtime_buffer(substream, NULL);
  79. return 0;
  80. }
  81. /**
  82. * psc_dma_trigger: start and stop the DMA transfer.
  83. *
  84. * This function is called by ALSA to start, stop, pause, and resume the DMA
  85. * transfer of data.
  86. */
  87. static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
  88. {
  89. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  90. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  91. struct snd_pcm_runtime *runtime = substream->runtime;
  92. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  93. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  94. u16 imr;
  95. unsigned long flags;
  96. int i;
  97. switch (cmd) {
  98. case SNDRV_PCM_TRIGGER_START:
  99. dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
  100. substream->pstr->stream, runtime->frame_bits,
  101. (int)runtime->period_size, runtime->periods);
  102. s->period_bytes = frames_to_bytes(runtime,
  103. runtime->period_size);
  104. s->period_next = 0;
  105. s->period_current = 0;
  106. s->active = 1;
  107. s->period_count = 0;
  108. s->runtime = runtime;
  109. /* Fill up the bestcomm bd queue and enable DMA.
  110. * This will begin filling the PSC's fifo.
  111. */
  112. spin_lock_irqsave(&psc_dma->lock, flags);
  113. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  114. bcom_gen_bd_rx_reset(s->bcom_task);
  115. else
  116. bcom_gen_bd_tx_reset(s->bcom_task);
  117. for (i = 0; i < runtime->periods; i++)
  118. if (!bcom_queue_full(s->bcom_task))
  119. psc_dma_bcom_enqueue_next_buffer(s);
  120. bcom_enable(s->bcom_task);
  121. spin_unlock_irqrestore(&psc_dma->lock, flags);
  122. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  123. break;
  124. case SNDRV_PCM_TRIGGER_STOP:
  125. dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
  126. substream->pstr->stream, s->period_count);
  127. s->active = 0;
  128. spin_lock_irqsave(&psc_dma->lock, flags);
  129. bcom_disable(s->bcom_task);
  130. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  131. bcom_gen_bd_rx_reset(s->bcom_task);
  132. else
  133. bcom_gen_bd_tx_reset(s->bcom_task);
  134. spin_unlock_irqrestore(&psc_dma->lock, flags);
  135. break;
  136. default:
  137. dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
  138. substream->pstr->stream, cmd);
  139. return -EINVAL;
  140. }
  141. /* Update interrupt enable settings */
  142. imr = 0;
  143. if (psc_dma->playback.active)
  144. imr |= MPC52xx_PSC_IMR_TXEMP;
  145. if (psc_dma->capture.active)
  146. imr |= MPC52xx_PSC_IMR_ORERR;
  147. out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
  148. return 0;
  149. }
  150. /* ---------------------------------------------------------------------
  151. * The PSC DMA 'ASoC platform' driver
  152. *
  153. * Can be referenced by an 'ASoC machine' driver
  154. * This driver only deals with the audio bus; it doesn't have any
  155. * interaction with the attached codec
  156. */
  157. static const struct snd_pcm_hardware psc_dma_hardware = {
  158. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  159. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
  160. SNDRV_PCM_INFO_BATCH,
  161. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
  162. SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
  163. .rate_min = 8000,
  164. .rate_max = 48000,
  165. .channels_min = 1,
  166. .channels_max = 2,
  167. .period_bytes_max = 1024 * 1024,
  168. .period_bytes_min = 32,
  169. .periods_min = 2,
  170. .periods_max = 256,
  171. .buffer_bytes_max = 2 * 1024 * 1024,
  172. .fifo_size = 512,
  173. };
  174. static int psc_dma_open(struct snd_pcm_substream *substream)
  175. {
  176. struct snd_pcm_runtime *runtime = substream->runtime;
  177. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  178. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  179. struct psc_dma_stream *s;
  180. int rc;
  181. dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
  182. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  183. s = &psc_dma->capture;
  184. else
  185. s = &psc_dma->playback;
  186. snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
  187. rc = snd_pcm_hw_constraint_integer(runtime,
  188. SNDRV_PCM_HW_PARAM_PERIODS);
  189. if (rc < 0) {
  190. dev_err(substream->pcm->card->dev, "invalid buffer size\n");
  191. return rc;
  192. }
  193. s->stream = substream;
  194. return 0;
  195. }
  196. static int psc_dma_close(struct snd_pcm_substream *substream)
  197. {
  198. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  199. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  200. struct psc_dma_stream *s;
  201. dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
  202. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  203. s = &psc_dma->capture;
  204. else
  205. s = &psc_dma->playback;
  206. if (!psc_dma->playback.active &&
  207. !psc_dma->capture.active) {
  208. /* Disable all interrupts and reset the PSC */
  209. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  210. out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
  211. }
  212. s->stream = NULL;
  213. return 0;
  214. }
  215. static snd_pcm_uframes_t
  216. psc_dma_pointer(struct snd_pcm_substream *substream)
  217. {
  218. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  219. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  220. struct psc_dma_stream *s;
  221. dma_addr_t count;
  222. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  223. s = &psc_dma->capture;
  224. else
  225. s = &psc_dma->playback;
  226. count = s->period_current * s->period_bytes;
  227. return bytes_to_frames(substream->runtime, count);
  228. }
  229. static int
  230. psc_dma_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *params)
  232. {
  233. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  234. return 0;
  235. }
  236. static struct snd_pcm_ops psc_dma_ops = {
  237. .open = psc_dma_open,
  238. .close = psc_dma_close,
  239. .hw_free = psc_dma_hw_free,
  240. .ioctl = snd_pcm_lib_ioctl,
  241. .pointer = psc_dma_pointer,
  242. .trigger = psc_dma_trigger,
  243. .hw_params = psc_dma_hw_params,
  244. };
  245. static u64 psc_dma_dmamask = 0xffffffff;
  246. static int psc_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
  247. struct snd_pcm *pcm)
  248. {
  249. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  250. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  251. size_t size = psc_dma_hardware.buffer_bytes_max;
  252. int rc = 0;
  253. dev_dbg(rtd->platform->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
  254. card, dai, pcm);
  255. if (!card->dev->dma_mask)
  256. card->dev->dma_mask = &psc_dma_dmamask;
  257. if (!card->dev->coherent_dma_mask)
  258. card->dev->coherent_dma_mask = 0xffffffff;
  259. if (pcm->streams[0].substream) {
  260. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  261. size, &pcm->streams[0].substream->dma_buffer);
  262. if (rc)
  263. goto playback_alloc_err;
  264. }
  265. if (pcm->streams[1].substream) {
  266. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  267. size, &pcm->streams[1].substream->dma_buffer);
  268. if (rc)
  269. goto capture_alloc_err;
  270. }
  271. if (rtd->codec->ac97)
  272. rtd->codec->ac97->private_data = psc_dma;
  273. return 0;
  274. capture_alloc_err:
  275. if (pcm->streams[0].substream)
  276. snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
  277. playback_alloc_err:
  278. dev_err(card->dev, "Cannot allocate buffer(s)\n");
  279. return -ENOMEM;
  280. }
  281. static void psc_dma_free(struct snd_pcm *pcm)
  282. {
  283. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  284. struct snd_pcm_substream *substream;
  285. int stream;
  286. dev_dbg(rtd->platform->dev, "psc_dma_free(pcm=%p)\n", pcm);
  287. for (stream = 0; stream < 2; stream++) {
  288. substream = pcm->streams[stream].substream;
  289. if (substream) {
  290. snd_dma_free_pages(&substream->dma_buffer);
  291. substream->dma_buffer.area = NULL;
  292. substream->dma_buffer.addr = 0;
  293. }
  294. }
  295. }
  296. static struct snd_soc_platform_driver mpc5200_audio_dma_platform = {
  297. .ops = &psc_dma_ops,
  298. .pcm_new = &psc_dma_new,
  299. .pcm_free = &psc_dma_free,
  300. };
  301. static int mpc5200_hpcd_probe(struct platform_device *op)
  302. {
  303. phys_addr_t fifo;
  304. struct psc_dma *psc_dma;
  305. struct resource res;
  306. int size, irq, rc;
  307. const __be32 *prop;
  308. void __iomem *regs;
  309. int ret;
  310. /* Fetch the registers and IRQ of the PSC */
  311. irq = irq_of_parse_and_map(op->dev.of_node, 0);
  312. if (of_address_to_resource(op->dev.of_node, 0, &res)) {
  313. dev_err(&op->dev, "Missing reg property\n");
  314. return -ENODEV;
  315. }
  316. regs = ioremap(res.start, 1 + res.end - res.start);
  317. if (!regs) {
  318. dev_err(&op->dev, "Could not map registers\n");
  319. return -ENODEV;
  320. }
  321. /* Allocate and initialize the driver private data */
  322. psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
  323. if (!psc_dma) {
  324. ret = -ENOMEM;
  325. goto out_unmap;
  326. }
  327. /* Get the PSC ID */
  328. prop = of_get_property(op->dev.of_node, "cell-index", &size);
  329. if (!prop || size < sizeof *prop) {
  330. ret = -ENODEV;
  331. goto out_free;
  332. }
  333. spin_lock_init(&psc_dma->lock);
  334. mutex_init(&psc_dma->mutex);
  335. psc_dma->id = be32_to_cpu(*prop);
  336. psc_dma->irq = irq;
  337. psc_dma->psc_regs = regs;
  338. psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
  339. psc_dma->dev = &op->dev;
  340. psc_dma->playback.psc_dma = psc_dma;
  341. psc_dma->capture.psc_dma = psc_dma;
  342. snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
  343. /* Find the address of the fifo data registers and setup the
  344. * DMA tasks */
  345. fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
  346. psc_dma->capture.bcom_task =
  347. bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
  348. psc_dma->playback.bcom_task =
  349. bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
  350. if (!psc_dma->capture.bcom_task ||
  351. !psc_dma->playback.bcom_task) {
  352. dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
  353. ret = -ENODEV;
  354. goto out_free;
  355. }
  356. /* Disable all interrupts and reset the PSC */
  357. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  358. /* reset receiver */
  359. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
  360. /* reset transmitter */
  361. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
  362. /* reset error */
  363. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
  364. /* reset mode */
  365. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
  366. /* Set up mode register;
  367. * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
  368. * Second write: register Normal mode for non loopback
  369. */
  370. out_8(&psc_dma->psc_regs->mode, 0);
  371. out_8(&psc_dma->psc_regs->mode, 0);
  372. /* Set the TX and RX fifo alarm thresholds */
  373. out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
  374. out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
  375. out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
  376. out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
  377. /* Lookup the IRQ numbers */
  378. psc_dma->playback.irq =
  379. bcom_get_task_irq(psc_dma->playback.bcom_task);
  380. psc_dma->capture.irq =
  381. bcom_get_task_irq(psc_dma->capture.bcom_task);
  382. rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
  383. "psc-dma-status", psc_dma);
  384. rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  385. "psc-dma-capture", &psc_dma->capture);
  386. rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  387. "psc-dma-playback", &psc_dma->playback);
  388. if (rc) {
  389. ret = -ENODEV;
  390. goto out_irq;
  391. }
  392. /* Save what we've done so it can be found again later */
  393. dev_set_drvdata(&op->dev, psc_dma);
  394. /* Tell the ASoC OF helpers about it */
  395. return snd_soc_register_platform(&op->dev, &mpc5200_audio_dma_platform);
  396. out_irq:
  397. free_irq(psc_dma->irq, psc_dma);
  398. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  399. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  400. out_free:
  401. kfree(psc_dma);
  402. out_unmap:
  403. iounmap(regs);
  404. return ret;
  405. }
  406. static int mpc5200_hpcd_remove(struct platform_device *op)
  407. {
  408. struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
  409. dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
  410. snd_soc_unregister_platform(&op->dev);
  411. bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
  412. bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
  413. /* Release irqs */
  414. free_irq(psc_dma->irq, psc_dma);
  415. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  416. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  417. iounmap(psc_dma->psc_regs);
  418. kfree(psc_dma);
  419. dev_set_drvdata(&op->dev, NULL);
  420. return 0;
  421. }
  422. static struct of_device_id mpc5200_hpcd_match[] = {
  423. { .compatible = "fsl,mpc5200-pcm", },
  424. {}
  425. };
  426. MODULE_DEVICE_TABLE(of, mpc5200_hpcd_match);
  427. static struct platform_driver mpc5200_hpcd_of_driver = {
  428. .probe = mpc5200_hpcd_probe,
  429. .remove = mpc5200_hpcd_remove,
  430. .driver = {
  431. .owner = THIS_MODULE,
  432. .name = "mpc5200-pcm-audio",
  433. .of_match_table = mpc5200_hpcd_match,
  434. }
  435. };
  436. static int __init mpc5200_hpcd_init(void)
  437. {
  438. return platform_driver_register(&mpc5200_hpcd_of_driver);
  439. }
  440. module_init(mpc5200_hpcd_init);
  441. static void __exit mpc5200_hpcd_exit(void)
  442. {
  443. platform_driver_unregister(&mpc5200_hpcd_of_driver);
  444. }
  445. module_exit(mpc5200_hpcd_exit);
  446. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  447. MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
  448. MODULE_LICENSE("GPL");