ak4642.c 12 KB

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  1. /*
  2. * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on wm8731.c by Richard Purdie
  8. * Based on ak4535.c by Richard Purdie
  9. * Based on wm8753.c by Liam Girdwood
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. /* ** CAUTION **
  16. *
  17. * This is very simple driver.
  18. * It can use headphone output / stereo input only
  19. *
  20. * AK4642 is not tested.
  21. * AK4643 is tested.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/i2c.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include <sound/soc.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #define AK4642_VERSION "0.0.1"
  31. #define PW_MGMT1 0x00
  32. #define PW_MGMT2 0x01
  33. #define SG_SL1 0x02
  34. #define SG_SL2 0x03
  35. #define MD_CTL1 0x04
  36. #define MD_CTL2 0x05
  37. #define TIMER 0x06
  38. #define ALC_CTL1 0x07
  39. #define ALC_CTL2 0x08
  40. #define L_IVC 0x09
  41. #define L_DVC 0x0a
  42. #define ALC_CTL3 0x0b
  43. #define R_IVC 0x0c
  44. #define R_DVC 0x0d
  45. #define MD_CTL3 0x0e
  46. #define MD_CTL4 0x0f
  47. #define PW_MGMT3 0x10
  48. #define DF_S 0x11
  49. #define FIL3_0 0x12
  50. #define FIL3_1 0x13
  51. #define FIL3_2 0x14
  52. #define FIL3_3 0x15
  53. #define EQ_0 0x16
  54. #define EQ_1 0x17
  55. #define EQ_2 0x18
  56. #define EQ_3 0x19
  57. #define EQ_4 0x1a
  58. #define EQ_5 0x1b
  59. #define FIL1_0 0x1c
  60. #define FIL1_1 0x1d
  61. #define FIL1_2 0x1e
  62. #define FIL1_3 0x1f
  63. #define PW_MGMT4 0x20
  64. #define MD_CTL5 0x21
  65. #define LO_MS 0x22
  66. #define HP_MS 0x23
  67. #define SPK_MS 0x24
  68. #define AK4642_CACHEREGNUM 0x25
  69. /* PW_MGMT1*/
  70. #define PMVCM (1 << 6) /* VCOM Power Management */
  71. #define PMMIN (1 << 5) /* MIN Input Power Management */
  72. #define PMDAC (1 << 2) /* DAC Power Management */
  73. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  74. /* PW_MGMT2 */
  75. #define HPMTN (1 << 6)
  76. #define PMHPL (1 << 5)
  77. #define PMHPR (1 << 4)
  78. #define MS (1 << 3) /* master/slave select */
  79. #define MCKO (1 << 1)
  80. #define PMPLL (1 << 0)
  81. #define PMHP_MASK (PMHPL | PMHPR)
  82. #define PMHP PMHP_MASK
  83. /* PW_MGMT3 */
  84. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  85. /* SG_SL1 */
  86. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  87. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  88. #define PMMP (1 << 2) /* MPWR pin Power Management */
  89. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  90. /* TIMER */
  91. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
  92. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  93. /* ALC_CTL1 */
  94. #define ALC (1 << 5) /* ALC Enable */
  95. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  96. /* MD_CTL1 */
  97. #define PLL3 (1 << 7)
  98. #define PLL2 (1 << 6)
  99. #define PLL1 (1 << 5)
  100. #define PLL0 (1 << 4)
  101. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  102. #define BCKO_MASK (1 << 3)
  103. #define BCKO_64 BCKO_MASK
  104. #define DIF_MASK (3 << 0)
  105. #define DSP (0 << 0)
  106. #define RIGHT_J (1 << 0)
  107. #define LEFT_J (2 << 0)
  108. #define I2S (3 << 0)
  109. /* MD_CTL2 */
  110. #define FS0 (1 << 0)
  111. #define FS1 (1 << 1)
  112. #define FS2 (1 << 2)
  113. #define FS3 (1 << 5)
  114. #define FS_MASK (FS0 | FS1 | FS2 | FS3)
  115. /* MD_CTL3 */
  116. #define BST1 (1 << 3)
  117. /* MD_CTL4 */
  118. #define DACH (1 << 0)
  119. /*
  120. * Playback Volume (table 39)
  121. *
  122. * max : 0x00 : +12.0 dB
  123. * ( 0.5 dB step )
  124. * min : 0xFE : -115.0 dB
  125. * mute: 0xFF
  126. */
  127. static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
  128. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  129. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  130. 0, 0xFF, 1, out_tlv),
  131. };
  132. /* codec private data */
  133. struct ak4642_priv {
  134. unsigned int sysclk;
  135. enum snd_soc_control_type control_type;
  136. void *control_data;
  137. };
  138. /*
  139. * ak4642 register cache
  140. */
  141. static const u8 ak4642_reg[AK4642_CACHEREGNUM] = {
  142. 0x00, 0x00, 0x01, 0x00,
  143. 0x02, 0x00, 0x00, 0x00,
  144. 0xe1, 0xe1, 0x18, 0x00,
  145. 0xe1, 0x18, 0x11, 0x08,
  146. 0x00, 0x00, 0x00, 0x00,
  147. 0x00, 0x00, 0x00, 0x00,
  148. 0x00, 0x00, 0x00, 0x00,
  149. 0x00, 0x00, 0x00, 0x00,
  150. 0x00, 0x00, 0x00, 0x00,
  151. 0x00,
  152. };
  153. /*
  154. * read ak4642 register cache
  155. */
  156. static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
  157. unsigned int reg)
  158. {
  159. u16 *cache = codec->reg_cache;
  160. if (reg >= AK4642_CACHEREGNUM)
  161. return -1;
  162. return cache[reg];
  163. }
  164. /*
  165. * write ak4642 register cache
  166. */
  167. static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
  168. u16 reg, unsigned int value)
  169. {
  170. u16 *cache = codec->reg_cache;
  171. if (reg >= AK4642_CACHEREGNUM)
  172. return;
  173. cache[reg] = value;
  174. }
  175. /*
  176. * write to the AK4642 register space
  177. */
  178. static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
  179. unsigned int value)
  180. {
  181. u8 data[2];
  182. /* data is
  183. * D15..D8 AK4642 register offset
  184. * D7...D0 register data
  185. */
  186. data[0] = reg & 0xff;
  187. data[1] = value & 0xff;
  188. if (codec->hw_write(codec->control_data, data, 2) == 2) {
  189. ak4642_write_reg_cache(codec, reg, value);
  190. return 0;
  191. } else
  192. return -EIO;
  193. }
  194. static int ak4642_sync(struct snd_soc_codec *codec)
  195. {
  196. u16 *cache = codec->reg_cache;
  197. int i, r = 0;
  198. for (i = 0; i < AK4642_CACHEREGNUM; i++)
  199. r |= ak4642_write(codec, i, cache[i]);
  200. return r;
  201. };
  202. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  203. struct snd_soc_dai *dai)
  204. {
  205. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  206. struct snd_soc_codec *codec = dai->codec;
  207. if (is_play) {
  208. /*
  209. * start headphone output
  210. *
  211. * PLL, Master Mode
  212. * Audio I/F Format :MSB justified (ADC & DAC)
  213. * Bass Boost Level : Middle
  214. *
  215. * This operation came from example code of
  216. * "ASAHI KASEI AK4642" (japanese) manual p97.
  217. */
  218. snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
  219. snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
  220. ak4642_write(codec, L_IVC, 0x91); /* volume */
  221. ak4642_write(codec, R_IVC, 0x91); /* volume */
  222. snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC,
  223. PMVCM | PMMIN | PMDAC);
  224. snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP);
  225. snd_soc_update_bits(codec, PW_MGMT2, HPMTN, HPMTN);
  226. } else {
  227. /*
  228. * start stereo input
  229. *
  230. * PLL Master Mode
  231. * Audio I/F Format:MSB justified (ADC & DAC)
  232. * Pre MIC AMP:+20dB
  233. * MIC Power On
  234. * ALC setting:Refer to Table 35
  235. * ALC bit=“1”
  236. *
  237. * This operation came from example code of
  238. * "ASAHI KASEI AK4642" (japanese) manual p94.
  239. */
  240. ak4642_write(codec, SG_SL1, PMMP | MGAIN0);
  241. ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
  242. ak4642_write(codec, ALC_CTL1, ALC | LMTH0);
  243. snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL,
  244. PMVCM | PMADL);
  245. snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
  246. }
  247. return 0;
  248. }
  249. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  250. struct snd_soc_dai *dai)
  251. {
  252. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  253. struct snd_soc_codec *codec = dai->codec;
  254. if (is_play) {
  255. /* stop headphone output */
  256. snd_soc_update_bits(codec, PW_MGMT2, HPMTN, 0);
  257. snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0);
  258. snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0);
  259. snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
  260. snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
  261. } else {
  262. /* stop stereo input */
  263. snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
  264. snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
  265. snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
  266. }
  267. }
  268. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  269. int clk_id, unsigned int freq, int dir)
  270. {
  271. struct snd_soc_codec *codec = codec_dai->codec;
  272. u8 pll;
  273. switch (freq) {
  274. case 11289600:
  275. pll = PLL2;
  276. break;
  277. case 12288000:
  278. pll = PLL2 | PLL0;
  279. break;
  280. case 12000000:
  281. pll = PLL2 | PLL1;
  282. break;
  283. case 24000000:
  284. pll = PLL2 | PLL1 | PLL0;
  285. break;
  286. case 13500000:
  287. pll = PLL3 | PLL2;
  288. break;
  289. case 27000000:
  290. pll = PLL3 | PLL2 | PLL0;
  291. break;
  292. default:
  293. return -EINVAL;
  294. }
  295. snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
  296. return 0;
  297. }
  298. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  299. {
  300. struct snd_soc_codec *codec = dai->codec;
  301. u8 data;
  302. u8 bcko;
  303. data = MCKO | PMPLL; /* use MCKO */
  304. bcko = 0;
  305. /* set master/slave audio interface */
  306. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  307. case SND_SOC_DAIFMT_CBM_CFM:
  308. data |= MS;
  309. bcko = BCKO_64;
  310. break;
  311. case SND_SOC_DAIFMT_CBS_CFS:
  312. break;
  313. default:
  314. return -EINVAL;
  315. }
  316. snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
  317. snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
  318. /* format type */
  319. data = 0;
  320. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  321. case SND_SOC_DAIFMT_LEFT_J:
  322. data = LEFT_J;
  323. break;
  324. case SND_SOC_DAIFMT_I2S:
  325. data = I2S;
  326. break;
  327. /* FIXME
  328. * Please add RIGHT_J / DSP support here
  329. */
  330. default:
  331. return -EINVAL;
  332. break;
  333. }
  334. snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
  335. return 0;
  336. }
  337. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  338. struct snd_pcm_hw_params *params,
  339. struct snd_soc_dai *dai)
  340. {
  341. struct snd_soc_codec *codec = dai->codec;
  342. u8 rate;
  343. switch (params_rate(params)) {
  344. case 7350:
  345. rate = FS2;
  346. break;
  347. case 8000:
  348. rate = 0;
  349. break;
  350. case 11025:
  351. rate = FS2 | FS0;
  352. break;
  353. case 12000:
  354. rate = FS0;
  355. break;
  356. case 14700:
  357. rate = FS2 | FS1;
  358. break;
  359. case 16000:
  360. rate = FS1;
  361. break;
  362. case 22050:
  363. rate = FS2 | FS1 | FS0;
  364. break;
  365. case 24000:
  366. rate = FS1 | FS0;
  367. break;
  368. case 29400:
  369. rate = FS3 | FS2 | FS1;
  370. break;
  371. case 32000:
  372. rate = FS3 | FS1;
  373. break;
  374. case 44100:
  375. rate = FS3 | FS2 | FS1 | FS0;
  376. break;
  377. case 48000:
  378. rate = FS3 | FS1 | FS0;
  379. break;
  380. default:
  381. return -EINVAL;
  382. break;
  383. }
  384. snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
  385. return 0;
  386. }
  387. static struct snd_soc_dai_ops ak4642_dai_ops = {
  388. .startup = ak4642_dai_startup,
  389. .shutdown = ak4642_dai_shutdown,
  390. .set_sysclk = ak4642_dai_set_sysclk,
  391. .set_fmt = ak4642_dai_set_fmt,
  392. .hw_params = ak4642_dai_hw_params,
  393. };
  394. static struct snd_soc_dai_driver ak4642_dai = {
  395. .name = "ak4642-hifi",
  396. .playback = {
  397. .stream_name = "Playback",
  398. .channels_min = 1,
  399. .channels_max = 2,
  400. .rates = SNDRV_PCM_RATE_8000_48000,
  401. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  402. .capture = {
  403. .stream_name = "Capture",
  404. .channels_min = 1,
  405. .channels_max = 2,
  406. .rates = SNDRV_PCM_RATE_8000_48000,
  407. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  408. .ops = &ak4642_dai_ops,
  409. .symmetric_rates = 1,
  410. };
  411. static int ak4642_resume(struct snd_soc_codec *codec)
  412. {
  413. ak4642_sync(codec);
  414. return 0;
  415. }
  416. static int ak4642_probe(struct snd_soc_codec *codec)
  417. {
  418. struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
  419. dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
  420. codec->hw_write = (hw_write_t)i2c_master_send;
  421. codec->control_data = ak4642->control_data;
  422. snd_soc_add_controls(codec, ak4642_snd_controls,
  423. ARRAY_SIZE(ak4642_snd_controls));
  424. return 0;
  425. }
  426. static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
  427. .probe = ak4642_probe,
  428. .resume = ak4642_resume,
  429. .read = ak4642_read_reg_cache,
  430. .write = ak4642_write,
  431. .reg_cache_size = ARRAY_SIZE(ak4642_reg),
  432. .reg_word_size = sizeof(u8),
  433. .reg_cache_default = ak4642_reg,
  434. };
  435. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  436. static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
  437. const struct i2c_device_id *id)
  438. {
  439. struct ak4642_priv *ak4642;
  440. int ret;
  441. ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
  442. if (!ak4642)
  443. return -ENOMEM;
  444. i2c_set_clientdata(i2c, ak4642);
  445. ak4642->control_data = i2c;
  446. ak4642->control_type = SND_SOC_I2C;
  447. ret = snd_soc_register_codec(&i2c->dev,
  448. &soc_codec_dev_ak4642, &ak4642_dai, 1);
  449. if (ret < 0)
  450. kfree(ak4642);
  451. return ret;
  452. }
  453. static __devexit int ak4642_i2c_remove(struct i2c_client *client)
  454. {
  455. snd_soc_unregister_codec(&client->dev);
  456. kfree(i2c_get_clientdata(client));
  457. return 0;
  458. }
  459. static const struct i2c_device_id ak4642_i2c_id[] = {
  460. { "ak4642", 0 },
  461. { "ak4643", 0 },
  462. { }
  463. };
  464. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  465. static struct i2c_driver ak4642_i2c_driver = {
  466. .driver = {
  467. .name = "ak4642-codec",
  468. .owner = THIS_MODULE,
  469. },
  470. .probe = ak4642_i2c_probe,
  471. .remove = __devexit_p(ak4642_i2c_remove),
  472. .id_table = ak4642_i2c_id,
  473. };
  474. #endif
  475. static int __init ak4642_modinit(void)
  476. {
  477. int ret = 0;
  478. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  479. ret = i2c_add_driver(&ak4642_i2c_driver);
  480. #endif
  481. return ret;
  482. }
  483. module_init(ak4642_modinit);
  484. static void __exit ak4642_exit(void)
  485. {
  486. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  487. i2c_del_driver(&ak4642_i2c_driver);
  488. #endif
  489. }
  490. module_exit(ak4642_exit);
  491. MODULE_DESCRIPTION("Soc AK4642 driver");
  492. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  493. MODULE_LICENSE("GPL");