sp805_wdt.c 8.5 KB

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  1. /*
  2. * drivers/char/watchdog/sp805-wdt.c
  3. *
  4. * Watchdog driver for ARM SP805 watchdog module
  5. *
  6. * Copyright (C) 2010 ST Microelectronics
  7. * Viresh Kumar<viresh.kumar@st.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2 or later. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/resource.h>
  15. #include <linux/amba/bus.h>
  16. #include <linux/bitops.h>
  17. #include <linux/clk.h>
  18. #include <linux/fs.h>
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/ioport.h>
  22. #include <linux/kernel.h>
  23. #include <linux/math64.h>
  24. #include <linux/miscdevice.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/slab.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. #include <linux/uaccess.h>
  31. #include <linux/watchdog.h>
  32. /* default timeout in seconds */
  33. #define DEFAULT_TIMEOUT 60
  34. #define MODULE_NAME "sp805-wdt"
  35. /* watchdog register offsets and masks */
  36. #define WDTLOAD 0x000
  37. #define LOAD_MIN 0x00000001
  38. #define LOAD_MAX 0xFFFFFFFF
  39. #define WDTVALUE 0x004
  40. #define WDTCONTROL 0x008
  41. /* control register masks */
  42. #define INT_ENABLE (1 << 0)
  43. #define RESET_ENABLE (1 << 1)
  44. #define WDTINTCLR 0x00C
  45. #define WDTRIS 0x010
  46. #define WDTMIS 0x014
  47. #define INT_MASK (1 << 0)
  48. #define WDTLOCK 0xC00
  49. #define UNLOCK 0x1ACCE551
  50. #define LOCK 0x00000001
  51. /**
  52. * struct sp805_wdt: sp805 wdt device structure
  53. *
  54. * lock: spin lock protecting dev structure and io access
  55. * base: base address of wdt
  56. * clk: clock structure of wdt
  57. * dev: amba device structure of wdt
  58. * status: current status of wdt
  59. * load_val: load value to be set for current timeout
  60. * timeout: current programmed timeout
  61. */
  62. struct sp805_wdt {
  63. spinlock_t lock;
  64. void __iomem *base;
  65. struct clk *clk;
  66. struct amba_device *adev;
  67. unsigned long status;
  68. #define WDT_BUSY 0
  69. #define WDT_CAN_BE_CLOSED 1
  70. unsigned int load_val;
  71. unsigned int timeout;
  72. };
  73. /* local variables */
  74. static struct sp805_wdt *wdt;
  75. static int nowayout = WATCHDOG_NOWAYOUT;
  76. /* This routine finds load value that will reset system in required timout */
  77. static void wdt_setload(unsigned int timeout)
  78. {
  79. u64 load, rate;
  80. rate = clk_get_rate(wdt->clk);
  81. /*
  82. * sp805 runs counter with given value twice, after the end of first
  83. * counter it gives an interrupt and then starts counter again. If
  84. * interrupt already occurred then it resets the system. This is why
  85. * load is half of what should be required.
  86. */
  87. load = div_u64(rate, 2) * timeout - 1;
  88. load = (load > LOAD_MAX) ? LOAD_MAX : load;
  89. load = (load < LOAD_MIN) ? LOAD_MIN : load;
  90. spin_lock(&wdt->lock);
  91. wdt->load_val = load;
  92. /* roundup timeout to closest positive integer value */
  93. wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
  94. spin_unlock(&wdt->lock);
  95. }
  96. /* returns number of seconds left for reset to occur */
  97. static u32 wdt_timeleft(void)
  98. {
  99. u64 load, rate;
  100. rate = clk_get_rate(wdt->clk);
  101. spin_lock(&wdt->lock);
  102. load = readl(wdt->base + WDTVALUE);
  103. /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
  104. if (!(readl(wdt->base + WDTRIS) & INT_MASK))
  105. load += wdt->load_val + 1;
  106. spin_unlock(&wdt->lock);
  107. return div_u64(load, rate);
  108. }
  109. /* enables watchdog timers reset */
  110. static void wdt_enable(void)
  111. {
  112. spin_lock(&wdt->lock);
  113. writel(UNLOCK, wdt->base + WDTLOCK);
  114. writel(wdt->load_val, wdt->base + WDTLOAD);
  115. writel(INT_MASK, wdt->base + WDTINTCLR);
  116. writel(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
  117. writel(LOCK, wdt->base + WDTLOCK);
  118. spin_unlock(&wdt->lock);
  119. }
  120. /* disables watchdog timers reset */
  121. static void wdt_disable(void)
  122. {
  123. spin_lock(&wdt->lock);
  124. writel(UNLOCK, wdt->base + WDTLOCK);
  125. writel(0, wdt->base + WDTCONTROL);
  126. writel(0, wdt->base + WDTLOAD);
  127. writel(LOCK, wdt->base + WDTLOCK);
  128. spin_unlock(&wdt->lock);
  129. }
  130. static ssize_t sp805_wdt_write(struct file *file, const char *data,
  131. size_t len, loff_t *ppos)
  132. {
  133. if (len) {
  134. if (!nowayout) {
  135. size_t i;
  136. clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
  137. for (i = 0; i != len; i++) {
  138. char c;
  139. if (get_user(c, data + i))
  140. return -EFAULT;
  141. /* Check for Magic Close character */
  142. if (c == 'V') {
  143. set_bit(WDT_CAN_BE_CLOSED,
  144. &wdt->status);
  145. break;
  146. }
  147. }
  148. }
  149. wdt_enable();
  150. }
  151. return len;
  152. }
  153. static const struct watchdog_info ident = {
  154. .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  155. .identity = MODULE_NAME,
  156. };
  157. static long sp805_wdt_ioctl(struct file *file, unsigned int cmd,
  158. unsigned long arg)
  159. {
  160. int ret = -ENOTTY;
  161. unsigned int timeout;
  162. switch (cmd) {
  163. case WDIOC_GETSUPPORT:
  164. ret = copy_to_user((struct watchdog_info *)arg, &ident,
  165. sizeof(ident)) ? -EFAULT : 0;
  166. break;
  167. case WDIOC_GETSTATUS:
  168. ret = put_user(0, (int *)arg);
  169. break;
  170. case WDIOC_KEEPALIVE:
  171. wdt_enable();
  172. ret = 0;
  173. break;
  174. case WDIOC_SETTIMEOUT:
  175. ret = get_user(timeout, (unsigned int *)arg);
  176. if (ret)
  177. break;
  178. wdt_setload(timeout);
  179. wdt_enable();
  180. /* Fall through */
  181. case WDIOC_GETTIMEOUT:
  182. ret = put_user(wdt->timeout, (unsigned int *)arg);
  183. break;
  184. case WDIOC_GETTIMELEFT:
  185. ret = put_user(wdt_timeleft(), (unsigned int *)arg);
  186. break;
  187. }
  188. return ret;
  189. }
  190. static int sp805_wdt_open(struct inode *inode, struct file *file)
  191. {
  192. int ret = 0;
  193. if (test_and_set_bit(WDT_BUSY, &wdt->status))
  194. return -EBUSY;
  195. ret = clk_enable(wdt->clk);
  196. if (ret) {
  197. dev_err(&wdt->adev->dev, "clock enable fail");
  198. goto err;
  199. }
  200. wdt_enable();
  201. /* can not be closed, once enabled */
  202. clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
  203. return nonseekable_open(inode, file);
  204. err:
  205. clear_bit(WDT_BUSY, &wdt->status);
  206. return ret;
  207. }
  208. static int sp805_wdt_release(struct inode *inode, struct file *file)
  209. {
  210. if (!test_bit(WDT_CAN_BE_CLOSED, &wdt->status)) {
  211. clear_bit(WDT_BUSY, &wdt->status);
  212. dev_warn(&wdt->adev->dev, "Device closed unexpectedly\n");
  213. return 0;
  214. }
  215. wdt_disable();
  216. clk_disable(wdt->clk);
  217. clear_bit(WDT_BUSY, &wdt->status);
  218. return 0;
  219. }
  220. static const struct file_operations sp805_wdt_fops = {
  221. .owner = THIS_MODULE,
  222. .llseek = no_llseek,
  223. .write = sp805_wdt_write,
  224. .unlocked_ioctl = sp805_wdt_ioctl,
  225. .open = sp805_wdt_open,
  226. .release = sp805_wdt_release,
  227. };
  228. static struct miscdevice sp805_wdt_miscdev = {
  229. .minor = WATCHDOG_MINOR,
  230. .name = "watchdog",
  231. .fops = &sp805_wdt_fops,
  232. };
  233. static int __devinit
  234. sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
  235. {
  236. int ret = 0;
  237. if (!request_mem_region(adev->res.start, resource_size(&adev->res),
  238. "sp805_wdt")) {
  239. dev_warn(&adev->dev, "Failed to get memory region resource\n");
  240. ret = -ENOENT;
  241. goto err;
  242. }
  243. wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
  244. if (!wdt) {
  245. dev_warn(&adev->dev, "Kzalloc failed\n");
  246. ret = -ENOMEM;
  247. goto err_kzalloc;
  248. }
  249. wdt->clk = clk_get(&adev->dev, NULL);
  250. if (IS_ERR(wdt->clk)) {
  251. dev_warn(&adev->dev, "Clock not found\n");
  252. ret = PTR_ERR(wdt->clk);
  253. goto err_clk_get;
  254. }
  255. wdt->base = ioremap(adev->res.start, resource_size(&adev->res));
  256. if (!wdt->base) {
  257. ret = -ENOMEM;
  258. dev_warn(&adev->dev, "ioremap fail\n");
  259. goto err_ioremap;
  260. }
  261. wdt->adev = adev;
  262. spin_lock_init(&wdt->lock);
  263. wdt_setload(DEFAULT_TIMEOUT);
  264. ret = misc_register(&sp805_wdt_miscdev);
  265. if (ret < 0) {
  266. dev_warn(&adev->dev, "cannot register misc device\n");
  267. goto err_misc_register;
  268. }
  269. dev_info(&adev->dev, "registration successful\n");
  270. return 0;
  271. err_misc_register:
  272. iounmap(wdt->base);
  273. err_ioremap:
  274. clk_put(wdt->clk);
  275. err_clk_get:
  276. kfree(wdt);
  277. wdt = NULL;
  278. err_kzalloc:
  279. release_mem_region(adev->res.start, resource_size(&adev->res));
  280. err:
  281. dev_err(&adev->dev, "Probe Failed!!!\n");
  282. return ret;
  283. }
  284. static int __devexit sp805_wdt_remove(struct amba_device *adev)
  285. {
  286. misc_deregister(&sp805_wdt_miscdev);
  287. iounmap(wdt->base);
  288. clk_put(wdt->clk);
  289. kfree(wdt);
  290. release_mem_region(adev->res.start, resource_size(&adev->res));
  291. return 0;
  292. }
  293. static struct amba_id sp805_wdt_ids[] __initdata = {
  294. {
  295. .id = 0x00141805,
  296. .mask = 0x00ffffff,
  297. },
  298. { 0, 0 },
  299. };
  300. static struct amba_driver sp805_wdt_driver = {
  301. .drv = {
  302. .name = MODULE_NAME,
  303. },
  304. .id_table = sp805_wdt_ids,
  305. .probe = sp805_wdt_probe,
  306. .remove = __devexit_p(sp805_wdt_remove),
  307. };
  308. static int __init sp805_wdt_init(void)
  309. {
  310. return amba_driver_register(&sp805_wdt_driver);
  311. }
  312. module_init(sp805_wdt_init);
  313. static void __exit sp805_wdt_exit(void)
  314. {
  315. amba_driver_unregister(&sp805_wdt_driver);
  316. }
  317. module_exit(sp805_wdt_exit);
  318. module_param(nowayout, int, 0);
  319. MODULE_PARM_DESC(nowayout,
  320. "Set to 1 to keep watchdog running after device release");
  321. MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
  322. MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
  323. MODULE_LICENSE("GPL");
  324. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);