omap_wdt.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458
  1. /*
  2. * omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/init.h>
  37. #include <linux/err.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/bitops.h>
  41. #include <linux/io.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/slab.h>
  44. #include <linux/pm_runtime.h>
  45. #include <mach/hardware.h>
  46. #include <plat/prcm.h>
  47. #include "omap_wdt.h"
  48. static struct platform_device *omap_wdt_dev;
  49. static unsigned timer_margin;
  50. module_param(timer_margin, uint, 0);
  51. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  52. static unsigned int wdt_trgr_pattern = 0x1234;
  53. static spinlock_t wdt_lock;
  54. struct omap_wdt_dev {
  55. void __iomem *base; /* physical */
  56. struct device *dev;
  57. int omap_wdt_users;
  58. struct resource *mem;
  59. struct miscdevice omap_wdt_miscdev;
  60. };
  61. static void omap_wdt_ping(struct omap_wdt_dev *wdev)
  62. {
  63. void __iomem *base = wdev->base;
  64. /* wait for posted write to complete */
  65. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  66. cpu_relax();
  67. wdt_trgr_pattern = ~wdt_trgr_pattern;
  68. __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  69. /* wait for posted write to complete */
  70. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  71. cpu_relax();
  72. /* reloaded WCRR from WLDR */
  73. }
  74. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  75. {
  76. void __iomem *base = wdev->base;
  77. /* Sequence to enable the watchdog */
  78. __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
  79. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  80. cpu_relax();
  81. __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
  82. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  83. cpu_relax();
  84. }
  85. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  86. {
  87. void __iomem *base = wdev->base;
  88. /* sequence required to disable watchdog */
  89. __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  90. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  91. cpu_relax();
  92. __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  93. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  94. cpu_relax();
  95. }
  96. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  97. {
  98. if (new_timeout < TIMER_MARGIN_MIN)
  99. new_timeout = TIMER_MARGIN_DEFAULT;
  100. if (new_timeout > TIMER_MARGIN_MAX)
  101. new_timeout = TIMER_MARGIN_MAX;
  102. timer_margin = new_timeout;
  103. }
  104. static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
  105. {
  106. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  107. void __iomem *base = wdev->base;
  108. pm_runtime_get_sync(wdev->dev);
  109. /* just count up at 32 KHz */
  110. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  111. cpu_relax();
  112. __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
  113. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  114. cpu_relax();
  115. pm_runtime_put_sync(wdev->dev);
  116. }
  117. /*
  118. * Allow only one task to hold it open
  119. */
  120. static int omap_wdt_open(struct inode *inode, struct file *file)
  121. {
  122. struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
  123. void __iomem *base = wdev->base;
  124. if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
  125. return -EBUSY;
  126. pm_runtime_get_sync(wdev->dev);
  127. /* initialize prescaler */
  128. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  129. cpu_relax();
  130. __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  131. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  132. cpu_relax();
  133. file->private_data = (void *) wdev;
  134. omap_wdt_set_timeout(wdev);
  135. omap_wdt_ping(wdev); /* trigger loading of new timeout value */
  136. omap_wdt_enable(wdev);
  137. pm_runtime_put_sync(wdev->dev);
  138. return nonseekable_open(inode, file);
  139. }
  140. static int omap_wdt_release(struct inode *inode, struct file *file)
  141. {
  142. struct omap_wdt_dev *wdev = file->private_data;
  143. /*
  144. * Shut off the timer unless NOWAYOUT is defined.
  145. */
  146. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  147. pm_runtime_get_sync(wdev->dev);
  148. omap_wdt_disable(wdev);
  149. pm_runtime_put_sync(wdev->dev);
  150. #else
  151. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  152. #endif
  153. wdev->omap_wdt_users = 0;
  154. return 0;
  155. }
  156. static ssize_t omap_wdt_write(struct file *file, const char __user *data,
  157. size_t len, loff_t *ppos)
  158. {
  159. struct omap_wdt_dev *wdev = file->private_data;
  160. /* Refresh LOAD_TIME. */
  161. if (len) {
  162. pm_runtime_get_sync(wdev->dev);
  163. spin_lock(&wdt_lock);
  164. omap_wdt_ping(wdev);
  165. spin_unlock(&wdt_lock);
  166. pm_runtime_put_sync(wdev->dev);
  167. }
  168. return len;
  169. }
  170. static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
  171. unsigned long arg)
  172. {
  173. struct omap_wdt_dev *wdev;
  174. int new_margin;
  175. static const struct watchdog_info ident = {
  176. .identity = "OMAP Watchdog",
  177. .options = WDIOF_SETTIMEOUT,
  178. .firmware_version = 0,
  179. };
  180. wdev = file->private_data;
  181. switch (cmd) {
  182. case WDIOC_GETSUPPORT:
  183. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  184. sizeof(ident));
  185. case WDIOC_GETSTATUS:
  186. return put_user(0, (int __user *)arg);
  187. case WDIOC_GETBOOTSTATUS:
  188. if (cpu_is_omap16xx())
  189. return put_user(__raw_readw(ARM_SYSST),
  190. (int __user *)arg);
  191. if (cpu_is_omap24xx())
  192. return put_user(omap_prcm_get_reset_sources(),
  193. (int __user *)arg);
  194. case WDIOC_KEEPALIVE:
  195. pm_runtime_get_sync(wdev->dev);
  196. spin_lock(&wdt_lock);
  197. omap_wdt_ping(wdev);
  198. spin_unlock(&wdt_lock);
  199. pm_runtime_put_sync(wdev->dev);
  200. return 0;
  201. case WDIOC_SETTIMEOUT:
  202. if (get_user(new_margin, (int __user *)arg))
  203. return -EFAULT;
  204. omap_wdt_adjust_timeout(new_margin);
  205. pm_runtime_get_sync(wdev->dev);
  206. spin_lock(&wdt_lock);
  207. omap_wdt_disable(wdev);
  208. omap_wdt_set_timeout(wdev);
  209. omap_wdt_enable(wdev);
  210. omap_wdt_ping(wdev);
  211. spin_unlock(&wdt_lock);
  212. pm_runtime_put_sync(wdev->dev);
  213. /* Fall */
  214. case WDIOC_GETTIMEOUT:
  215. return put_user(timer_margin, (int __user *)arg);
  216. default:
  217. return -ENOTTY;
  218. }
  219. }
  220. static const struct file_operations omap_wdt_fops = {
  221. .owner = THIS_MODULE,
  222. .write = omap_wdt_write,
  223. .unlocked_ioctl = omap_wdt_ioctl,
  224. .open = omap_wdt_open,
  225. .release = omap_wdt_release,
  226. .llseek = no_llseek,
  227. };
  228. static int __devinit omap_wdt_probe(struct platform_device *pdev)
  229. {
  230. struct resource *res, *mem;
  231. struct omap_wdt_dev *wdev;
  232. int ret;
  233. /* reserve static register mappings */
  234. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  235. if (!res) {
  236. ret = -ENOENT;
  237. goto err_get_resource;
  238. }
  239. if (omap_wdt_dev) {
  240. ret = -EBUSY;
  241. goto err_busy;
  242. }
  243. mem = request_mem_region(res->start, resource_size(res), pdev->name);
  244. if (!mem) {
  245. ret = -EBUSY;
  246. goto err_busy;
  247. }
  248. wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
  249. if (!wdev) {
  250. ret = -ENOMEM;
  251. goto err_kzalloc;
  252. }
  253. wdev->omap_wdt_users = 0;
  254. wdev->mem = mem;
  255. wdev->dev = &pdev->dev;
  256. wdev->base = ioremap(res->start, resource_size(res));
  257. if (!wdev->base) {
  258. ret = -ENOMEM;
  259. goto err_ioremap;
  260. }
  261. platform_set_drvdata(pdev, wdev);
  262. pm_runtime_enable(wdev->dev);
  263. pm_runtime_get_sync(wdev->dev);
  264. omap_wdt_disable(wdev);
  265. omap_wdt_adjust_timeout(timer_margin);
  266. wdev->omap_wdt_miscdev.parent = &pdev->dev;
  267. wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
  268. wdev->omap_wdt_miscdev.name = "watchdog";
  269. wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
  270. ret = misc_register(&(wdev->omap_wdt_miscdev));
  271. if (ret)
  272. goto err_misc;
  273. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  274. __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  275. timer_margin);
  276. pm_runtime_put_sync(wdev->dev);
  277. omap_wdt_dev = pdev;
  278. return 0;
  279. err_misc:
  280. platform_set_drvdata(pdev, NULL);
  281. iounmap(wdev->base);
  282. err_ioremap:
  283. wdev->base = NULL;
  284. kfree(wdev);
  285. err_kzalloc:
  286. release_mem_region(res->start, resource_size(res));
  287. err_busy:
  288. err_get_resource:
  289. return ret;
  290. }
  291. static void omap_wdt_shutdown(struct platform_device *pdev)
  292. {
  293. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  294. if (wdev->omap_wdt_users) {
  295. pm_runtime_get_sync(wdev->dev);
  296. omap_wdt_disable(wdev);
  297. pm_runtime_put_sync(wdev->dev);
  298. }
  299. }
  300. static int __devexit omap_wdt_remove(struct platform_device *pdev)
  301. {
  302. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  303. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  304. if (!res)
  305. return -ENOENT;
  306. misc_deregister(&(wdev->omap_wdt_miscdev));
  307. release_mem_region(res->start, resource_size(res));
  308. platform_set_drvdata(pdev, NULL);
  309. iounmap(wdev->base);
  310. kfree(wdev);
  311. omap_wdt_dev = NULL;
  312. return 0;
  313. }
  314. #ifdef CONFIG_PM
  315. /* REVISIT ... not clear this is the best way to handle system suspend; and
  316. * it's very inappropriate for selective device suspend (e.g. suspending this
  317. * through sysfs rather than by stopping the watchdog daemon). Also, this
  318. * may not play well enough with NOWAYOUT...
  319. */
  320. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  321. {
  322. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  323. if (wdev->omap_wdt_users) {
  324. pm_runtime_get_sync(wdev->dev);
  325. omap_wdt_disable(wdev);
  326. pm_runtime_put_sync(wdev->dev);
  327. }
  328. return 0;
  329. }
  330. static int omap_wdt_resume(struct platform_device *pdev)
  331. {
  332. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  333. if (wdev->omap_wdt_users) {
  334. pm_runtime_get_sync(wdev->dev);
  335. omap_wdt_enable(wdev);
  336. omap_wdt_ping(wdev);
  337. pm_runtime_put_sync(wdev->dev);
  338. }
  339. return 0;
  340. }
  341. #else
  342. #define omap_wdt_suspend NULL
  343. #define omap_wdt_resume NULL
  344. #endif
  345. static struct platform_driver omap_wdt_driver = {
  346. .probe = omap_wdt_probe,
  347. .remove = __devexit_p(omap_wdt_remove),
  348. .shutdown = omap_wdt_shutdown,
  349. .suspend = omap_wdt_suspend,
  350. .resume = omap_wdt_resume,
  351. .driver = {
  352. .owner = THIS_MODULE,
  353. .name = "omap_wdt",
  354. },
  355. };
  356. static int __init omap_wdt_init(void)
  357. {
  358. spin_lock_init(&wdt_lock);
  359. return platform_driver_register(&omap_wdt_driver);
  360. }
  361. static void __exit omap_wdt_exit(void)
  362. {
  363. platform_driver_unregister(&omap_wdt_driver);
  364. }
  365. module_init(omap_wdt_init);
  366. module_exit(omap_wdt_exit);
  367. MODULE_AUTHOR("George G. Davis");
  368. MODULE_LICENSE("GPL");
  369. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  370. MODULE_ALIAS("platform:omap_wdt");