dpi.c 7.7 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dpi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "DPI"
  23. #include <linux/kernel.h>
  24. #include <linux/clk.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <linux/errno.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <video/omapdss.h>
  31. #include <plat/cpu.h>
  32. #include "dss.h"
  33. static struct {
  34. struct regulator *vdds_dsi_reg;
  35. struct platform_device *dsidev;
  36. } dpi;
  37. static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
  38. {
  39. int dsi_module;
  40. dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
  41. return dsi_get_dsidev_from_id(dsi_module);
  42. }
  43. static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
  44. {
  45. if (dssdev->clocks.dispc.dispc_fclk_src ==
  46. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  47. dssdev->clocks.dispc.dispc_fclk_src ==
  48. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
  49. dssdev->clocks.dispc.channel.lcd_clk_src ==
  50. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  51. dssdev->clocks.dispc.channel.lcd_clk_src ==
  52. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
  53. return true;
  54. else
  55. return false;
  56. }
  57. static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
  58. unsigned long pck_req, unsigned long *fck, int *lck_div,
  59. int *pck_div)
  60. {
  61. struct dsi_clock_info dsi_cinfo;
  62. struct dispc_clock_info dispc_cinfo;
  63. int r;
  64. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
  65. &dsi_cinfo, &dispc_cinfo);
  66. if (r)
  67. return r;
  68. r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
  69. if (r)
  70. return r;
  71. dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
  72. r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  73. if (r)
  74. return r;
  75. *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  76. *lck_div = dispc_cinfo.lck_div;
  77. *pck_div = dispc_cinfo.pck_div;
  78. return 0;
  79. }
  80. static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
  81. unsigned long pck_req, unsigned long *fck, int *lck_div,
  82. int *pck_div)
  83. {
  84. struct dss_clock_info dss_cinfo;
  85. struct dispc_clock_info dispc_cinfo;
  86. int r;
  87. r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
  88. if (r)
  89. return r;
  90. r = dss_set_clock_div(&dss_cinfo);
  91. if (r)
  92. return r;
  93. r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  94. if (r)
  95. return r;
  96. *fck = dss_cinfo.fck;
  97. *lck_div = dispc_cinfo.lck_div;
  98. *pck_div = dispc_cinfo.pck_div;
  99. return 0;
  100. }
  101. static int dpi_set_mode(struct omap_dss_device *dssdev)
  102. {
  103. struct omap_video_timings *t = &dssdev->panel.timings;
  104. int lck_div = 0, pck_div = 0;
  105. unsigned long fck = 0;
  106. unsigned long pck;
  107. bool is_tft;
  108. int r = 0;
  109. dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
  110. dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
  111. dssdev->panel.acbi, dssdev->panel.acb);
  112. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  113. if (dpi_use_dsi_pll(dssdev))
  114. r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
  115. &fck, &lck_div, &pck_div);
  116. else
  117. r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
  118. &fck, &lck_div, &pck_div);
  119. if (r)
  120. goto err0;
  121. pck = fck / lck_div / pck_div / 1000;
  122. if (pck != t->pixel_clock) {
  123. DSSWARN("Could not find exact pixel clock. "
  124. "Requested %d kHz, got %lu kHz\n",
  125. t->pixel_clock, pck);
  126. t->pixel_clock = pck;
  127. }
  128. dispc_set_lcd_timings(dssdev->manager->id, t);
  129. err0:
  130. dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
  131. return r;
  132. }
  133. static int dpi_basic_init(struct omap_dss_device *dssdev)
  134. {
  135. bool is_tft;
  136. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  137. dispc_set_parallel_interface_mode(dssdev->manager->id,
  138. OMAP_DSS_PARALLELMODE_BYPASS);
  139. dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
  140. OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
  141. dispc_set_tft_data_lines(dssdev->manager->id,
  142. dssdev->phy.dpi.data_lines);
  143. return 0;
  144. }
  145. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
  146. {
  147. int r;
  148. r = omap_dss_start_device(dssdev);
  149. if (r) {
  150. DSSERR("failed to start device\n");
  151. goto err0;
  152. }
  153. if (cpu_is_omap34xx()) {
  154. r = regulator_enable(dpi.vdds_dsi_reg);
  155. if (r)
  156. goto err1;
  157. }
  158. dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
  159. r = dpi_basic_init(dssdev);
  160. if (r)
  161. goto err2;
  162. if (dpi_use_dsi_pll(dssdev)) {
  163. dss_clk_enable(DSS_CLK_SYSCK);
  164. r = dsi_pll_init(dpi.dsidev, 0, 1);
  165. if (r)
  166. goto err3;
  167. }
  168. r = dpi_set_mode(dssdev);
  169. if (r)
  170. goto err4;
  171. mdelay(2);
  172. dssdev->manager->enable(dssdev->manager);
  173. return 0;
  174. err4:
  175. if (dpi_use_dsi_pll(dssdev))
  176. dsi_pll_uninit(dpi.dsidev, true);
  177. err3:
  178. if (dpi_use_dsi_pll(dssdev))
  179. dss_clk_disable(DSS_CLK_SYSCK);
  180. err2:
  181. dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
  182. if (cpu_is_omap34xx())
  183. regulator_disable(dpi.vdds_dsi_reg);
  184. err1:
  185. omap_dss_stop_device(dssdev);
  186. err0:
  187. return r;
  188. }
  189. EXPORT_SYMBOL(omapdss_dpi_display_enable);
  190. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
  191. {
  192. dssdev->manager->disable(dssdev->manager);
  193. if (dpi_use_dsi_pll(dssdev)) {
  194. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  195. dsi_pll_uninit(dpi.dsidev, true);
  196. dss_clk_disable(DSS_CLK_SYSCK);
  197. }
  198. dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
  199. if (cpu_is_omap34xx())
  200. regulator_disable(dpi.vdds_dsi_reg);
  201. omap_dss_stop_device(dssdev);
  202. }
  203. EXPORT_SYMBOL(omapdss_dpi_display_disable);
  204. void dpi_set_timings(struct omap_dss_device *dssdev,
  205. struct omap_video_timings *timings)
  206. {
  207. DSSDBG("dpi_set_timings\n");
  208. dssdev->panel.timings = *timings;
  209. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  210. dpi_set_mode(dssdev);
  211. dispc_go(dssdev->manager->id);
  212. }
  213. }
  214. EXPORT_SYMBOL(dpi_set_timings);
  215. int dpi_check_timings(struct omap_dss_device *dssdev,
  216. struct omap_video_timings *timings)
  217. {
  218. bool is_tft;
  219. int r;
  220. int lck_div, pck_div;
  221. unsigned long fck;
  222. unsigned long pck;
  223. struct dispc_clock_info dispc_cinfo;
  224. if (!dispc_lcd_timings_ok(timings))
  225. return -EINVAL;
  226. if (timings->pixel_clock == 0)
  227. return -EINVAL;
  228. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  229. if (dpi_use_dsi_pll(dssdev)) {
  230. struct dsi_clock_info dsi_cinfo;
  231. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
  232. timings->pixel_clock * 1000,
  233. &dsi_cinfo, &dispc_cinfo);
  234. if (r)
  235. return r;
  236. fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  237. } else {
  238. struct dss_clock_info dss_cinfo;
  239. r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
  240. &dss_cinfo, &dispc_cinfo);
  241. if (r)
  242. return r;
  243. fck = dss_cinfo.fck;
  244. }
  245. lck_div = dispc_cinfo.lck_div;
  246. pck_div = dispc_cinfo.pck_div;
  247. pck = fck / lck_div / pck_div / 1000;
  248. timings->pixel_clock = pck;
  249. return 0;
  250. }
  251. EXPORT_SYMBOL(dpi_check_timings);
  252. int dpi_init_display(struct omap_dss_device *dssdev)
  253. {
  254. DSSDBG("init_display\n");
  255. if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
  256. struct regulator *vdds_dsi;
  257. vdds_dsi = dss_get_vdds_dsi();
  258. if (IS_ERR(vdds_dsi)) {
  259. DSSERR("can't get VDDS_DSI regulator\n");
  260. return PTR_ERR(vdds_dsi);
  261. }
  262. dpi.vdds_dsi_reg = vdds_dsi;
  263. }
  264. if (dpi_use_dsi_pll(dssdev)) {
  265. enum omap_dss_clk_source dispc_fclk_src =
  266. dssdev->clocks.dispc.dispc_fclk_src;
  267. dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
  268. }
  269. return 0;
  270. }
  271. int dpi_init(void)
  272. {
  273. return 0;
  274. }
  275. void dpi_exit(void)
  276. {
  277. }