r8a66597-udc.c 41 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/err.h>
  29. #include <linux/slab.h>
  30. #include <linux/usb/ch9.h>
  31. #include <linux/usb/gadget.h>
  32. #include "r8a66597-udc.h"
  33. #define DRIVER_VERSION "2009-08-18"
  34. static const char udc_name[] = "r8a66597_udc";
  35. static const char *r8a66597_ep_name[] = {
  36. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  37. "ep8", "ep9",
  38. };
  39. static void init_controller(struct r8a66597 *r8a66597);
  40. static void disable_controller(struct r8a66597 *r8a66597);
  41. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  42. static void irq_packet_write(struct r8a66597_ep *ep,
  43. struct r8a66597_request *req);
  44. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  45. gfp_t gfp_flags);
  46. static void transfer_complete(struct r8a66597_ep *ep,
  47. struct r8a66597_request *req, int status);
  48. /*-------------------------------------------------------------------------*/
  49. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  50. {
  51. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  52. }
  53. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = r8a66597_read(r8a66597, INTENB0);
  58. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  59. INTENB0);
  60. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  61. r8a66597_write(r8a66597, tmp, INTENB0);
  62. }
  63. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  64. unsigned long reg)
  65. {
  66. u16 tmp;
  67. tmp = r8a66597_read(r8a66597, INTENB0);
  68. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  69. INTENB0);
  70. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  71. r8a66597_write(r8a66597, tmp, INTENB0);
  72. }
  73. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  74. {
  75. r8a66597_bset(r8a66597, CTRE, INTENB0);
  76. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  77. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  78. }
  79. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  80. __releases(r8a66597->lock)
  81. __acquires(r8a66597->lock)
  82. {
  83. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  84. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  85. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  86. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  87. spin_unlock(&r8a66597->lock);
  88. r8a66597->driver->disconnect(&r8a66597->gadget);
  89. spin_lock(&r8a66597->lock);
  90. disable_controller(r8a66597);
  91. init_controller(r8a66597);
  92. r8a66597_bset(r8a66597, VBSE, INTENB0);
  93. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  94. }
  95. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  96. {
  97. u16 pid = 0;
  98. unsigned long offset;
  99. if (pipenum == 0)
  100. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  101. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  102. offset = get_pipectr_addr(pipenum);
  103. pid = r8a66597_read(r8a66597, offset) & PID;
  104. } else
  105. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  106. return pid;
  107. }
  108. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  109. u16 pid)
  110. {
  111. unsigned long offset;
  112. if (pipenum == 0)
  113. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  114. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  115. offset = get_pipectr_addr(pipenum);
  116. r8a66597_mdfy(r8a66597, pid, PID, offset);
  117. } else
  118. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  119. }
  120. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  121. {
  122. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  123. }
  124. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  125. {
  126. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  127. }
  128. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  129. {
  130. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  131. }
  132. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  133. {
  134. u16 ret = 0;
  135. unsigned long offset;
  136. if (pipenum == 0)
  137. ret = r8a66597_read(r8a66597, DCPCTR);
  138. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  139. offset = get_pipectr_addr(pipenum);
  140. ret = r8a66597_read(r8a66597, offset);
  141. } else
  142. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  143. return ret;
  144. }
  145. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  146. {
  147. unsigned long offset;
  148. pipe_stop(r8a66597, pipenum);
  149. if (pipenum == 0)
  150. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  151. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  152. offset = get_pipectr_addr(pipenum);
  153. r8a66597_bset(r8a66597, SQCLR, offset);
  154. } else
  155. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  156. }
  157. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  158. {
  159. u16 tmp;
  160. int size;
  161. if (pipenum == 0) {
  162. tmp = r8a66597_read(r8a66597, DCPCFG);
  163. if ((tmp & R8A66597_CNTMD) != 0)
  164. size = 256;
  165. else {
  166. tmp = r8a66597_read(r8a66597, DCPMAXP);
  167. size = tmp & MAXP;
  168. }
  169. } else {
  170. r8a66597_write(r8a66597, pipenum, PIPESEL);
  171. tmp = r8a66597_read(r8a66597, PIPECFG);
  172. if ((tmp & R8A66597_CNTMD) != 0) {
  173. tmp = r8a66597_read(r8a66597, PIPEBUF);
  174. size = ((tmp >> 10) + 1) * 64;
  175. } else {
  176. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  177. size = tmp & MXPS;
  178. }
  179. }
  180. return size;
  181. }
  182. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  183. {
  184. if (r8a66597->pdata->on_chip)
  185. return MBW_32;
  186. else
  187. return MBW_16;
  188. }
  189. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  190. {
  191. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  192. if (ep->use_dma)
  193. return;
  194. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  195. ndelay(450);
  196. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  197. }
  198. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  199. struct r8a66597_pipe_info *info)
  200. {
  201. u16 bufnum = 0, buf_bsize = 0;
  202. u16 pipecfg = 0;
  203. if (info->pipe == 0)
  204. return -EINVAL;
  205. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  206. if (info->dir_in)
  207. pipecfg |= R8A66597_DIR;
  208. pipecfg |= info->type;
  209. pipecfg |= info->epnum;
  210. switch (info->type) {
  211. case R8A66597_INT:
  212. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  213. buf_bsize = 0;
  214. break;
  215. case R8A66597_BULK:
  216. /* isochronous pipes may be used as bulk pipes */
  217. if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
  218. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  219. else
  220. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  221. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  222. buf_bsize = 7;
  223. pipecfg |= R8A66597_DBLB;
  224. if (!info->dir_in)
  225. pipecfg |= R8A66597_SHTNAK;
  226. break;
  227. case R8A66597_ISO:
  228. bufnum = R8A66597_BASE_BUFNUM +
  229. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  230. buf_bsize = 7;
  231. break;
  232. }
  233. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  234. pr_err("r8a66597 pipe memory is insufficient\n");
  235. return -ENOMEM;
  236. }
  237. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  238. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  239. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  240. if (info->interval)
  241. info->interval--;
  242. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  243. return 0;
  244. }
  245. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  246. struct r8a66597_pipe_info *info)
  247. {
  248. if (info->pipe == 0)
  249. return;
  250. if (is_bulk_pipe(info->pipe))
  251. r8a66597->bulk--;
  252. else if (is_interrupt_pipe(info->pipe))
  253. r8a66597->interrupt--;
  254. else if (is_isoc_pipe(info->pipe)) {
  255. r8a66597->isochronous--;
  256. if (info->type == R8A66597_BULK)
  257. r8a66597->bulk--;
  258. } else
  259. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  260. info->pipe);
  261. }
  262. static void pipe_initialize(struct r8a66597_ep *ep)
  263. {
  264. struct r8a66597 *r8a66597 = ep->r8a66597;
  265. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  266. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  267. r8a66597_write(r8a66597, 0, ep->pipectr);
  268. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  269. if (ep->use_dma) {
  270. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  271. ndelay(450);
  272. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  273. }
  274. }
  275. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  276. struct r8a66597_ep *ep,
  277. const struct usb_endpoint_descriptor *desc,
  278. u16 pipenum, int dma)
  279. {
  280. ep->use_dma = 0;
  281. ep->fifoaddr = CFIFO;
  282. ep->fifosel = CFIFOSEL;
  283. ep->fifoctr = CFIFOCTR;
  284. ep->fifotrn = 0;
  285. ep->pipectr = get_pipectr_addr(pipenum);
  286. ep->pipenum = pipenum;
  287. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  288. r8a66597->pipenum2ep[pipenum] = ep;
  289. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  290. = ep;
  291. INIT_LIST_HEAD(&ep->queue);
  292. }
  293. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  294. {
  295. struct r8a66597 *r8a66597 = ep->r8a66597;
  296. u16 pipenum = ep->pipenum;
  297. if (pipenum == 0)
  298. return;
  299. if (ep->use_dma)
  300. r8a66597->num_dma--;
  301. ep->pipenum = 0;
  302. ep->busy = 0;
  303. ep->use_dma = 0;
  304. }
  305. static int alloc_pipe_config(struct r8a66597_ep *ep,
  306. const struct usb_endpoint_descriptor *desc)
  307. {
  308. struct r8a66597 *r8a66597 = ep->r8a66597;
  309. struct r8a66597_pipe_info info;
  310. int dma = 0;
  311. unsigned char *counter;
  312. int ret;
  313. ep->desc = desc;
  314. if (ep->pipenum) /* already allocated pipe */
  315. return 0;
  316. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  317. case USB_ENDPOINT_XFER_BULK:
  318. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  319. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  320. printk(KERN_ERR "bulk pipe is insufficient\n");
  321. return -ENODEV;
  322. } else {
  323. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  324. + r8a66597->isochronous;
  325. counter = &r8a66597->isochronous;
  326. }
  327. } else {
  328. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  329. counter = &r8a66597->bulk;
  330. }
  331. info.type = R8A66597_BULK;
  332. dma = 1;
  333. break;
  334. case USB_ENDPOINT_XFER_INT:
  335. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  336. printk(KERN_ERR "interrupt pipe is insufficient\n");
  337. return -ENODEV;
  338. }
  339. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  340. info.type = R8A66597_INT;
  341. counter = &r8a66597->interrupt;
  342. break;
  343. case USB_ENDPOINT_XFER_ISOC:
  344. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  345. printk(KERN_ERR "isochronous pipe is insufficient\n");
  346. return -ENODEV;
  347. }
  348. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  349. info.type = R8A66597_ISO;
  350. counter = &r8a66597->isochronous;
  351. break;
  352. default:
  353. printk(KERN_ERR "unexpect xfer type\n");
  354. return -EINVAL;
  355. }
  356. ep->type = info.type;
  357. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  358. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  359. info.interval = desc->bInterval;
  360. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  361. info.dir_in = 1;
  362. else
  363. info.dir_in = 0;
  364. ret = pipe_buffer_setting(r8a66597, &info);
  365. if (ret < 0) {
  366. printk(KERN_ERR "pipe_buffer_setting fail\n");
  367. return ret;
  368. }
  369. (*counter)++;
  370. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  371. r8a66597->bulk++;
  372. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  373. pipe_initialize(ep);
  374. return 0;
  375. }
  376. static int free_pipe_config(struct r8a66597_ep *ep)
  377. {
  378. struct r8a66597 *r8a66597 = ep->r8a66597;
  379. struct r8a66597_pipe_info info;
  380. info.pipe = ep->pipenum;
  381. info.type = ep->type;
  382. pipe_buffer_release(r8a66597, &info);
  383. r8a66597_ep_release(ep);
  384. return 0;
  385. }
  386. /*-------------------------------------------------------------------------*/
  387. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  388. {
  389. enable_irq_ready(r8a66597, pipenum);
  390. enable_irq_nrdy(r8a66597, pipenum);
  391. }
  392. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  393. {
  394. disable_irq_ready(r8a66597, pipenum);
  395. disable_irq_nrdy(r8a66597, pipenum);
  396. }
  397. /* if complete is true, gadget driver complete function is not call */
  398. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  399. {
  400. r8a66597->ep[0].internal_ccpl = ccpl;
  401. pipe_start(r8a66597, 0);
  402. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  403. }
  404. static void start_ep0_write(struct r8a66597_ep *ep,
  405. struct r8a66597_request *req)
  406. {
  407. struct r8a66597 *r8a66597 = ep->r8a66597;
  408. pipe_change(r8a66597, ep->pipenum);
  409. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  410. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  411. if (req->req.length == 0) {
  412. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  413. pipe_start(r8a66597, 0);
  414. transfer_complete(ep, req, 0);
  415. } else {
  416. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  417. irq_ep0_write(ep, req);
  418. }
  419. }
  420. static void start_packet_write(struct r8a66597_ep *ep,
  421. struct r8a66597_request *req)
  422. {
  423. struct r8a66597 *r8a66597 = ep->r8a66597;
  424. u16 tmp;
  425. pipe_change(r8a66597, ep->pipenum);
  426. disable_irq_empty(r8a66597, ep->pipenum);
  427. pipe_start(r8a66597, ep->pipenum);
  428. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  429. if (unlikely((tmp & FRDY) == 0))
  430. pipe_irq_enable(r8a66597, ep->pipenum);
  431. else
  432. irq_packet_write(ep, req);
  433. }
  434. static void start_packet_read(struct r8a66597_ep *ep,
  435. struct r8a66597_request *req)
  436. {
  437. struct r8a66597 *r8a66597 = ep->r8a66597;
  438. u16 pipenum = ep->pipenum;
  439. if (ep->pipenum == 0) {
  440. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  441. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  442. pipe_start(r8a66597, pipenum);
  443. pipe_irq_enable(r8a66597, pipenum);
  444. } else {
  445. if (ep->use_dma) {
  446. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  447. pipe_change(r8a66597, pipenum);
  448. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  449. r8a66597_write(r8a66597,
  450. (req->req.length + ep->ep.maxpacket - 1)
  451. / ep->ep.maxpacket,
  452. ep->fifotrn);
  453. }
  454. pipe_start(r8a66597, pipenum); /* trigger once */
  455. pipe_irq_enable(r8a66597, pipenum);
  456. }
  457. }
  458. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  459. {
  460. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  461. start_packet_write(ep, req);
  462. else
  463. start_packet_read(ep, req);
  464. }
  465. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  466. {
  467. u16 ctsq;
  468. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  469. switch (ctsq) {
  470. case CS_RDDS:
  471. start_ep0_write(ep, req);
  472. break;
  473. case CS_WRDS:
  474. start_packet_read(ep, req);
  475. break;
  476. case CS_WRND:
  477. control_end(ep->r8a66597, 0);
  478. break;
  479. default:
  480. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  481. break;
  482. }
  483. }
  484. static void init_controller(struct r8a66597 *r8a66597)
  485. {
  486. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  487. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  488. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  489. if (r8a66597->pdata->on_chip) {
  490. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  491. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  492. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  493. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  494. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  495. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  496. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  497. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  498. DMA0CFG);
  499. } else {
  500. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  501. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  502. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  503. XTAL, SYSCFG0);
  504. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  505. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  506. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  507. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  508. msleep(3);
  509. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  510. msleep(1);
  511. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  512. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  513. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  514. DMA0CFG);
  515. }
  516. }
  517. static void disable_controller(struct r8a66597 *r8a66597)
  518. {
  519. if (r8a66597->pdata->on_chip) {
  520. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  521. /* disable interrupts */
  522. r8a66597_write(r8a66597, 0, INTENB0);
  523. r8a66597_write(r8a66597, 0, INTENB1);
  524. r8a66597_write(r8a66597, 0, BRDYENB);
  525. r8a66597_write(r8a66597, 0, BEMPENB);
  526. r8a66597_write(r8a66597, 0, NRDYENB);
  527. /* clear status */
  528. r8a66597_write(r8a66597, 0, BRDYSTS);
  529. r8a66597_write(r8a66597, 0, NRDYSTS);
  530. r8a66597_write(r8a66597, 0, BEMPSTS);
  531. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  532. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  533. } else {
  534. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  535. udelay(1);
  536. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  537. udelay(1);
  538. udelay(1);
  539. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  540. }
  541. }
  542. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  543. {
  544. u16 tmp;
  545. if (!r8a66597->pdata->on_chip) {
  546. tmp = r8a66597_read(r8a66597, SYSCFG0);
  547. if (!(tmp & XCKE))
  548. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  549. }
  550. }
  551. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  552. {
  553. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  554. }
  555. /*-------------------------------------------------------------------------*/
  556. static void transfer_complete(struct r8a66597_ep *ep,
  557. struct r8a66597_request *req, int status)
  558. __releases(r8a66597->lock)
  559. __acquires(r8a66597->lock)
  560. {
  561. int restart = 0;
  562. if (unlikely(ep->pipenum == 0)) {
  563. if (ep->internal_ccpl) {
  564. ep->internal_ccpl = 0;
  565. return;
  566. }
  567. }
  568. list_del_init(&req->queue);
  569. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  570. req->req.status = -ESHUTDOWN;
  571. else
  572. req->req.status = status;
  573. if (!list_empty(&ep->queue))
  574. restart = 1;
  575. spin_unlock(&ep->r8a66597->lock);
  576. req->req.complete(&ep->ep, &req->req);
  577. spin_lock(&ep->r8a66597->lock);
  578. if (restart) {
  579. req = get_request_from_ep(ep);
  580. if (ep->desc)
  581. start_packet(ep, req);
  582. }
  583. }
  584. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  585. {
  586. int i;
  587. u16 tmp;
  588. unsigned bufsize;
  589. size_t size;
  590. void *buf;
  591. u16 pipenum = ep->pipenum;
  592. struct r8a66597 *r8a66597 = ep->r8a66597;
  593. pipe_change(r8a66597, pipenum);
  594. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  595. i = 0;
  596. do {
  597. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  598. if (i++ > 100000) {
  599. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  600. "conflict. please power off this controller.");
  601. return;
  602. }
  603. ndelay(1);
  604. } while ((tmp & FRDY) == 0);
  605. /* prepare parameters */
  606. bufsize = get_buffer_size(r8a66597, pipenum);
  607. buf = req->req.buf + req->req.actual;
  608. size = min(bufsize, req->req.length - req->req.actual);
  609. /* write fifo */
  610. if (req->req.buf) {
  611. if (size > 0)
  612. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  613. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  614. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  615. }
  616. /* update parameters */
  617. req->req.actual += size;
  618. /* check transfer finish */
  619. if ((!req->req.zero && (req->req.actual == req->req.length))
  620. || (size % ep->ep.maxpacket)
  621. || (size == 0)) {
  622. disable_irq_ready(r8a66597, pipenum);
  623. disable_irq_empty(r8a66597, pipenum);
  624. } else {
  625. disable_irq_ready(r8a66597, pipenum);
  626. enable_irq_empty(r8a66597, pipenum);
  627. }
  628. pipe_start(r8a66597, pipenum);
  629. }
  630. static void irq_packet_write(struct r8a66597_ep *ep,
  631. struct r8a66597_request *req)
  632. {
  633. u16 tmp;
  634. unsigned bufsize;
  635. size_t size;
  636. void *buf;
  637. u16 pipenum = ep->pipenum;
  638. struct r8a66597 *r8a66597 = ep->r8a66597;
  639. pipe_change(r8a66597, pipenum);
  640. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  641. if (unlikely((tmp & FRDY) == 0)) {
  642. pipe_stop(r8a66597, pipenum);
  643. pipe_irq_disable(r8a66597, pipenum);
  644. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  645. return;
  646. }
  647. /* prepare parameters */
  648. bufsize = get_buffer_size(r8a66597, pipenum);
  649. buf = req->req.buf + req->req.actual;
  650. size = min(bufsize, req->req.length - req->req.actual);
  651. /* write fifo */
  652. if (req->req.buf) {
  653. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  654. if ((size == 0)
  655. || ((size % ep->ep.maxpacket) != 0)
  656. || ((bufsize != ep->ep.maxpacket)
  657. && (bufsize > size)))
  658. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  659. }
  660. /* update parameters */
  661. req->req.actual += size;
  662. /* check transfer finish */
  663. if ((!req->req.zero && (req->req.actual == req->req.length))
  664. || (size % ep->ep.maxpacket)
  665. || (size == 0)) {
  666. disable_irq_ready(r8a66597, pipenum);
  667. enable_irq_empty(r8a66597, pipenum);
  668. } else {
  669. disable_irq_empty(r8a66597, pipenum);
  670. pipe_irq_enable(r8a66597, pipenum);
  671. }
  672. }
  673. static void irq_packet_read(struct r8a66597_ep *ep,
  674. struct r8a66597_request *req)
  675. {
  676. u16 tmp;
  677. int rcv_len, bufsize, req_len;
  678. int size;
  679. void *buf;
  680. u16 pipenum = ep->pipenum;
  681. struct r8a66597 *r8a66597 = ep->r8a66597;
  682. int finish = 0;
  683. pipe_change(r8a66597, pipenum);
  684. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  685. if (unlikely((tmp & FRDY) == 0)) {
  686. req->req.status = -EPIPE;
  687. pipe_stop(r8a66597, pipenum);
  688. pipe_irq_disable(r8a66597, pipenum);
  689. printk(KERN_ERR "read fifo not ready");
  690. return;
  691. }
  692. /* prepare parameters */
  693. rcv_len = tmp & DTLN;
  694. bufsize = get_buffer_size(r8a66597, pipenum);
  695. buf = req->req.buf + req->req.actual;
  696. req_len = req->req.length - req->req.actual;
  697. if (rcv_len < bufsize)
  698. size = min(rcv_len, req_len);
  699. else
  700. size = min(bufsize, req_len);
  701. /* update parameters */
  702. req->req.actual += size;
  703. /* check transfer finish */
  704. if ((!req->req.zero && (req->req.actual == req->req.length))
  705. || (size % ep->ep.maxpacket)
  706. || (size == 0)) {
  707. pipe_stop(r8a66597, pipenum);
  708. pipe_irq_disable(r8a66597, pipenum);
  709. finish = 1;
  710. }
  711. /* read fifo */
  712. if (req->req.buf) {
  713. if (size == 0)
  714. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  715. else
  716. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  717. }
  718. if ((ep->pipenum != 0) && finish)
  719. transfer_complete(ep, req, 0);
  720. }
  721. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  722. {
  723. u16 check;
  724. u16 pipenum;
  725. struct r8a66597_ep *ep;
  726. struct r8a66597_request *req;
  727. if ((status & BRDY0) && (enb & BRDY0)) {
  728. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  729. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  730. ep = &r8a66597->ep[0];
  731. req = get_request_from_ep(ep);
  732. irq_packet_read(ep, req);
  733. } else {
  734. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  735. check = 1 << pipenum;
  736. if ((status & check) && (enb & check)) {
  737. r8a66597_write(r8a66597, ~check, BRDYSTS);
  738. ep = r8a66597->pipenum2ep[pipenum];
  739. req = get_request_from_ep(ep);
  740. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  741. irq_packet_write(ep, req);
  742. else
  743. irq_packet_read(ep, req);
  744. }
  745. }
  746. }
  747. }
  748. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  749. {
  750. u16 tmp;
  751. u16 check;
  752. u16 pipenum;
  753. struct r8a66597_ep *ep;
  754. struct r8a66597_request *req;
  755. if ((status & BEMP0) && (enb & BEMP0)) {
  756. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  757. ep = &r8a66597->ep[0];
  758. req = get_request_from_ep(ep);
  759. irq_ep0_write(ep, req);
  760. } else {
  761. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  762. check = 1 << pipenum;
  763. if ((status & check) && (enb & check)) {
  764. r8a66597_write(r8a66597, ~check, BEMPSTS);
  765. tmp = control_reg_get(r8a66597, pipenum);
  766. if ((tmp & INBUFM) == 0) {
  767. disable_irq_empty(r8a66597, pipenum);
  768. pipe_irq_disable(r8a66597, pipenum);
  769. pipe_stop(r8a66597, pipenum);
  770. ep = r8a66597->pipenum2ep[pipenum];
  771. req = get_request_from_ep(ep);
  772. if (!list_empty(&ep->queue))
  773. transfer_complete(ep, req, 0);
  774. }
  775. }
  776. }
  777. }
  778. }
  779. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  780. __releases(r8a66597->lock)
  781. __acquires(r8a66597->lock)
  782. {
  783. struct r8a66597_ep *ep;
  784. u16 pid;
  785. u16 status = 0;
  786. u16 w_index = le16_to_cpu(ctrl->wIndex);
  787. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  788. case USB_RECIP_DEVICE:
  789. status = 1 << USB_DEVICE_SELF_POWERED;
  790. break;
  791. case USB_RECIP_INTERFACE:
  792. status = 0;
  793. break;
  794. case USB_RECIP_ENDPOINT:
  795. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  796. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  797. if (pid == PID_STALL)
  798. status = 1 << USB_ENDPOINT_HALT;
  799. else
  800. status = 0;
  801. break;
  802. default:
  803. pipe_stall(r8a66597, 0);
  804. return; /* exit */
  805. }
  806. r8a66597->ep0_data = cpu_to_le16(status);
  807. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  808. r8a66597->ep0_req->length = 2;
  809. /* AV: what happens if we get called again before that gets through? */
  810. spin_unlock(&r8a66597->lock);
  811. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  812. spin_lock(&r8a66597->lock);
  813. }
  814. static void clear_feature(struct r8a66597 *r8a66597,
  815. struct usb_ctrlrequest *ctrl)
  816. {
  817. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  818. case USB_RECIP_DEVICE:
  819. control_end(r8a66597, 1);
  820. break;
  821. case USB_RECIP_INTERFACE:
  822. control_end(r8a66597, 1);
  823. break;
  824. case USB_RECIP_ENDPOINT: {
  825. struct r8a66597_ep *ep;
  826. struct r8a66597_request *req;
  827. u16 w_index = le16_to_cpu(ctrl->wIndex);
  828. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  829. if (!ep->wedge) {
  830. pipe_stop(r8a66597, ep->pipenum);
  831. control_reg_sqclr(r8a66597, ep->pipenum);
  832. spin_unlock(&r8a66597->lock);
  833. usb_ep_clear_halt(&ep->ep);
  834. spin_lock(&r8a66597->lock);
  835. }
  836. control_end(r8a66597, 1);
  837. req = get_request_from_ep(ep);
  838. if (ep->busy) {
  839. ep->busy = 0;
  840. if (list_empty(&ep->queue))
  841. break;
  842. start_packet(ep, req);
  843. } else if (!list_empty(&ep->queue))
  844. pipe_start(r8a66597, ep->pipenum);
  845. }
  846. break;
  847. default:
  848. pipe_stall(r8a66597, 0);
  849. break;
  850. }
  851. }
  852. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  853. {
  854. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  855. case USB_RECIP_DEVICE:
  856. control_end(r8a66597, 1);
  857. break;
  858. case USB_RECIP_INTERFACE:
  859. control_end(r8a66597, 1);
  860. break;
  861. case USB_RECIP_ENDPOINT: {
  862. struct r8a66597_ep *ep;
  863. u16 w_index = le16_to_cpu(ctrl->wIndex);
  864. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  865. pipe_stall(r8a66597, ep->pipenum);
  866. control_end(r8a66597, 1);
  867. }
  868. break;
  869. default:
  870. pipe_stall(r8a66597, 0);
  871. break;
  872. }
  873. }
  874. /* if return value is true, call class driver's setup() */
  875. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  876. {
  877. u16 *p = (u16 *)ctrl;
  878. unsigned long offset = USBREQ;
  879. int i, ret = 0;
  880. /* read fifo */
  881. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  882. for (i = 0; i < 4; i++)
  883. p[i] = r8a66597_read(r8a66597, offset + i*2);
  884. /* check request */
  885. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  886. switch (ctrl->bRequest) {
  887. case USB_REQ_GET_STATUS:
  888. get_status(r8a66597, ctrl);
  889. break;
  890. case USB_REQ_CLEAR_FEATURE:
  891. clear_feature(r8a66597, ctrl);
  892. break;
  893. case USB_REQ_SET_FEATURE:
  894. set_feature(r8a66597, ctrl);
  895. break;
  896. default:
  897. ret = 1;
  898. break;
  899. }
  900. } else
  901. ret = 1;
  902. return ret;
  903. }
  904. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  905. {
  906. u16 speed = get_usb_speed(r8a66597);
  907. switch (speed) {
  908. case HSMODE:
  909. r8a66597->gadget.speed = USB_SPEED_HIGH;
  910. break;
  911. case FSMODE:
  912. r8a66597->gadget.speed = USB_SPEED_FULL;
  913. break;
  914. default:
  915. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  916. printk(KERN_ERR "USB speed unknown\n");
  917. }
  918. }
  919. static void irq_device_state(struct r8a66597 *r8a66597)
  920. {
  921. u16 dvsq;
  922. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  923. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  924. if (dvsq == DS_DFLT) {
  925. /* bus reset */
  926. spin_unlock(&r8a66597->lock);
  927. r8a66597->driver->disconnect(&r8a66597->gadget);
  928. spin_lock(&r8a66597->lock);
  929. r8a66597_update_usb_speed(r8a66597);
  930. }
  931. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  932. r8a66597_update_usb_speed(r8a66597);
  933. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  934. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  935. r8a66597_update_usb_speed(r8a66597);
  936. r8a66597->old_dvsq = dvsq;
  937. }
  938. static void irq_control_stage(struct r8a66597 *r8a66597)
  939. __releases(r8a66597->lock)
  940. __acquires(r8a66597->lock)
  941. {
  942. struct usb_ctrlrequest ctrl;
  943. u16 ctsq;
  944. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  945. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  946. switch (ctsq) {
  947. case CS_IDST: {
  948. struct r8a66597_ep *ep;
  949. struct r8a66597_request *req;
  950. ep = &r8a66597->ep[0];
  951. req = get_request_from_ep(ep);
  952. transfer_complete(ep, req, 0);
  953. }
  954. break;
  955. case CS_RDDS:
  956. case CS_WRDS:
  957. case CS_WRND:
  958. if (setup_packet(r8a66597, &ctrl)) {
  959. spin_unlock(&r8a66597->lock);
  960. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  961. < 0)
  962. pipe_stall(r8a66597, 0);
  963. spin_lock(&r8a66597->lock);
  964. }
  965. break;
  966. case CS_RDSS:
  967. case CS_WRSS:
  968. control_end(r8a66597, 0);
  969. break;
  970. default:
  971. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  972. break;
  973. }
  974. }
  975. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  976. {
  977. struct r8a66597 *r8a66597 = _r8a66597;
  978. u16 intsts0;
  979. u16 intenb0;
  980. u16 brdysts, nrdysts, bempsts;
  981. u16 brdyenb, nrdyenb, bempenb;
  982. u16 savepipe;
  983. u16 mask0;
  984. spin_lock(&r8a66597->lock);
  985. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  986. intenb0 = r8a66597_read(r8a66597, INTENB0);
  987. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  988. mask0 = intsts0 & intenb0;
  989. if (mask0) {
  990. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  991. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  992. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  993. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  994. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  995. bempenb = r8a66597_read(r8a66597, BEMPENB);
  996. if (mask0 & VBINT) {
  997. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  998. INTSTS0);
  999. r8a66597_start_xclock(r8a66597);
  1000. /* start vbus sampling */
  1001. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  1002. & VBSTS;
  1003. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1004. mod_timer(&r8a66597->timer,
  1005. jiffies + msecs_to_jiffies(50));
  1006. }
  1007. if (intsts0 & DVSQ)
  1008. irq_device_state(r8a66597);
  1009. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1010. && (brdysts & brdyenb))
  1011. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1012. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1013. && (bempsts & bempenb))
  1014. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1015. if (intsts0 & CTRT)
  1016. irq_control_stage(r8a66597);
  1017. }
  1018. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1019. spin_unlock(&r8a66597->lock);
  1020. return IRQ_HANDLED;
  1021. }
  1022. static void r8a66597_timer(unsigned long _r8a66597)
  1023. {
  1024. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1025. unsigned long flags;
  1026. u16 tmp;
  1027. spin_lock_irqsave(&r8a66597->lock, flags);
  1028. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1029. if (r8a66597->scount > 0) {
  1030. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1031. if (tmp == r8a66597->old_vbus) {
  1032. r8a66597->scount--;
  1033. if (r8a66597->scount == 0) {
  1034. if (tmp == VBSTS)
  1035. r8a66597_usb_connect(r8a66597);
  1036. else
  1037. r8a66597_usb_disconnect(r8a66597);
  1038. } else {
  1039. mod_timer(&r8a66597->timer,
  1040. jiffies + msecs_to_jiffies(50));
  1041. }
  1042. } else {
  1043. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1044. r8a66597->old_vbus = tmp;
  1045. mod_timer(&r8a66597->timer,
  1046. jiffies + msecs_to_jiffies(50));
  1047. }
  1048. }
  1049. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1050. }
  1051. /*-------------------------------------------------------------------------*/
  1052. static int r8a66597_enable(struct usb_ep *_ep,
  1053. const struct usb_endpoint_descriptor *desc)
  1054. {
  1055. struct r8a66597_ep *ep;
  1056. ep = container_of(_ep, struct r8a66597_ep, ep);
  1057. return alloc_pipe_config(ep, desc);
  1058. }
  1059. static int r8a66597_disable(struct usb_ep *_ep)
  1060. {
  1061. struct r8a66597_ep *ep;
  1062. struct r8a66597_request *req;
  1063. unsigned long flags;
  1064. ep = container_of(_ep, struct r8a66597_ep, ep);
  1065. BUG_ON(!ep);
  1066. while (!list_empty(&ep->queue)) {
  1067. req = get_request_from_ep(ep);
  1068. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1069. transfer_complete(ep, req, -ECONNRESET);
  1070. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1071. }
  1072. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1073. return free_pipe_config(ep);
  1074. }
  1075. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1076. gfp_t gfp_flags)
  1077. {
  1078. struct r8a66597_request *req;
  1079. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1080. if (!req)
  1081. return NULL;
  1082. INIT_LIST_HEAD(&req->queue);
  1083. return &req->req;
  1084. }
  1085. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1086. {
  1087. struct r8a66597_request *req;
  1088. req = container_of(_req, struct r8a66597_request, req);
  1089. kfree(req);
  1090. }
  1091. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1092. gfp_t gfp_flags)
  1093. {
  1094. struct r8a66597_ep *ep;
  1095. struct r8a66597_request *req;
  1096. unsigned long flags;
  1097. int request = 0;
  1098. ep = container_of(_ep, struct r8a66597_ep, ep);
  1099. req = container_of(_req, struct r8a66597_request, req);
  1100. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1101. return -ESHUTDOWN;
  1102. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1103. if (list_empty(&ep->queue))
  1104. request = 1;
  1105. list_add_tail(&req->queue, &ep->queue);
  1106. req->req.actual = 0;
  1107. req->req.status = -EINPROGRESS;
  1108. if (ep->desc == NULL) /* control */
  1109. start_ep0(ep, req);
  1110. else {
  1111. if (request && !ep->busy)
  1112. start_packet(ep, req);
  1113. }
  1114. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1115. return 0;
  1116. }
  1117. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1118. {
  1119. struct r8a66597_ep *ep;
  1120. struct r8a66597_request *req;
  1121. unsigned long flags;
  1122. ep = container_of(_ep, struct r8a66597_ep, ep);
  1123. req = container_of(_req, struct r8a66597_request, req);
  1124. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1125. if (!list_empty(&ep->queue))
  1126. transfer_complete(ep, req, -ECONNRESET);
  1127. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1128. return 0;
  1129. }
  1130. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1131. {
  1132. struct r8a66597_ep *ep;
  1133. struct r8a66597_request *req;
  1134. unsigned long flags;
  1135. int ret = 0;
  1136. ep = container_of(_ep, struct r8a66597_ep, ep);
  1137. req = get_request_from_ep(ep);
  1138. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1139. if (!list_empty(&ep->queue)) {
  1140. ret = -EAGAIN;
  1141. goto out;
  1142. }
  1143. if (value) {
  1144. ep->busy = 1;
  1145. pipe_stall(ep->r8a66597, ep->pipenum);
  1146. } else {
  1147. ep->busy = 0;
  1148. ep->wedge = 0;
  1149. pipe_stop(ep->r8a66597, ep->pipenum);
  1150. }
  1151. out:
  1152. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1153. return ret;
  1154. }
  1155. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1156. {
  1157. struct r8a66597_ep *ep;
  1158. unsigned long flags;
  1159. ep = container_of(_ep, struct r8a66597_ep, ep);
  1160. if (!ep || !ep->desc)
  1161. return -EINVAL;
  1162. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1163. ep->wedge = 1;
  1164. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1165. return usb_ep_set_halt(_ep);
  1166. }
  1167. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1168. {
  1169. struct r8a66597_ep *ep;
  1170. unsigned long flags;
  1171. ep = container_of(_ep, struct r8a66597_ep, ep);
  1172. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1173. if (list_empty(&ep->queue) && !ep->busy) {
  1174. pipe_stop(ep->r8a66597, ep->pipenum);
  1175. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1176. }
  1177. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1178. }
  1179. static struct usb_ep_ops r8a66597_ep_ops = {
  1180. .enable = r8a66597_enable,
  1181. .disable = r8a66597_disable,
  1182. .alloc_request = r8a66597_alloc_request,
  1183. .free_request = r8a66597_free_request,
  1184. .queue = r8a66597_queue,
  1185. .dequeue = r8a66597_dequeue,
  1186. .set_halt = r8a66597_set_halt,
  1187. .set_wedge = r8a66597_set_wedge,
  1188. .fifo_flush = r8a66597_fifo_flush,
  1189. };
  1190. /*-------------------------------------------------------------------------*/
  1191. static struct r8a66597 *the_controller;
  1192. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  1193. int (*bind)(struct usb_gadget *))
  1194. {
  1195. struct r8a66597 *r8a66597 = the_controller;
  1196. int retval;
  1197. if (!driver
  1198. || driver->speed != USB_SPEED_HIGH
  1199. || !bind
  1200. || !driver->setup)
  1201. return -EINVAL;
  1202. if (!r8a66597)
  1203. return -ENODEV;
  1204. if (r8a66597->driver)
  1205. return -EBUSY;
  1206. /* hook up the driver */
  1207. driver->driver.bus = NULL;
  1208. r8a66597->driver = driver;
  1209. r8a66597->gadget.dev.driver = &driver->driver;
  1210. retval = device_add(&r8a66597->gadget.dev);
  1211. if (retval) {
  1212. printk(KERN_ERR "device_add error (%d)\n", retval);
  1213. goto error;
  1214. }
  1215. retval = bind(&r8a66597->gadget);
  1216. if (retval) {
  1217. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1218. device_del(&r8a66597->gadget.dev);
  1219. goto error;
  1220. }
  1221. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1222. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1223. r8a66597_start_xclock(r8a66597);
  1224. /* start vbus sampling */
  1225. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1226. INTSTS0) & VBSTS;
  1227. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1228. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1229. }
  1230. return 0;
  1231. error:
  1232. r8a66597->driver = NULL;
  1233. r8a66597->gadget.dev.driver = NULL;
  1234. return retval;
  1235. }
  1236. EXPORT_SYMBOL(usb_gadget_probe_driver);
  1237. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1238. {
  1239. struct r8a66597 *r8a66597 = the_controller;
  1240. unsigned long flags;
  1241. if (driver != r8a66597->driver || !driver->unbind)
  1242. return -EINVAL;
  1243. spin_lock_irqsave(&r8a66597->lock, flags);
  1244. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1245. r8a66597_usb_disconnect(r8a66597);
  1246. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1247. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1248. driver->unbind(&r8a66597->gadget);
  1249. init_controller(r8a66597);
  1250. disable_controller(r8a66597);
  1251. device_del(&r8a66597->gadget.dev);
  1252. r8a66597->driver = NULL;
  1253. return 0;
  1254. }
  1255. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1256. /*-------------------------------------------------------------------------*/
  1257. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1258. {
  1259. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1260. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1261. }
  1262. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1263. .get_frame = r8a66597_get_frame,
  1264. };
  1265. static int __exit r8a66597_remove(struct platform_device *pdev)
  1266. {
  1267. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1268. del_timer_sync(&r8a66597->timer);
  1269. iounmap(r8a66597->reg);
  1270. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1271. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1272. #ifdef CONFIG_HAVE_CLK
  1273. if (r8a66597->pdata->on_chip) {
  1274. clk_disable(r8a66597->clk);
  1275. clk_put(r8a66597->clk);
  1276. }
  1277. #endif
  1278. kfree(r8a66597);
  1279. return 0;
  1280. }
  1281. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1282. {
  1283. }
  1284. static int __init r8a66597_probe(struct platform_device *pdev)
  1285. {
  1286. #ifdef CONFIG_HAVE_CLK
  1287. char clk_name[8];
  1288. #endif
  1289. struct resource *res, *ires;
  1290. int irq;
  1291. void __iomem *reg = NULL;
  1292. struct r8a66597 *r8a66597 = NULL;
  1293. int ret = 0;
  1294. int i;
  1295. unsigned long irq_trigger;
  1296. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1297. if (!res) {
  1298. ret = -ENODEV;
  1299. printk(KERN_ERR "platform_get_resource error.\n");
  1300. goto clean_up;
  1301. }
  1302. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1303. irq = ires->start;
  1304. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1305. if (irq < 0) {
  1306. ret = -ENODEV;
  1307. printk(KERN_ERR "platform_get_irq error.\n");
  1308. goto clean_up;
  1309. }
  1310. reg = ioremap(res->start, resource_size(res));
  1311. if (reg == NULL) {
  1312. ret = -ENOMEM;
  1313. printk(KERN_ERR "ioremap error.\n");
  1314. goto clean_up;
  1315. }
  1316. /* initialize ucd */
  1317. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1318. if (r8a66597 == NULL) {
  1319. ret = -ENOMEM;
  1320. printk(KERN_ERR "kzalloc error\n");
  1321. goto clean_up;
  1322. }
  1323. spin_lock_init(&r8a66597->lock);
  1324. dev_set_drvdata(&pdev->dev, r8a66597);
  1325. r8a66597->pdata = pdev->dev.platform_data;
  1326. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1327. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1328. device_initialize(&r8a66597->gadget.dev);
  1329. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1330. r8a66597->gadget.is_dualspeed = 1;
  1331. r8a66597->gadget.dev.parent = &pdev->dev;
  1332. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1333. r8a66597->gadget.dev.release = pdev->dev.release;
  1334. r8a66597->gadget.name = udc_name;
  1335. init_timer(&r8a66597->timer);
  1336. r8a66597->timer.function = r8a66597_timer;
  1337. r8a66597->timer.data = (unsigned long)r8a66597;
  1338. r8a66597->reg = reg;
  1339. #ifdef CONFIG_HAVE_CLK
  1340. if (r8a66597->pdata->on_chip) {
  1341. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1342. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1343. if (IS_ERR(r8a66597->clk)) {
  1344. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1345. clk_name);
  1346. ret = PTR_ERR(r8a66597->clk);
  1347. goto clean_up;
  1348. }
  1349. clk_enable(r8a66597->clk);
  1350. }
  1351. #endif
  1352. disable_controller(r8a66597); /* make sure controller is disabled */
  1353. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1354. udc_name, r8a66597);
  1355. if (ret < 0) {
  1356. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1357. goto clean_up2;
  1358. }
  1359. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1360. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1361. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1362. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1363. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1364. if (i != 0) {
  1365. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1366. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1367. &r8a66597->gadget.ep_list);
  1368. }
  1369. ep->r8a66597 = r8a66597;
  1370. INIT_LIST_HEAD(&ep->queue);
  1371. ep->ep.name = r8a66597_ep_name[i];
  1372. ep->ep.ops = &r8a66597_ep_ops;
  1373. ep->ep.maxpacket = 512;
  1374. }
  1375. r8a66597->ep[0].ep.maxpacket = 64;
  1376. r8a66597->ep[0].pipenum = 0;
  1377. r8a66597->ep[0].fifoaddr = CFIFO;
  1378. r8a66597->ep[0].fifosel = CFIFOSEL;
  1379. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1380. r8a66597->ep[0].fifotrn = 0;
  1381. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1382. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1383. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1384. the_controller = r8a66597;
  1385. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1386. GFP_KERNEL);
  1387. if (r8a66597->ep0_req == NULL)
  1388. goto clean_up3;
  1389. r8a66597->ep0_req->complete = nop_completion;
  1390. init_controller(r8a66597);
  1391. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1392. return 0;
  1393. clean_up3:
  1394. free_irq(irq, r8a66597);
  1395. clean_up2:
  1396. #ifdef CONFIG_HAVE_CLK
  1397. if (r8a66597->pdata->on_chip) {
  1398. clk_disable(r8a66597->clk);
  1399. clk_put(r8a66597->clk);
  1400. }
  1401. #endif
  1402. clean_up:
  1403. if (r8a66597) {
  1404. if (r8a66597->ep0_req)
  1405. r8a66597_free_request(&r8a66597->ep[0].ep,
  1406. r8a66597->ep0_req);
  1407. kfree(r8a66597);
  1408. }
  1409. if (reg)
  1410. iounmap(reg);
  1411. return ret;
  1412. }
  1413. /*-------------------------------------------------------------------------*/
  1414. static struct platform_driver r8a66597_driver = {
  1415. .remove = __exit_p(r8a66597_remove),
  1416. .driver = {
  1417. .name = (char *) udc_name,
  1418. },
  1419. };
  1420. static int __init r8a66597_udc_init(void)
  1421. {
  1422. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1423. }
  1424. module_init(r8a66597_udc_init);
  1425. static void __exit r8a66597_udc_cleanup(void)
  1426. {
  1427. platform_driver_unregister(&r8a66597_driver);
  1428. }
  1429. module_exit(r8a66597_udc_cleanup);
  1430. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1431. MODULE_LICENSE("GPL");
  1432. MODULE_AUTHOR("Yoshihiro Shimoda");