bfin_sport_uart.c 23 KB

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  1. /*
  2. * Blackfin On-Chip Sport Emulated UART Driver
  3. *
  4. * Copyright 2006-2009 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. /*
  11. * This driver and the hardware supported are in term of EE-191 of ADI.
  12. * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
  13. * This application note describe how to implement a UART on a Sharc DSP,
  14. * but this driver is implemented on Blackfin Processor.
  15. * Transmit Frame Sync is not used by this driver to transfer data out.
  16. */
  17. /* #define DEBUG */
  18. #define DRV_NAME "bfin-sport-uart"
  19. #define DEVICE_NAME "ttySS"
  20. #define pr_fmt(fmt) DRV_NAME ": " fmt
  21. #include <linux/module.h>
  22. #include <linux/ioport.h>
  23. #include <linux/io.h>
  24. #include <linux/init.h>
  25. #include <linux/console.h>
  26. #include <linux/sysrq.h>
  27. #include <linux/slab.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/tty.h>
  30. #include <linux/tty_flip.h>
  31. #include <linux/serial_core.h>
  32. #include <asm/bfin_sport.h>
  33. #include <asm/delay.h>
  34. #include <asm/portmux.h>
  35. #include "bfin_sport_uart.h"
  36. struct sport_uart_port {
  37. struct uart_port port;
  38. int err_irq;
  39. unsigned short csize;
  40. unsigned short rxmask;
  41. unsigned short txmask1;
  42. unsigned short txmask2;
  43. unsigned char stopb;
  44. /* unsigned char parib; */
  45. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  46. int cts_pin;
  47. int rts_pin;
  48. #endif
  49. };
  50. static int sport_uart_tx_chars(struct sport_uart_port *up);
  51. static void sport_stop_tx(struct uart_port *port);
  52. static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
  53. {
  54. pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
  55. up->txmask1, up->txmask2);
  56. /* Place Start and Stop bits */
  57. __asm__ __volatile__ (
  58. "%[val] <<= 1;"
  59. "%[val] = %[val] & %[mask1];"
  60. "%[val] = %[val] | %[mask2];"
  61. : [val]"+d"(value)
  62. : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
  63. : "ASTAT"
  64. );
  65. pr_debug("%s value:%x\n", __func__, value);
  66. SPORT_PUT_TX(up, value);
  67. }
  68. static inline unsigned char rx_one_byte(struct sport_uart_port *up)
  69. {
  70. unsigned int value;
  71. unsigned char extract;
  72. u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
  73. if ((up->csize + up->stopb) > 7)
  74. value = SPORT_GET_RX32(up);
  75. else
  76. value = SPORT_GET_RX(up);
  77. pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
  78. up->csize, up->rxmask);
  79. /* Extract data */
  80. __asm__ __volatile__ (
  81. "%[extr] = 0;"
  82. "%[mask1] = %[rxmask];"
  83. "%[mask2] = 0x0200(Z);"
  84. "%[shift] = 0;"
  85. "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
  86. ".Lloop_s:"
  87. "%[tmp] = extract(%[val], %[mask1].L)(Z);"
  88. "%[tmp] <<= %[shift];"
  89. "%[extr] = %[extr] | %[tmp];"
  90. "%[mask1] = %[mask1] - %[mask2];"
  91. ".Lloop_e:"
  92. "%[shift] += 1;"
  93. : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
  94. [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
  95. : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
  96. : "ASTAT", "LB0", "LC0", "LT0"
  97. );
  98. pr_debug(" extract:%x\n", extract);
  99. return extract;
  100. }
  101. static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
  102. {
  103. int tclkdiv, rclkdiv;
  104. unsigned int sclk = get_sclk();
  105. /* Set TCR1 and TCR2, TFSR is not enabled for uart */
  106. SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
  107. SPORT_PUT_TCR2(up, size + 1);
  108. pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
  109. /* Set RCR1 and RCR2 */
  110. SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
  111. SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
  112. pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
  113. tclkdiv = sclk / (2 * baud_rate) - 1;
  114. /* The actual uart baud rate of devices vary between +/-2%. The sport
  115. * RX sample rate should be faster than the double of the worst case,
  116. * otherwise, wrong data are received. So, set sport RX clock to be
  117. * 3% faster.
  118. */
  119. rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
  120. SPORT_PUT_TCLKDIV(up, tclkdiv);
  121. SPORT_PUT_RCLKDIV(up, rclkdiv);
  122. SSYNC();
  123. pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
  124. __func__, sclk, baud_rate, tclkdiv, rclkdiv);
  125. return 0;
  126. }
  127. static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
  128. {
  129. struct sport_uart_port *up = dev_id;
  130. struct tty_struct *tty = up->port.state->port.tty;
  131. unsigned int ch;
  132. spin_lock(&up->port.lock);
  133. while (SPORT_GET_STAT(up) & RXNE) {
  134. ch = rx_one_byte(up);
  135. up->port.icount.rx++;
  136. if (!uart_handle_sysrq_char(&up->port, ch))
  137. tty_insert_flip_char(tty, ch, TTY_NORMAL);
  138. }
  139. tty_flip_buffer_push(tty);
  140. spin_unlock(&up->port.lock);
  141. return IRQ_HANDLED;
  142. }
  143. static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
  144. {
  145. struct sport_uart_port *up = dev_id;
  146. spin_lock(&up->port.lock);
  147. sport_uart_tx_chars(up);
  148. spin_unlock(&up->port.lock);
  149. return IRQ_HANDLED;
  150. }
  151. static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
  152. {
  153. struct sport_uart_port *up = dev_id;
  154. struct tty_struct *tty = up->port.state->port.tty;
  155. unsigned int stat = SPORT_GET_STAT(up);
  156. spin_lock(&up->port.lock);
  157. /* Overflow in RX FIFO */
  158. if (stat & ROVF) {
  159. up->port.icount.overrun++;
  160. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  161. SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
  162. }
  163. /* These should not happen */
  164. if (stat & (TOVF | TUVF | RUVF)) {
  165. pr_err("SPORT Error:%s %s %s\n",
  166. (stat & TOVF) ? "TX overflow" : "",
  167. (stat & TUVF) ? "TX underflow" : "",
  168. (stat & RUVF) ? "RX underflow" : "");
  169. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  170. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
  171. }
  172. SSYNC();
  173. spin_unlock(&up->port.lock);
  174. return IRQ_HANDLED;
  175. }
  176. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  177. static unsigned int sport_get_mctrl(struct uart_port *port)
  178. {
  179. struct sport_uart_port *up = (struct sport_uart_port *)port;
  180. if (up->cts_pin < 0)
  181. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  182. /* CTS PIN is negative assertive. */
  183. if (SPORT_UART_GET_CTS(up))
  184. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  185. else
  186. return TIOCM_DSR | TIOCM_CAR;
  187. }
  188. static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
  189. {
  190. struct sport_uart_port *up = (struct sport_uart_port *)port;
  191. if (up->rts_pin < 0)
  192. return;
  193. /* RTS PIN is negative assertive. */
  194. if (mctrl & TIOCM_RTS)
  195. SPORT_UART_ENABLE_RTS(up);
  196. else
  197. SPORT_UART_DISABLE_RTS(up);
  198. }
  199. /*
  200. * Handle any change of modem status signal.
  201. */
  202. static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
  203. {
  204. struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
  205. unsigned int status;
  206. status = sport_get_mctrl(&up->port);
  207. uart_handle_cts_change(&up->port, status & TIOCM_CTS);
  208. return IRQ_HANDLED;
  209. }
  210. #else
  211. static unsigned int sport_get_mctrl(struct uart_port *port)
  212. {
  213. pr_debug("%s enter\n", __func__);
  214. return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
  215. }
  216. static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
  217. {
  218. pr_debug("%s enter\n", __func__);
  219. }
  220. #endif
  221. /* Reqeust IRQ, Setup clock */
  222. static int sport_startup(struct uart_port *port)
  223. {
  224. struct sport_uart_port *up = (struct sport_uart_port *)port;
  225. int ret;
  226. pr_debug("%s enter\n", __func__);
  227. ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
  228. "SPORT_UART_RX", up);
  229. if (ret) {
  230. dev_err(port->dev, "unable to request SPORT RX interrupt\n");
  231. return ret;
  232. }
  233. ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
  234. "SPORT_UART_TX", up);
  235. if (ret) {
  236. dev_err(port->dev, "unable to request SPORT TX interrupt\n");
  237. goto fail1;
  238. }
  239. ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
  240. "SPORT_UART_STATUS", up);
  241. if (ret) {
  242. dev_err(port->dev, "unable to request SPORT status interrupt\n");
  243. goto fail2;
  244. }
  245. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  246. if (up->cts_pin >= 0) {
  247. if (request_irq(gpio_to_irq(up->cts_pin),
  248. sport_mctrl_cts_int,
  249. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
  250. IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
  251. up->cts_pin = -1;
  252. dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
  253. }
  254. }
  255. if (up->rts_pin >= 0)
  256. gpio_direction_output(up->rts_pin, 0);
  257. #endif
  258. return 0;
  259. fail2:
  260. free_irq(up->port.irq+1, up);
  261. fail1:
  262. free_irq(up->port.irq, up);
  263. return ret;
  264. }
  265. /*
  266. * sport_uart_tx_chars
  267. *
  268. * ret 1 means need to enable sport.
  269. * ret 0 means do nothing.
  270. */
  271. static int sport_uart_tx_chars(struct sport_uart_port *up)
  272. {
  273. struct circ_buf *xmit = &up->port.state->xmit;
  274. if (SPORT_GET_STAT(up) & TXF)
  275. return 0;
  276. if (up->port.x_char) {
  277. tx_one_byte(up, up->port.x_char);
  278. up->port.icount.tx++;
  279. up->port.x_char = 0;
  280. return 1;
  281. }
  282. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  283. /* The waiting loop to stop SPORT TX from TX interrupt is
  284. * too long. This may block SPORT RX interrupts and cause
  285. * RX FIFO overflow. So, do stop sport TX only after the last
  286. * char in TX FIFO is moved into the shift register.
  287. */
  288. if (SPORT_GET_STAT(up) & TXHRE)
  289. sport_stop_tx(&up->port);
  290. return 0;
  291. }
  292. while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
  293. tx_one_byte(up, xmit->buf[xmit->tail]);
  294. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
  295. up->port.icount.tx++;
  296. }
  297. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  298. uart_write_wakeup(&up->port);
  299. return 1;
  300. }
  301. static unsigned int sport_tx_empty(struct uart_port *port)
  302. {
  303. struct sport_uart_port *up = (struct sport_uart_port *)port;
  304. unsigned int stat;
  305. stat = SPORT_GET_STAT(up);
  306. pr_debug("%s stat:%04x\n", __func__, stat);
  307. if (stat & TXHRE) {
  308. return TIOCSER_TEMT;
  309. } else
  310. return 0;
  311. }
  312. static void sport_stop_tx(struct uart_port *port)
  313. {
  314. struct sport_uart_port *up = (struct sport_uart_port *)port;
  315. pr_debug("%s enter\n", __func__);
  316. if (!(SPORT_GET_TCR1(up) & TSPEN))
  317. return;
  318. /* Although the hold register is empty, last byte is still in shift
  319. * register and not sent out yet. So, put a dummy data into TX FIFO.
  320. * Then, sport tx stops when last byte is shift out and the dummy
  321. * data is moved into the shift register.
  322. */
  323. SPORT_PUT_TX(up, 0xffff);
  324. while (!(SPORT_GET_STAT(up) & TXHRE))
  325. cpu_relax();
  326. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  327. SSYNC();
  328. return;
  329. }
  330. static void sport_start_tx(struct uart_port *port)
  331. {
  332. struct sport_uart_port *up = (struct sport_uart_port *)port;
  333. pr_debug("%s enter\n", __func__);
  334. /* Write data into SPORT FIFO before enable SPROT to transmit */
  335. if (sport_uart_tx_chars(up)) {
  336. /* Enable transmit, then an interrupt will generated */
  337. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  338. SSYNC();
  339. }
  340. pr_debug("%s exit\n", __func__);
  341. }
  342. static void sport_stop_rx(struct uart_port *port)
  343. {
  344. struct sport_uart_port *up = (struct sport_uart_port *)port;
  345. pr_debug("%s enter\n", __func__);
  346. /* Disable sport to stop rx */
  347. SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
  348. SSYNC();
  349. }
  350. static void sport_enable_ms(struct uart_port *port)
  351. {
  352. pr_debug("%s enter\n", __func__);
  353. }
  354. static void sport_break_ctl(struct uart_port *port, int break_state)
  355. {
  356. pr_debug("%s enter\n", __func__);
  357. }
  358. static void sport_shutdown(struct uart_port *port)
  359. {
  360. struct sport_uart_port *up = (struct sport_uart_port *)port;
  361. dev_dbg(port->dev, "%s enter\n", __func__);
  362. /* Disable sport */
  363. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  364. SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
  365. SSYNC();
  366. free_irq(up->port.irq, up);
  367. free_irq(up->port.irq+1, up);
  368. free_irq(up->err_irq, up);
  369. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  370. if (up->cts_pin >= 0)
  371. free_irq(gpio_to_irq(up->cts_pin), up);
  372. #endif
  373. }
  374. static const char *sport_type(struct uart_port *port)
  375. {
  376. struct sport_uart_port *up = (struct sport_uart_port *)port;
  377. pr_debug("%s enter\n", __func__);
  378. return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
  379. }
  380. static void sport_release_port(struct uart_port *port)
  381. {
  382. pr_debug("%s enter\n", __func__);
  383. }
  384. static int sport_request_port(struct uart_port *port)
  385. {
  386. pr_debug("%s enter\n", __func__);
  387. return 0;
  388. }
  389. static void sport_config_port(struct uart_port *port, int flags)
  390. {
  391. struct sport_uart_port *up = (struct sport_uart_port *)port;
  392. pr_debug("%s enter\n", __func__);
  393. up->port.type = PORT_BFIN_SPORT;
  394. }
  395. static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
  396. {
  397. pr_debug("%s enter\n", __func__);
  398. return 0;
  399. }
  400. static void sport_set_termios(struct uart_port *port,
  401. struct ktermios *termios, struct ktermios *old)
  402. {
  403. struct sport_uart_port *up = (struct sport_uart_port *)port;
  404. unsigned long flags;
  405. int i;
  406. pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
  407. switch (termios->c_cflag & CSIZE) {
  408. case CS8:
  409. up->csize = 8;
  410. break;
  411. case CS7:
  412. up->csize = 7;
  413. break;
  414. case CS6:
  415. up->csize = 6;
  416. break;
  417. case CS5:
  418. up->csize = 5;
  419. break;
  420. default:
  421. pr_warning("requested word length not supported\n");
  422. }
  423. if (termios->c_cflag & CSTOPB) {
  424. up->stopb = 1;
  425. }
  426. if (termios->c_cflag & PARENB) {
  427. pr_warning("PAREN bits is not supported yet\n");
  428. /* up->parib = 1; */
  429. }
  430. spin_lock_irqsave(&up->port.lock, flags);
  431. port->read_status_mask = 0;
  432. /*
  433. * Characters to ignore
  434. */
  435. port->ignore_status_mask = 0;
  436. /* RX extract mask */
  437. up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
  438. /* TX masks, 8 bit data and 1 bit stop for example:
  439. * mask1 = b#0111111110
  440. * mask2 = b#1000000000
  441. */
  442. for (i = 0, up->txmask1 = 0; i < up->csize; i++)
  443. up->txmask1 |= (1<<i);
  444. up->txmask2 = (1<<i);
  445. if (up->stopb) {
  446. ++i;
  447. up->txmask2 |= (1<<i);
  448. }
  449. up->txmask1 <<= 1;
  450. up->txmask2 <<= 1;
  451. /* uart baud rate */
  452. port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
  453. /* Disable UART */
  454. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  455. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
  456. sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
  457. /* driver TX line high after config, one dummy data is
  458. * necessary to stop sport after shift one byte
  459. */
  460. SPORT_PUT_TX(up, 0xffff);
  461. SPORT_PUT_TX(up, 0xffff);
  462. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  463. SSYNC();
  464. while (!(SPORT_GET_STAT(up) & TXHRE))
  465. cpu_relax();
  466. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  467. SSYNC();
  468. /* Port speed changed, update the per-port timeout. */
  469. uart_update_timeout(port, termios->c_cflag, port->uartclk);
  470. /* Enable sport rx */
  471. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
  472. SSYNC();
  473. spin_unlock_irqrestore(&up->port.lock, flags);
  474. }
  475. struct uart_ops sport_uart_ops = {
  476. .tx_empty = sport_tx_empty,
  477. .set_mctrl = sport_set_mctrl,
  478. .get_mctrl = sport_get_mctrl,
  479. .stop_tx = sport_stop_tx,
  480. .start_tx = sport_start_tx,
  481. .stop_rx = sport_stop_rx,
  482. .enable_ms = sport_enable_ms,
  483. .break_ctl = sport_break_ctl,
  484. .startup = sport_startup,
  485. .shutdown = sport_shutdown,
  486. .set_termios = sport_set_termios,
  487. .type = sport_type,
  488. .release_port = sport_release_port,
  489. .request_port = sport_request_port,
  490. .config_port = sport_config_port,
  491. .verify_port = sport_verify_port,
  492. };
  493. #define BFIN_SPORT_UART_MAX_PORTS 4
  494. static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
  495. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  496. #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
  497. static int __init
  498. sport_uart_console_setup(struct console *co, char *options)
  499. {
  500. struct sport_uart_port *up;
  501. int baud = 57600;
  502. int bits = 8;
  503. int parity = 'n';
  504. # ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  505. int flow = 'r';
  506. # else
  507. int flow = 'n';
  508. # endif
  509. /* Check whether an invalid uart number has been specified */
  510. if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
  511. return -ENODEV;
  512. up = bfin_sport_uart_ports[co->index];
  513. if (!up)
  514. return -ENODEV;
  515. if (options)
  516. uart_parse_options(options, &baud, &parity, &bits, &flow);
  517. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  518. }
  519. static void sport_uart_console_putchar(struct uart_port *port, int ch)
  520. {
  521. struct sport_uart_port *up = (struct sport_uart_port *)port;
  522. while (SPORT_GET_STAT(up) & TXF)
  523. barrier();
  524. tx_one_byte(up, ch);
  525. }
  526. /*
  527. * Interrupts are disabled on entering
  528. */
  529. static void
  530. sport_uart_console_write(struct console *co, const char *s, unsigned int count)
  531. {
  532. struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
  533. unsigned long flags;
  534. spin_lock_irqsave(&up->port.lock, flags);
  535. if (SPORT_GET_TCR1(up) & TSPEN)
  536. uart_console_write(&up->port, s, count, sport_uart_console_putchar);
  537. else {
  538. /* dummy data to start sport */
  539. while (SPORT_GET_STAT(up) & TXF)
  540. barrier();
  541. SPORT_PUT_TX(up, 0xffff);
  542. /* Enable transmit, then an interrupt will generated */
  543. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  544. SSYNC();
  545. uart_console_write(&up->port, s, count, sport_uart_console_putchar);
  546. /* Although the hold register is empty, last byte is still in shift
  547. * register and not sent out yet. So, put a dummy data into TX FIFO.
  548. * Then, sport tx stops when last byte is shift out and the dummy
  549. * data is moved into the shift register.
  550. */
  551. while (SPORT_GET_STAT(up) & TXF)
  552. barrier();
  553. SPORT_PUT_TX(up, 0xffff);
  554. while (!(SPORT_GET_STAT(up) & TXHRE))
  555. barrier();
  556. /* Stop sport tx transfer */
  557. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  558. SSYNC();
  559. }
  560. spin_unlock_irqrestore(&up->port.lock, flags);
  561. }
  562. static struct uart_driver sport_uart_reg;
  563. static struct console sport_uart_console = {
  564. .name = DEVICE_NAME,
  565. .write = sport_uart_console_write,
  566. .device = uart_console_device,
  567. .setup = sport_uart_console_setup,
  568. .flags = CON_PRINTBUFFER,
  569. .index = -1,
  570. .data = &sport_uart_reg,
  571. };
  572. #define SPORT_UART_CONSOLE (&sport_uart_console)
  573. #else
  574. #define SPORT_UART_CONSOLE NULL
  575. #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
  576. static struct uart_driver sport_uart_reg = {
  577. .owner = THIS_MODULE,
  578. .driver_name = DRV_NAME,
  579. .dev_name = DEVICE_NAME,
  580. .major = 204,
  581. .minor = 84,
  582. .nr = BFIN_SPORT_UART_MAX_PORTS,
  583. .cons = SPORT_UART_CONSOLE,
  584. };
  585. #ifdef CONFIG_PM
  586. static int sport_uart_suspend(struct device *dev)
  587. {
  588. struct sport_uart_port *sport = dev_get_drvdata(dev);
  589. dev_dbg(dev, "%s enter\n", __func__);
  590. if (sport)
  591. uart_suspend_port(&sport_uart_reg, &sport->port);
  592. return 0;
  593. }
  594. static int sport_uart_resume(struct device *dev)
  595. {
  596. struct sport_uart_port *sport = dev_get_drvdata(dev);
  597. dev_dbg(dev, "%s enter\n", __func__);
  598. if (sport)
  599. uart_resume_port(&sport_uart_reg, &sport->port);
  600. return 0;
  601. }
  602. static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
  603. .suspend = sport_uart_suspend,
  604. .resume = sport_uart_resume,
  605. };
  606. #endif
  607. static int __devinit sport_uart_probe(struct platform_device *pdev)
  608. {
  609. struct resource *res;
  610. struct sport_uart_port *sport;
  611. int ret = 0;
  612. dev_dbg(&pdev->dev, "%s enter\n", __func__);
  613. if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
  614. dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
  615. return -ENOENT;
  616. }
  617. if (bfin_sport_uart_ports[pdev->id] == NULL) {
  618. bfin_sport_uart_ports[pdev->id] =
  619. kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
  620. sport = bfin_sport_uart_ports[pdev->id];
  621. if (!sport) {
  622. dev_err(&pdev->dev,
  623. "Fail to malloc sport_uart_port\n");
  624. return -ENOMEM;
  625. }
  626. ret = peripheral_request_list(
  627. (unsigned short *)pdev->dev.platform_data, DRV_NAME);
  628. if (ret) {
  629. dev_err(&pdev->dev,
  630. "Fail to request SPORT peripherals\n");
  631. goto out_error_free_mem;
  632. }
  633. spin_lock_init(&sport->port.lock);
  634. sport->port.fifosize = SPORT_TX_FIFO_SIZE,
  635. sport->port.ops = &sport_uart_ops;
  636. sport->port.line = pdev->id;
  637. sport->port.iotype = UPIO_MEM;
  638. sport->port.flags = UPF_BOOT_AUTOCONF;
  639. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  640. if (res == NULL) {
  641. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  642. ret = -ENOENT;
  643. goto out_error_free_peripherals;
  644. }
  645. sport->port.membase = ioremap(res->start, resource_size(res));
  646. if (!sport->port.membase) {
  647. dev_err(&pdev->dev, "Cannot map sport IO\n");
  648. ret = -ENXIO;
  649. goto out_error_free_peripherals;
  650. }
  651. sport->port.mapbase = res->start;
  652. sport->port.irq = platform_get_irq(pdev, 0);
  653. if ((int)sport->port.irq < 0) {
  654. dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
  655. ret = -ENOENT;
  656. goto out_error_unmap;
  657. }
  658. sport->err_irq = platform_get_irq(pdev, 1);
  659. if (sport->err_irq < 0) {
  660. dev_err(&pdev->dev, "No sport status IRQ specified\n");
  661. ret = -ENOENT;
  662. goto out_error_unmap;
  663. }
  664. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  665. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  666. if (res == NULL)
  667. sport->cts_pin = -1;
  668. else
  669. sport->cts_pin = res->start;
  670. res = platform_get_resource(pdev, IORESOURCE_IO, 1);
  671. if (res == NULL)
  672. sport->rts_pin = -1;
  673. else
  674. sport->rts_pin = res->start;
  675. if (sport->rts_pin >= 0)
  676. gpio_request(sport->rts_pin, DRV_NAME);
  677. #endif
  678. }
  679. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  680. if (!is_early_platform_device(pdev)) {
  681. #endif
  682. sport = bfin_sport_uart_ports[pdev->id];
  683. sport->port.dev = &pdev->dev;
  684. dev_set_drvdata(&pdev->dev, sport);
  685. ret = uart_add_one_port(&sport_uart_reg, &sport->port);
  686. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  687. }
  688. #endif
  689. if (!ret)
  690. return 0;
  691. if (sport) {
  692. out_error_unmap:
  693. iounmap(sport->port.membase);
  694. out_error_free_peripherals:
  695. peripheral_free_list(
  696. (unsigned short *)pdev->dev.platform_data);
  697. out_error_free_mem:
  698. kfree(sport);
  699. bfin_sport_uart_ports[pdev->id] = NULL;
  700. }
  701. return ret;
  702. }
  703. static int __devexit sport_uart_remove(struct platform_device *pdev)
  704. {
  705. struct sport_uart_port *sport = platform_get_drvdata(pdev);
  706. dev_dbg(&pdev->dev, "%s enter\n", __func__);
  707. dev_set_drvdata(&pdev->dev, NULL);
  708. if (sport) {
  709. uart_remove_one_port(&sport_uart_reg, &sport->port);
  710. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  711. if (sport->rts_pin >= 0)
  712. gpio_free(sport->rts_pin);
  713. #endif
  714. iounmap(sport->port.membase);
  715. peripheral_free_list(
  716. (unsigned short *)pdev->dev.platform_data);
  717. kfree(sport);
  718. bfin_sport_uart_ports[pdev->id] = NULL;
  719. }
  720. return 0;
  721. }
  722. static struct platform_driver sport_uart_driver = {
  723. .probe = sport_uart_probe,
  724. .remove = __devexit_p(sport_uart_remove),
  725. .driver = {
  726. .name = DRV_NAME,
  727. #ifdef CONFIG_PM
  728. .pm = &bfin_sport_uart_dev_pm_ops,
  729. #endif
  730. },
  731. };
  732. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  733. static __initdata struct early_platform_driver early_sport_uart_driver = {
  734. .class_str = CLASS_BFIN_SPORT_CONSOLE,
  735. .pdrv = &sport_uart_driver,
  736. .requested_id = EARLY_PLATFORM_ID_UNSET,
  737. };
  738. static int __init sport_uart_rs_console_init(void)
  739. {
  740. early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
  741. early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
  742. BFIN_SPORT_UART_MAX_PORTS, 0);
  743. register_console(&sport_uart_console);
  744. return 0;
  745. }
  746. console_initcall(sport_uart_rs_console_init);
  747. #endif
  748. static int __init sport_uart_init(void)
  749. {
  750. int ret;
  751. pr_info("Blackfin uart over sport driver\n");
  752. ret = uart_register_driver(&sport_uart_reg);
  753. if (ret) {
  754. pr_err("failed to register %s:%d\n",
  755. sport_uart_reg.driver_name, ret);
  756. return ret;
  757. }
  758. ret = platform_driver_register(&sport_uart_driver);
  759. if (ret) {
  760. pr_err("failed to register sport uart driver:%d\n", ret);
  761. uart_unregister_driver(&sport_uart_reg);
  762. }
  763. return ret;
  764. }
  765. module_init(sport_uart_init);
  766. static void __exit sport_uart_exit(void)
  767. {
  768. platform_driver_unregister(&sport_uart_driver);
  769. uart_unregister_driver(&sport_uart_reg);
  770. }
  771. module_exit(sport_uart_exit);
  772. MODULE_AUTHOR("Sonic Zhang, Roy Huang");
  773. MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
  774. MODULE_LICENSE("GPL");