ethernet-rx.c 15 KB

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  1. /**********************************************************************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: support@caviumnetworks.com
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2010 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. **********************************************************************/
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/cache.h>
  30. #include <linux/cpumask.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/init.h>
  33. #include <linux/etherdevice.h>
  34. #include <linux/ip.h>
  35. #include <linux/string.h>
  36. #include <linux/prefetch.h>
  37. #include <linux/smp.h>
  38. #include <net/dst.h>
  39. #ifdef CONFIG_XFRM
  40. #include <linux/xfrm.h>
  41. #include <net/xfrm.h>
  42. #endif /* CONFIG_XFRM */
  43. #include <asm/atomic.h>
  44. #include <asm/octeon/octeon.h>
  45. #include "ethernet-defines.h"
  46. #include "ethernet-mem.h"
  47. #include "ethernet-rx.h"
  48. #include "octeon-ethernet.h"
  49. #include "ethernet-util.h"
  50. #include "cvmx-helper.h"
  51. #include "cvmx-wqe.h"
  52. #include "cvmx-fau.h"
  53. #include "cvmx-pow.h"
  54. #include "cvmx-pip.h"
  55. #include "cvmx-scratch.h"
  56. #include "cvmx-gmxx-defs.h"
  57. struct cvm_napi_wrapper {
  58. struct napi_struct napi;
  59. } ____cacheline_aligned_in_smp;
  60. static struct cvm_napi_wrapper cvm_oct_napi[NR_CPUS] __cacheline_aligned_in_smp;
  61. struct cvm_oct_core_state {
  62. int baseline_cores;
  63. /*
  64. * The number of additional cores that could be processing
  65. * input packtes.
  66. */
  67. atomic_t available_cores;
  68. cpumask_t cpu_state;
  69. } ____cacheline_aligned_in_smp;
  70. static struct cvm_oct_core_state core_state __cacheline_aligned_in_smp;
  71. static void cvm_oct_enable_napi(void *_)
  72. {
  73. int cpu = smp_processor_id();
  74. napi_schedule(&cvm_oct_napi[cpu].napi);
  75. }
  76. static void cvm_oct_enable_one_cpu(void)
  77. {
  78. int v;
  79. int cpu;
  80. /* Check to see if more CPUs are available for receive processing... */
  81. v = atomic_sub_if_positive(1, &core_state.available_cores);
  82. if (v < 0)
  83. return;
  84. /* ... if a CPU is available, Turn on NAPI polling for that CPU. */
  85. for_each_online_cpu(cpu) {
  86. if (!cpu_test_and_set(cpu, core_state.cpu_state)) {
  87. v = smp_call_function_single(cpu, cvm_oct_enable_napi,
  88. NULL, 0);
  89. if (v)
  90. panic("Can't enable NAPI.");
  91. break;
  92. }
  93. }
  94. }
  95. static void cvm_oct_no_more_work(void)
  96. {
  97. int cpu = smp_processor_id();
  98. /*
  99. * CPU zero is special. It always has the irq enabled when
  100. * waiting for incoming packets.
  101. */
  102. if (cpu == 0) {
  103. enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  104. return;
  105. }
  106. cpu_clear(cpu, core_state.cpu_state);
  107. atomic_add(1, &core_state.available_cores);
  108. }
  109. /**
  110. * cvm_oct_do_interrupt - interrupt handler.
  111. *
  112. * The interrupt occurs whenever the POW has packets in our group.
  113. *
  114. */
  115. static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
  116. {
  117. /* Disable the IRQ and start napi_poll. */
  118. disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  119. cvm_oct_enable_napi(NULL);
  120. return IRQ_HANDLED;
  121. }
  122. /**
  123. * cvm_oct_check_rcv_error - process receive errors
  124. * @work: Work queue entry pointing to the packet.
  125. *
  126. * Returns Non-zero if the packet can be dropped, zero otherwise.
  127. */
  128. static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
  129. {
  130. if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) {
  131. /*
  132. * Ignore length errors on min size packets. Some
  133. * equipment incorrectly pads packets to 64+4FCS
  134. * instead of 60+4FCS. Note these packets still get
  135. * counted as frame errors.
  136. */
  137. } else
  138. if (USE_10MBPS_PREAMBLE_WORKAROUND
  139. && ((work->word2.snoip.err_code == 5)
  140. || (work->word2.snoip.err_code == 7))) {
  141. /*
  142. * We received a packet with either an alignment error
  143. * or a FCS error. This may be signalling that we are
  144. * running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK}
  145. * off. If this is the case we need to parse the
  146. * packet to determine if we can remove a non spec
  147. * preamble and generate a correct packet.
  148. */
  149. int interface = cvmx_helper_get_interface_num(work->ipprt);
  150. int index = cvmx_helper_get_interface_index_num(work->ipprt);
  151. union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
  152. gmxx_rxx_frm_ctl.u64 =
  153. cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
  154. if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
  155. uint8_t *ptr =
  156. cvmx_phys_to_ptr(work->packet_ptr.s.addr);
  157. int i = 0;
  158. while (i < work->len - 1) {
  159. if (*ptr != 0x55)
  160. break;
  161. ptr++;
  162. i++;
  163. }
  164. if (*ptr == 0xd5) {
  165. /*
  166. DEBUGPRINT("Port %d received 0xd5 preamble\n", work->ipprt);
  167. */
  168. work->packet_ptr.s.addr += i + 1;
  169. work->len -= i + 5;
  170. } else if ((*ptr & 0xf) == 0xd) {
  171. /*
  172. DEBUGPRINT("Port %d received 0x?d preamble\n", work->ipprt);
  173. */
  174. work->packet_ptr.s.addr += i;
  175. work->len -= i + 4;
  176. for (i = 0; i < work->len; i++) {
  177. *ptr =
  178. ((*ptr & 0xf0) >> 4) |
  179. ((*(ptr + 1) & 0xf) << 4);
  180. ptr++;
  181. }
  182. } else {
  183. DEBUGPRINT("Port %d unknown preamble, packet "
  184. "dropped\n",
  185. work->ipprt);
  186. /*
  187. cvmx_helper_dump_packet(work);
  188. */
  189. cvm_oct_free_work(work);
  190. return 1;
  191. }
  192. }
  193. } else {
  194. DEBUGPRINT("Port %d receive error code %d, packet dropped\n",
  195. work->ipprt, work->word2.snoip.err_code);
  196. cvm_oct_free_work(work);
  197. return 1;
  198. }
  199. return 0;
  200. }
  201. /**
  202. * cvm_oct_napi_poll - the NAPI poll function.
  203. * @napi: The NAPI instance, or null if called from cvm_oct_poll_controller
  204. * @budget: Maximum number of packets to receive.
  205. *
  206. * Returns the number of packets processed.
  207. */
  208. static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
  209. {
  210. const int coreid = cvmx_get_core_num();
  211. uint64_t old_group_mask;
  212. uint64_t old_scratch;
  213. int rx_count = 0;
  214. int did_work_request = 0;
  215. int packet_not_copied;
  216. /* Prefetch cvm_oct_device since we know we need it soon */
  217. prefetch(cvm_oct_device);
  218. if (USE_ASYNC_IOBDMA) {
  219. /* Save scratch in case userspace is using it */
  220. CVMX_SYNCIOBDMA;
  221. old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
  222. }
  223. /* Only allow work for our group (and preserve priorities) */
  224. old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
  225. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
  226. (old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
  227. if (USE_ASYNC_IOBDMA) {
  228. cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
  229. did_work_request = 1;
  230. }
  231. while (rx_count < budget) {
  232. struct sk_buff *skb = NULL;
  233. struct sk_buff **pskb = NULL;
  234. int skb_in_hw;
  235. cvmx_wqe_t *work;
  236. if (USE_ASYNC_IOBDMA && did_work_request)
  237. work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
  238. else
  239. work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
  240. prefetch(work);
  241. did_work_request = 0;
  242. if (work == NULL) {
  243. union cvmx_pow_wq_int wq_int;
  244. wq_int.u64 = 0;
  245. wq_int.s.iq_dis = 1 << pow_receive_group;
  246. wq_int.s.wq_int = 1 << pow_receive_group;
  247. cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
  248. break;
  249. }
  250. pskb = (struct sk_buff **)(cvm_oct_get_buffer_ptr(work->packet_ptr) - sizeof(void *));
  251. prefetch(pskb);
  252. if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
  253. cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
  254. did_work_request = 1;
  255. }
  256. if (rx_count == 0) {
  257. /*
  258. * First time through, see if there is enough
  259. * work waiting to merit waking another
  260. * CPU.
  261. */
  262. union cvmx_pow_wq_int_cntx counts;
  263. int backlog;
  264. int cores_in_use = core_state.baseline_cores - atomic_read(&core_state.available_cores);
  265. counts.u64 = cvmx_read_csr(CVMX_POW_WQ_INT_CNTX(pow_receive_group));
  266. backlog = counts.s.iq_cnt + counts.s.ds_cnt;
  267. if (backlog > budget * cores_in_use && napi != NULL)
  268. cvm_oct_enable_one_cpu();
  269. }
  270. skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
  271. if (likely(skb_in_hw)) {
  272. skb = *pskb;
  273. prefetch(&skb->head);
  274. prefetch(&skb->len);
  275. }
  276. prefetch(cvm_oct_device[work->ipprt]);
  277. /* Immediately throw away all packets with receive errors */
  278. if (unlikely(work->word2.snoip.rcv_error)) {
  279. if (cvm_oct_check_rcv_error(work))
  280. continue;
  281. }
  282. /*
  283. * We can only use the zero copy path if skbuffs are
  284. * in the FPA pool and the packet fits in a single
  285. * buffer.
  286. */
  287. if (likely(skb_in_hw)) {
  288. skb->data = skb->head + work->packet_ptr.s.addr - cvmx_ptr_to_phys(skb->head);
  289. prefetch(skb->data);
  290. skb->len = work->len;
  291. skb_set_tail_pointer(skb, skb->len);
  292. packet_not_copied = 1;
  293. } else {
  294. /*
  295. * We have to copy the packet. First allocate
  296. * an skbuff for it.
  297. */
  298. skb = dev_alloc_skb(work->len);
  299. if (!skb) {
  300. DEBUGPRINT("Port %d failed to allocate skbuff, packet dropped\n",
  301. work->ipprt);
  302. cvm_oct_free_work(work);
  303. continue;
  304. }
  305. /*
  306. * Check if we've received a packet that was
  307. * entirely stored in the work entry.
  308. */
  309. if (unlikely(work->word2.s.bufs == 0)) {
  310. uint8_t *ptr = work->packet_data;
  311. if (likely(!work->word2.s.not_IP)) {
  312. /*
  313. * The beginning of the packet
  314. * moves for IP packets.
  315. */
  316. if (work->word2.s.is_v6)
  317. ptr += 2;
  318. else
  319. ptr += 6;
  320. }
  321. memcpy(skb_put(skb, work->len), ptr, work->len);
  322. /* No packet buffers to free */
  323. } else {
  324. int segments = work->word2.s.bufs;
  325. union cvmx_buf_ptr segment_ptr = work->packet_ptr;
  326. int len = work->len;
  327. while (segments--) {
  328. union cvmx_buf_ptr next_ptr =
  329. *(union cvmx_buf_ptr *)cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
  330. /*
  331. * Octeon Errata PKI-100: The segment size is
  332. * wrong. Until it is fixed, calculate the
  333. * segment size based on the packet pool
  334. * buffer size. When it is fixed, the
  335. * following line should be replaced with this
  336. * one: int segment_size =
  337. * segment_ptr.s.size;
  338. */
  339. int segment_size = CVMX_FPA_PACKET_POOL_SIZE -
  340. (segment_ptr.s.addr - (((segment_ptr.s.addr >> 7) - segment_ptr.s.back) << 7));
  341. /*
  342. * Don't copy more than what
  343. * is left in the packet.
  344. */
  345. if (segment_size > len)
  346. segment_size = len;
  347. /* Copy the data into the packet */
  348. memcpy(skb_put(skb, segment_size),
  349. cvmx_phys_to_ptr(segment_ptr.s.addr),
  350. segment_size);
  351. len -= segment_size;
  352. segment_ptr = next_ptr;
  353. }
  354. }
  355. packet_not_copied = 0;
  356. }
  357. if (likely((work->ipprt < TOTAL_NUMBER_OF_PORTS) &&
  358. cvm_oct_device[work->ipprt])) {
  359. struct net_device *dev = cvm_oct_device[work->ipprt];
  360. struct octeon_ethernet *priv = netdev_priv(dev);
  361. /*
  362. * Only accept packets for devices that are
  363. * currently up.
  364. */
  365. if (likely(dev->flags & IFF_UP)) {
  366. skb->protocol = eth_type_trans(skb, dev);
  367. skb->dev = dev;
  368. if (unlikely(work->word2.s.not_IP || work->word2.s.IP_exc || work->word2.s.L4_error))
  369. skb->ip_summed = CHECKSUM_NONE;
  370. else
  371. skb->ip_summed = CHECKSUM_UNNECESSARY;
  372. /* Increment RX stats for virtual ports */
  373. if (work->ipprt >= CVMX_PIP_NUM_INPUT_PORTS) {
  374. #ifdef CONFIG_64BIT
  375. atomic64_add(1, (atomic64_t *)&priv->stats.rx_packets);
  376. atomic64_add(skb->len, (atomic64_t *)&priv->stats.rx_bytes);
  377. #else
  378. atomic_add(1, (atomic_t *)&priv->stats.rx_packets);
  379. atomic_add(skb->len, (atomic_t *)&priv->stats.rx_bytes);
  380. #endif
  381. }
  382. netif_receive_skb(skb);
  383. rx_count++;
  384. } else {
  385. /* Drop any packet received for a device that isn't up */
  386. /*
  387. DEBUGPRINT("%s: Device not up, packet dropped\n",
  388. dev->name);
  389. */
  390. #ifdef CONFIG_64BIT
  391. atomic64_add(1, (atomic64_t *)&priv->stats.rx_dropped);
  392. #else
  393. atomic_add(1, (atomic_t *)&priv->stats.rx_dropped);
  394. #endif
  395. dev_kfree_skb_irq(skb);
  396. }
  397. } else {
  398. /*
  399. * Drop any packet received for a device that
  400. * doesn't exist.
  401. */
  402. DEBUGPRINT("Port %d not controlled by Linux, packet dropped\n",
  403. work->ipprt);
  404. dev_kfree_skb_irq(skb);
  405. }
  406. /*
  407. * Check to see if the skbuff and work share the same
  408. * packet buffer.
  409. */
  410. if (USE_SKBUFFS_IN_HW && likely(packet_not_copied)) {
  411. /*
  412. * This buffer needs to be replaced, increment
  413. * the number of buffers we need to free by
  414. * one.
  415. */
  416. cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
  417. 1);
  418. cvmx_fpa_free(work, CVMX_FPA_WQE_POOL,
  419. DONT_WRITEBACK(1));
  420. } else {
  421. cvm_oct_free_work(work);
  422. }
  423. }
  424. /* Restore the original POW group mask */
  425. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
  426. if (USE_ASYNC_IOBDMA) {
  427. /* Restore the scratch area */
  428. cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
  429. }
  430. cvm_oct_rx_refill_pool(0);
  431. if (rx_count < budget && napi != NULL) {
  432. /* No more work */
  433. napi_complete(napi);
  434. cvm_oct_no_more_work();
  435. }
  436. return rx_count;
  437. }
  438. #ifdef CONFIG_NET_POLL_CONTROLLER
  439. /**
  440. * cvm_oct_poll_controller - poll for receive packets
  441. * device.
  442. *
  443. * @dev: Device to poll. Unused
  444. */
  445. void cvm_oct_poll_controller(struct net_device *dev)
  446. {
  447. cvm_oct_napi_poll(NULL, 16);
  448. }
  449. #endif
  450. void cvm_oct_rx_initialize(void)
  451. {
  452. int i;
  453. struct net_device *dev_for_napi = NULL;
  454. union cvmx_pow_wq_int_thrx int_thr;
  455. union cvmx_pow_wq_int_pc int_pc;
  456. for (i = 0; i < TOTAL_NUMBER_OF_PORTS; i++) {
  457. if (cvm_oct_device[i]) {
  458. dev_for_napi = cvm_oct_device[i];
  459. break;
  460. }
  461. }
  462. if (NULL == dev_for_napi)
  463. panic("No net_devices were allocated.");
  464. if (max_rx_cpus > 1 && max_rx_cpus < num_online_cpus())
  465. atomic_set(&core_state.available_cores, max_rx_cpus);
  466. else
  467. atomic_set(&core_state.available_cores, num_online_cpus());
  468. core_state.baseline_cores = atomic_read(&core_state.available_cores);
  469. core_state.cpu_state = CPU_MASK_NONE;
  470. for_each_possible_cpu(i) {
  471. netif_napi_add(dev_for_napi, &cvm_oct_napi[i].napi,
  472. cvm_oct_napi_poll, rx_napi_weight);
  473. napi_enable(&cvm_oct_napi[i].napi);
  474. }
  475. /* Register an IRQ hander for to receive POW interrupts */
  476. i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
  477. cvm_oct_do_interrupt, 0, "Ethernet", cvm_oct_device);
  478. if (i)
  479. panic("Could not acquire Ethernet IRQ %d\n",
  480. OCTEON_IRQ_WORKQ0 + pow_receive_group);
  481. disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  482. int_thr.u64 = 0;
  483. int_thr.s.tc_en = 1;
  484. int_thr.s.tc_thr = 1;
  485. /* Enable POW interrupt when our port has at least one packet */
  486. cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), int_thr.u64);
  487. int_pc.u64 = 0;
  488. int_pc.s.pc_thr = 5;
  489. cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
  490. /* Scheduld NAPI now. This will indirectly enable interrupts. */
  491. cvm_oct_enable_one_cpu();
  492. }
  493. void cvm_oct_rx_shutdown(void)
  494. {
  495. int i;
  496. /* Shutdown all of the NAPIs */
  497. for_each_possible_cpu(i)
  498. netif_napi_del(&cvm_oct_napi[i].napi);
  499. }