pci.h 10 KB

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  1. #ifndef DRIVERS_PCI_H
  2. #define DRIVERS_PCI_H
  3. #include <linux/workqueue.h>
  4. #define PCI_CFG_SPACE_SIZE 256
  5. #define PCI_CFG_SPACE_EXP_SIZE 4096
  6. /* Functions internal to the PCI core code */
  7. extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
  8. extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  9. extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  10. #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  11. static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  12. { return; }
  13. static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  14. { return; }
  15. #else
  16. extern void pci_create_firmware_label_files(struct pci_dev *pdev);
  17. extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
  18. #endif
  19. extern void pci_cleanup_rom(struct pci_dev *dev);
  20. #ifdef HAVE_PCI_MMAP
  21. enum pci_mmap_api {
  22. PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  23. PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  24. };
  25. extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
  26. struct vm_area_struct *vmai,
  27. enum pci_mmap_api mmap_api);
  28. #endif
  29. int pci_probe_reset_function(struct pci_dev *dev);
  30. /**
  31. * struct pci_platform_pm_ops - Firmware PM callbacks
  32. *
  33. * @is_manageable: returns 'true' if given device is power manageable by the
  34. * platform firmware
  35. *
  36. * @set_state: invokes the platform firmware to set the device's power state
  37. *
  38. * @choose_state: returns PCI power state of given device preferred by the
  39. * platform; to be used during system-wide transitions from a
  40. * sleeping state to the working state and vice versa
  41. *
  42. * @can_wakeup: returns 'true' if given device is capable of waking up the
  43. * system from a sleeping state
  44. *
  45. * @sleep_wake: enables/disables the system wake up capability of given device
  46. *
  47. * @run_wake: enables/disables the platform to generate run-time wake-up events
  48. * for given device (the device's wake-up capability has to be
  49. * enabled by @sleep_wake for this feature to work)
  50. *
  51. * If given platform is generally capable of power managing PCI devices, all of
  52. * these callbacks are mandatory.
  53. */
  54. struct pci_platform_pm_ops {
  55. bool (*is_manageable)(struct pci_dev *dev);
  56. int (*set_state)(struct pci_dev *dev, pci_power_t state);
  57. pci_power_t (*choose_state)(struct pci_dev *dev);
  58. bool (*can_wakeup)(struct pci_dev *dev);
  59. int (*sleep_wake)(struct pci_dev *dev, bool enable);
  60. int (*run_wake)(struct pci_dev *dev, bool enable);
  61. };
  62. extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
  63. extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  64. extern void pci_disable_enabled_device(struct pci_dev *dev);
  65. extern int pci_finish_runtime_suspend(struct pci_dev *dev);
  66. extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  67. extern void pci_pm_init(struct pci_dev *dev);
  68. extern void platform_pci_wakeup_init(struct pci_dev *dev);
  69. extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  70. static inline void pci_wakeup_event(struct pci_dev *dev)
  71. {
  72. /* Wait 100 ms before the system can be put into a sleep state. */
  73. pm_wakeup_event(&dev->dev, 100);
  74. }
  75. static inline bool pci_is_bridge(struct pci_dev *pci_dev)
  76. {
  77. return !!(pci_dev->subordinate);
  78. }
  79. extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
  80. extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
  81. extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
  82. extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
  83. extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
  84. extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
  85. struct pci_vpd_ops {
  86. ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  87. ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  88. void (*release)(struct pci_dev *dev);
  89. };
  90. struct pci_vpd {
  91. unsigned int len;
  92. const struct pci_vpd_ops *ops;
  93. struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
  94. };
  95. extern int pci_vpd_pci22_init(struct pci_dev *dev);
  96. static inline void pci_vpd_release(struct pci_dev *dev)
  97. {
  98. if (dev->vpd)
  99. dev->vpd->ops->release(dev);
  100. }
  101. /* PCI /proc functions */
  102. #ifdef CONFIG_PROC_FS
  103. extern int pci_proc_attach_device(struct pci_dev *dev);
  104. extern int pci_proc_detach_device(struct pci_dev *dev);
  105. extern int pci_proc_detach_bus(struct pci_bus *bus);
  106. #else
  107. static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
  108. static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
  109. static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
  110. #endif
  111. /* Functions for PCI Hotplug drivers to use */
  112. extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
  113. #ifdef HAVE_PCI_LEGACY
  114. extern void pci_create_legacy_files(struct pci_bus *bus);
  115. extern void pci_remove_legacy_files(struct pci_bus *bus);
  116. #else
  117. static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  118. static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  119. #endif
  120. /* Lock for read/write access to pci device and bus lists */
  121. extern struct rw_semaphore pci_bus_sem;
  122. extern unsigned int pci_pm_d3_delay;
  123. #ifdef CONFIG_PCI_MSI
  124. void pci_no_msi(void);
  125. extern void pci_msi_init_pci_dev(struct pci_dev *dev);
  126. #else
  127. static inline void pci_no_msi(void) { }
  128. static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
  129. #endif
  130. extern void pci_realloc(void);
  131. static inline int pci_no_d1d2(struct pci_dev *dev)
  132. {
  133. unsigned int parent_dstates = 0;
  134. if (dev->bus->self)
  135. parent_dstates = dev->bus->self->no_d1d2;
  136. return (dev->no_d1d2 || parent_dstates);
  137. }
  138. extern struct device_attribute pci_dev_attrs[];
  139. extern struct device_attribute pcibus_dev_attrs[];
  140. #ifdef CONFIG_HOTPLUG
  141. extern struct bus_attribute pci_bus_attrs[];
  142. #else
  143. #define pci_bus_attrs NULL
  144. #endif
  145. /**
  146. * pci_match_one_device - Tell if a PCI device structure has a matching
  147. * PCI device id structure
  148. * @id: single PCI device id structure to match
  149. * @dev: the PCI device structure to match against
  150. *
  151. * Returns the matching pci_device_id structure or %NULL if there is no match.
  152. */
  153. static inline const struct pci_device_id *
  154. pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
  155. {
  156. if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
  157. (id->device == PCI_ANY_ID || id->device == dev->device) &&
  158. (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
  159. (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
  160. !((id->class ^ dev->class) & id->class_mask))
  161. return id;
  162. return NULL;
  163. }
  164. struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
  165. /* PCI slot sysfs helper code */
  166. #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
  167. extern struct kset *pci_slots_kset;
  168. struct pci_slot_attribute {
  169. struct attribute attr;
  170. ssize_t (*show)(struct pci_slot *, char *);
  171. ssize_t (*store)(struct pci_slot *, const char *, size_t);
  172. };
  173. #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
  174. enum pci_bar_type {
  175. pci_bar_unknown, /* Standard PCI BAR probe */
  176. pci_bar_io, /* An io port BAR */
  177. pci_bar_mem32, /* A 32-bit memory BAR */
  178. pci_bar_mem64, /* A 64-bit memory BAR */
  179. };
  180. extern int pci_setup_device(struct pci_dev *dev);
  181. extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
  182. struct resource *res, unsigned int reg);
  183. extern int pci_resource_bar(struct pci_dev *dev, int resno,
  184. enum pci_bar_type *type);
  185. extern int pci_bus_add_child(struct pci_bus *bus);
  186. extern void pci_enable_ari(struct pci_dev *dev);
  187. /**
  188. * pci_ari_enabled - query ARI forwarding status
  189. * @bus: the PCI bus
  190. *
  191. * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
  192. */
  193. static inline int pci_ari_enabled(struct pci_bus *bus)
  194. {
  195. return bus->self && bus->self->ari_enabled;
  196. }
  197. #ifdef CONFIG_PCI_QUIRKS
  198. extern int pci_is_reassigndev(struct pci_dev *dev);
  199. resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
  200. extern void pci_disable_bridge_window(struct pci_dev *dev);
  201. #endif
  202. /* Single Root I/O Virtualization */
  203. struct pci_sriov {
  204. int pos; /* capability position */
  205. int nres; /* number of resources */
  206. u32 cap; /* SR-IOV Capabilities */
  207. u16 ctrl; /* SR-IOV Control */
  208. u16 total; /* total VFs associated with the PF */
  209. u16 initial; /* initial VFs associated with the PF */
  210. u16 nr_virtfn; /* number of VFs available */
  211. u16 offset; /* first VF Routing ID offset */
  212. u16 stride; /* following VF stride */
  213. u32 pgsz; /* page size for BAR alignment */
  214. u8 link; /* Function Dependency Link */
  215. struct pci_dev *dev; /* lowest numbered PF */
  216. struct pci_dev *self; /* this PF */
  217. struct mutex lock; /* lock for VF bus */
  218. struct work_struct mtask; /* VF Migration task */
  219. u8 __iomem *mstate; /* VF Migration State Array */
  220. };
  221. #ifdef CONFIG_PCI_IOV
  222. extern int pci_iov_init(struct pci_dev *dev);
  223. extern void pci_iov_release(struct pci_dev *dev);
  224. extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
  225. enum pci_bar_type *type);
  226. extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
  227. int resno);
  228. extern void pci_restore_iov_state(struct pci_dev *dev);
  229. extern int pci_iov_bus_range(struct pci_bus *bus);
  230. #else
  231. static inline int pci_iov_init(struct pci_dev *dev)
  232. {
  233. return -ENODEV;
  234. }
  235. static inline void pci_iov_release(struct pci_dev *dev)
  236. {
  237. }
  238. static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
  239. enum pci_bar_type *type)
  240. {
  241. return 0;
  242. }
  243. static inline void pci_restore_iov_state(struct pci_dev *dev)
  244. {
  245. }
  246. static inline int pci_iov_bus_range(struct pci_bus *bus)
  247. {
  248. return 0;
  249. }
  250. #endif /* CONFIG_PCI_IOV */
  251. static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
  252. struct resource *res)
  253. {
  254. #ifdef CONFIG_PCI_IOV
  255. int resno = res - dev->resource;
  256. if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
  257. return pci_sriov_resource_alignment(dev, resno);
  258. #endif
  259. return resource_alignment(res);
  260. }
  261. extern void pci_enable_acs(struct pci_dev *dev);
  262. struct pci_dev_reset_methods {
  263. u16 vendor;
  264. u16 device;
  265. int (*reset)(struct pci_dev *dev, int probe);
  266. };
  267. #ifdef CONFIG_PCI_QUIRKS
  268. extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
  269. #else
  270. static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
  271. {
  272. return -ENOTTY;
  273. }
  274. #endif
  275. #endif /* DRIVERS_PCI_H */