dm_common.c 53 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "dm_common.h"
  30. #include "phy_common.h"
  31. #include "../pci.h"
  32. #include "../base.h"
  33. struct dig_t dm_digtable;
  34. static struct ps_t dm_pstable;
  35. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  36. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  37. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  38. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  39. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  40. #define RTLPRIV (struct rtl_priv *)
  41. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  42. ((RTLPRIV(_priv))->mac80211.opmode == \
  43. NL80211_IFTYPE_ADHOC) ? \
  44. ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
  45. ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
  46. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  47. 0x7f8001fe,
  48. 0x788001e2,
  49. 0x71c001c7,
  50. 0x6b8001ae,
  51. 0x65400195,
  52. 0x5fc0017f,
  53. 0x5a400169,
  54. 0x55400155,
  55. 0x50800142,
  56. 0x4c000130,
  57. 0x47c0011f,
  58. 0x43c0010f,
  59. 0x40000100,
  60. 0x3c8000f2,
  61. 0x390000e4,
  62. 0x35c000d7,
  63. 0x32c000cb,
  64. 0x300000c0,
  65. 0x2d4000b5,
  66. 0x2ac000ab,
  67. 0x288000a2,
  68. 0x26000098,
  69. 0x24000090,
  70. 0x22000088,
  71. 0x20000080,
  72. 0x1e400079,
  73. 0x1c800072,
  74. 0x1b00006c,
  75. 0x19800066,
  76. 0x18000060,
  77. 0x16c0005b,
  78. 0x15800056,
  79. 0x14400051,
  80. 0x1300004c,
  81. 0x12000048,
  82. 0x11000044,
  83. 0x10000040,
  84. };
  85. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  86. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  87. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  88. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  89. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  90. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  91. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  92. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  93. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  94. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  95. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  96. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  97. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  98. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  99. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  100. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  101. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  102. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  103. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  104. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  105. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  106. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  107. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  108. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  109. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  110. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  111. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  112. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  113. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  114. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  115. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  116. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  117. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  118. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  119. };
  120. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  121. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  122. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  123. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  124. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  125. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  126. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  127. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  128. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  129. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  130. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  131. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  132. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  133. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  134. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  135. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  136. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  137. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  138. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  139. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  140. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  141. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  142. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  143. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  144. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  145. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  146. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  147. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  148. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  149. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  150. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  151. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  152. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  153. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  154. };
  155. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  156. {
  157. dm_digtable.dig_enable_flag = true;
  158. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  159. dm_digtable.cur_igvalue = 0x20;
  160. dm_digtable.pre_igvalue = 0x0;
  161. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  162. dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
  163. dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  164. dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  165. dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  166. dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  167. dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  168. dm_digtable.rx_gain_range_max = DM_DIG_MAX;
  169. dm_digtable.rx_gain_range_min = DM_DIG_MIN;
  170. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  171. dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  172. dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  173. dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
  174. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  175. }
  176. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  177. {
  178. struct rtl_priv *rtlpriv = rtl_priv(hw);
  179. long rssi_val_min = 0;
  180. if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  181. (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
  182. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  183. rssi_val_min =
  184. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  185. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  186. rtlpriv->dm.undecorated_smoothed_pwdb :
  187. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  188. else
  189. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  190. } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
  191. dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  192. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  193. } else if (dm_digtable.curmultista_connectstate ==
  194. DIG_MULTISTA_CONNECT) {
  195. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  196. }
  197. return (u8) rssi_val_min;
  198. }
  199. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  200. {
  201. u32 ret_value;
  202. struct rtl_priv *rtlpriv = rtl_priv(hw);
  203. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  204. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  205. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  206. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  207. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  208. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  209. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  210. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  211. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  212. falsealm_cnt->cnt_rate_illegal +
  213. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  214. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  215. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  216. falsealm_cnt->cnt_cck_fail = ret_value;
  217. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  218. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  219. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  220. falsealm_cnt->cnt_rate_illegal +
  221. falsealm_cnt->cnt_crc8_fail +
  222. falsealm_cnt->cnt_mcs_fail +
  223. falsealm_cnt->cnt_cck_fail);
  224. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  225. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  226. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  227. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  228. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  229. ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
  230. "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  231. falsealm_cnt->cnt_parity_fail,
  232. falsealm_cnt->cnt_rate_illegal,
  233. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
  234. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  235. ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  236. falsealm_cnt->cnt_ofdm_fail,
  237. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
  238. }
  239. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  240. {
  241. struct rtl_priv *rtlpriv = rtl_priv(hw);
  242. u8 value_igi = dm_digtable.cur_igvalue;
  243. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  244. value_igi--;
  245. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  246. value_igi += 0;
  247. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  248. value_igi++;
  249. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  250. value_igi += 2;
  251. if (value_igi > DM_DIG_FA_UPPER)
  252. value_igi = DM_DIG_FA_UPPER;
  253. else if (value_igi < DM_DIG_FA_LOWER)
  254. value_igi = DM_DIG_FA_LOWER;
  255. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  256. value_igi = 0x32;
  257. dm_digtable.cur_igvalue = value_igi;
  258. rtl92c_dm_write_dig(hw);
  259. }
  260. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  261. {
  262. struct rtl_priv *rtlpriv = rtl_priv(hw);
  263. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
  264. if ((dm_digtable.backoff_val - 2) <
  265. dm_digtable.backoff_val_range_min)
  266. dm_digtable.backoff_val =
  267. dm_digtable.backoff_val_range_min;
  268. else
  269. dm_digtable.backoff_val -= 2;
  270. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
  271. if ((dm_digtable.backoff_val + 2) >
  272. dm_digtable.backoff_val_range_max)
  273. dm_digtable.backoff_val =
  274. dm_digtable.backoff_val_range_max;
  275. else
  276. dm_digtable.backoff_val += 2;
  277. }
  278. if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
  279. dm_digtable.rx_gain_range_max)
  280. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
  281. else if ((dm_digtable.rssi_val_min + 10 -
  282. dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
  283. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
  284. else
  285. dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
  286. dm_digtable.backoff_val;
  287. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  288. ("rssi_val_min = %x backoff_val %x\n",
  289. dm_digtable.rssi_val_min, dm_digtable.backoff_val));
  290. rtl92c_dm_write_dig(hw);
  291. }
  292. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  293. {
  294. static u8 initialized; /* initialized to false */
  295. struct rtl_priv *rtlpriv = rtl_priv(hw);
  296. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  297. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  298. bool multi_sta = false;
  299. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  300. multi_sta = true;
  301. if ((multi_sta == false) || (dm_digtable.cursta_connectctate !=
  302. DIG_STA_DISCONNECT)) {
  303. initialized = false;
  304. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  305. return;
  306. } else if (initialized == false) {
  307. initialized = true;
  308. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  309. dm_digtable.cur_igvalue = 0x20;
  310. rtl92c_dm_write_dig(hw);
  311. }
  312. if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  313. if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
  314. (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  315. if (dm_digtable.dig_ext_port_stage ==
  316. DIG_EXT_PORT_STAGE_2) {
  317. dm_digtable.cur_igvalue = 0x20;
  318. rtl92c_dm_write_dig(hw);
  319. }
  320. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  321. } else if (rssi_strength > dm_digtable.rssi_highthresh) {
  322. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  323. rtl92c_dm_ctrl_initgain_by_fa(hw);
  324. }
  325. } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  326. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  327. dm_digtable.cur_igvalue = 0x20;
  328. rtl92c_dm_write_dig(hw);
  329. }
  330. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  331. ("curmultista_connectstate = "
  332. "%x dig_ext_port_stage %x\n",
  333. dm_digtable.curmultista_connectstate,
  334. dm_digtable.dig_ext_port_stage));
  335. }
  336. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  337. {
  338. struct rtl_priv *rtlpriv = rtl_priv(hw);
  339. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  340. ("presta_connectstate = %x,"
  341. " cursta_connectctate = %x\n",
  342. dm_digtable.presta_connectstate,
  343. dm_digtable.cursta_connectctate));
  344. if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
  345. || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
  346. || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  347. if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  348. dm_digtable.rssi_val_min =
  349. rtl92c_dm_initial_gain_min_pwdb(hw);
  350. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  351. }
  352. } else {
  353. dm_digtable.rssi_val_min = 0;
  354. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  355. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  356. dm_digtable.cur_igvalue = 0x20;
  357. dm_digtable.pre_igvalue = 0;
  358. rtl92c_dm_write_dig(hw);
  359. }
  360. }
  361. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  362. {
  363. struct rtl_priv *rtlpriv = rtl_priv(hw);
  364. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  365. if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  366. dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  367. if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  368. if (dm_digtable.rssi_val_min <= 25)
  369. dm_digtable.cur_cck_pd_state =
  370. CCK_PD_STAGE_LowRssi;
  371. else
  372. dm_digtable.cur_cck_pd_state =
  373. CCK_PD_STAGE_HighRssi;
  374. } else {
  375. if (dm_digtable.rssi_val_min <= 20)
  376. dm_digtable.cur_cck_pd_state =
  377. CCK_PD_STAGE_LowRssi;
  378. else
  379. dm_digtable.cur_cck_pd_state =
  380. CCK_PD_STAGE_HighRssi;
  381. }
  382. } else {
  383. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  384. }
  385. if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
  386. if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  387. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  388. dm_digtable.cur_cck_fa_state =
  389. CCK_FA_STAGE_High;
  390. else
  391. dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
  392. if (dm_digtable.pre_cck_fa_state !=
  393. dm_digtable.cur_cck_fa_state) {
  394. if (dm_digtable.cur_cck_fa_state ==
  395. CCK_FA_STAGE_Low)
  396. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  397. 0x83);
  398. else
  399. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  400. 0xcd);
  401. dm_digtable.pre_cck_fa_state =
  402. dm_digtable.cur_cck_fa_state;
  403. }
  404. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  405. if (IS_92C_SERIAL(rtlhal->version))
  406. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  407. MASKBYTE2, 0xd7);
  408. } else {
  409. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  410. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  411. if (IS_92C_SERIAL(rtlhal->version))
  412. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  413. MASKBYTE2, 0xd3);
  414. }
  415. dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
  416. }
  417. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  418. ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
  419. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  420. ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
  421. }
  422. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  423. {
  424. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  425. if (mac->act_scanning == true)
  426. return;
  427. if (mac->link_state >= MAC80211_LINKED)
  428. dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
  429. else
  430. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  431. rtl92c_dm_initial_gain_sta(hw);
  432. rtl92c_dm_initial_gain_multi_sta(hw);
  433. rtl92c_dm_cck_packet_detection_thresh(hw);
  434. dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
  435. }
  436. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  437. {
  438. struct rtl_priv *rtlpriv = rtl_priv(hw);
  439. if (rtlpriv->dm.dm_initialgain_enable == false)
  440. return;
  441. if (dm_digtable.dig_enable_flag == false)
  442. return;
  443. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  444. }
  445. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  446. {
  447. struct rtl_priv *rtlpriv = rtl_priv(hw);
  448. rtlpriv->dm.dynamic_txpower_enable = false;
  449. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  450. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  451. }
  452. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  453. {
  454. struct rtl_priv *rtlpriv = rtl_priv(hw);
  455. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  456. ("cur_igvalue = 0x%x, "
  457. "pre_igvalue = 0x%x, backoff_val = %d\n",
  458. dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
  459. dm_digtable.backoff_val));
  460. dm_digtable.cur_igvalue += 2;
  461. if (dm_digtable.cur_igvalue > 0x3f)
  462. dm_digtable.cur_igvalue = 0x3f;
  463. if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
  464. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  465. dm_digtable.cur_igvalue);
  466. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  467. dm_digtable.cur_igvalue);
  468. dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
  469. }
  470. }
  471. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  472. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  473. {
  474. struct rtl_priv *rtlpriv = rtl_priv(hw);
  475. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  476. u8 h2c_parameter[3] = { 0 };
  477. return;
  478. if (tmpentry_max_pwdb != 0) {
  479. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  480. tmpentry_max_pwdb;
  481. } else {
  482. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  483. }
  484. if (tmpentry_min_pwdb != 0xff) {
  485. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  486. tmpentry_min_pwdb;
  487. } else {
  488. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  489. }
  490. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  491. h2c_parameter[0] = 0;
  492. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  493. }
  494. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  495. {
  496. struct rtl_priv *rtlpriv = rtl_priv(hw);
  497. rtlpriv->dm.current_turbo_edca = false;
  498. rtlpriv->dm.is_any_nonbepkts = false;
  499. rtlpriv->dm.is_cur_rdlstate = false;
  500. }
  501. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  502. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  503. {
  504. struct rtl_priv *rtlpriv = rtl_priv(hw);
  505. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  506. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  507. static u64 last_txok_cnt;
  508. static u64 last_rxok_cnt;
  509. static u32 last_bt_edca_ul;
  510. static u32 last_bt_edca_dl;
  511. u64 cur_txok_cnt = 0;
  512. u64 cur_rxok_cnt = 0;
  513. u32 edca_be_ul = 0x5ea42b;
  514. u32 edca_be_dl = 0x5ea42b;
  515. bool bt_change_edca = false;
  516. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  517. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  518. rtlpriv->dm.current_turbo_edca = false;
  519. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  520. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  521. }
  522. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  523. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  524. bt_change_edca = true;
  525. }
  526. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  527. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  528. bt_change_edca = true;
  529. }
  530. if (mac->link_state != MAC80211_LINKED) {
  531. rtlpriv->dm.current_turbo_edca = false;
  532. return;
  533. }
  534. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  535. if (!(edca_be_ul & 0xffff0000))
  536. edca_be_ul |= 0x005e0000;
  537. if (!(edca_be_dl & 0xffff0000))
  538. edca_be_dl |= 0x005e0000;
  539. }
  540. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  541. (!rtlpriv->dm.disable_framebursting))) {
  542. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  543. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  544. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  545. if (!rtlpriv->dm.is_cur_rdlstate ||
  546. !rtlpriv->dm.current_turbo_edca) {
  547. rtl_write_dword(rtlpriv,
  548. REG_EDCA_BE_PARAM,
  549. edca_be_dl);
  550. rtlpriv->dm.is_cur_rdlstate = true;
  551. }
  552. } else {
  553. if (rtlpriv->dm.is_cur_rdlstate ||
  554. !rtlpriv->dm.current_turbo_edca) {
  555. rtl_write_dword(rtlpriv,
  556. REG_EDCA_BE_PARAM,
  557. edca_be_ul);
  558. rtlpriv->dm.is_cur_rdlstate = false;
  559. }
  560. }
  561. rtlpriv->dm.current_turbo_edca = true;
  562. } else {
  563. if (rtlpriv->dm.current_turbo_edca) {
  564. u8 tmp = AC0_BE;
  565. rtlpriv->cfg->ops->set_hw_reg(hw,
  566. HW_VAR_AC_PARAM,
  567. (u8 *) (&tmp));
  568. rtlpriv->dm.current_turbo_edca = false;
  569. }
  570. }
  571. rtlpriv->dm.is_any_nonbepkts = false;
  572. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  573. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  574. }
  575. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  576. *hw)
  577. {
  578. struct rtl_priv *rtlpriv = rtl_priv(hw);
  579. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  580. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  581. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  582. u8 thermalvalue, delta, delta_lck, delta_iqk;
  583. long ele_a, ele_d, temp_cck, val_x, value32;
  584. long val_y, ele_c = 0;
  585. u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
  586. int i;
  587. bool is2t = IS_92C_SERIAL(rtlhal->version);
  588. u8 txpwr_level[2] = {0, 0};
  589. u8 ofdm_min_index = 6, rf;
  590. rtlpriv->dm.txpower_trackinginit = true;
  591. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  592. ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
  593. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  594. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  595. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  596. "eeprom_thermalmeter 0x%x\n",
  597. thermalvalue, rtlpriv->dm.thermalvalue,
  598. rtlefuse->eeprom_thermalmeter));
  599. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  600. rtlefuse->eeprom_thermalmeter));
  601. if (is2t)
  602. rf = 2;
  603. else
  604. rf = 1;
  605. if (thermalvalue) {
  606. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  607. MASKDWORD) & MASKOFDM_D;
  608. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  609. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  610. ofdm_index_old[0] = (u8) i;
  611. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  612. ("Initial pathA ele_d reg0x%x = 0x%lx, "
  613. "ofdm_index=0x%x\n",
  614. ROFDM0_XATXIQIMBALANCE,
  615. ele_d, ofdm_index_old[0]));
  616. break;
  617. }
  618. }
  619. if (is2t) {
  620. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  621. MASKDWORD) & MASKOFDM_D;
  622. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  623. if (ele_d == (ofdmswing_table[i] &
  624. MASKOFDM_D)) {
  625. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  626. DBG_LOUD,
  627. ("Initial pathB ele_d reg0x%x = "
  628. "0x%lx, ofdm_index=0x%x\n",
  629. ROFDM0_XBTXIQIMBALANCE, ele_d,
  630. ofdm_index_old[1]));
  631. break;
  632. }
  633. }
  634. }
  635. temp_cck =
  636. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  637. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  638. if (rtlpriv->dm.cck_inch14) {
  639. if (memcmp((void *)&temp_cck,
  640. (void *)&cckswing_table_ch14[i][2],
  641. 4) == 0) {
  642. cck_index_old = (u8) i;
  643. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  644. DBG_LOUD,
  645. ("Initial reg0x%x = 0x%lx, "
  646. "cck_index=0x%x, ch 14 %d\n",
  647. RCCK0_TXFILTER2, temp_cck,
  648. cck_index_old,
  649. rtlpriv->dm.cck_inch14));
  650. break;
  651. }
  652. } else {
  653. if (memcmp((void *)&temp_cck,
  654. (void *)
  655. &cckswing_table_ch1ch13[i][2],
  656. 4) == 0) {
  657. cck_index_old = (u8) i;
  658. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  659. DBG_LOUD,
  660. ("Initial reg0x%x = 0x%lx, "
  661. "cck_index=0x%x, ch14 %d\n",
  662. RCCK0_TXFILTER2, temp_cck,
  663. cck_index_old,
  664. rtlpriv->dm.cck_inch14));
  665. break;
  666. }
  667. }
  668. }
  669. if (!rtlpriv->dm.thermalvalue) {
  670. rtlpriv->dm.thermalvalue =
  671. rtlefuse->eeprom_thermalmeter;
  672. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  673. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  674. for (i = 0; i < rf; i++)
  675. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  676. rtlpriv->dm.cck_index = cck_index_old;
  677. }
  678. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  679. (thermalvalue - rtlpriv->dm.thermalvalue) :
  680. (rtlpriv->dm.thermalvalue - thermalvalue);
  681. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  682. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  683. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  684. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  685. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  686. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  687. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  688. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  689. "eeprom_thermalmeter 0x%x delta 0x%x "
  690. "delta_lck 0x%x delta_iqk 0x%x\n",
  691. thermalvalue, rtlpriv->dm.thermalvalue,
  692. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  693. delta_iqk));
  694. if (delta_lck > 1) {
  695. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  696. rtl92c_phy_lc_calibrate(hw);
  697. }
  698. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  699. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  700. for (i = 0; i < rf; i++)
  701. rtlpriv->dm.ofdm_index[i] -= delta;
  702. rtlpriv->dm.cck_index -= delta;
  703. } else {
  704. for (i = 0; i < rf; i++)
  705. rtlpriv->dm.ofdm_index[i] += delta;
  706. rtlpriv->dm.cck_index += delta;
  707. }
  708. if (is2t) {
  709. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  710. ("temp OFDM_A_index=0x%x, "
  711. "OFDM_B_index=0x%x,"
  712. "cck_index=0x%x\n",
  713. rtlpriv->dm.ofdm_index[0],
  714. rtlpriv->dm.ofdm_index[1],
  715. rtlpriv->dm.cck_index));
  716. } else {
  717. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  718. ("temp OFDM_A_index=0x%x,"
  719. "cck_index=0x%x\n",
  720. rtlpriv->dm.ofdm_index[0],
  721. rtlpriv->dm.cck_index));
  722. }
  723. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  724. for (i = 0; i < rf; i++)
  725. ofdm_index[i] =
  726. rtlpriv->dm.ofdm_index[i]
  727. + 1;
  728. cck_index = rtlpriv->dm.cck_index + 1;
  729. } else {
  730. for (i = 0; i < rf; i++)
  731. ofdm_index[i] =
  732. rtlpriv->dm.ofdm_index[i];
  733. cck_index = rtlpriv->dm.cck_index;
  734. }
  735. for (i = 0; i < rf; i++) {
  736. if (txpwr_level[i] >= 0 &&
  737. txpwr_level[i] <= 26) {
  738. if (thermalvalue >
  739. rtlefuse->eeprom_thermalmeter) {
  740. if (delta < 5)
  741. ofdm_index[i] -= 1;
  742. else
  743. ofdm_index[i] -= 2;
  744. } else if (delta > 5 && thermalvalue <
  745. rtlefuse->
  746. eeprom_thermalmeter) {
  747. ofdm_index[i] += 1;
  748. }
  749. } else if (txpwr_level[i] >= 27 &&
  750. txpwr_level[i] <= 32
  751. && thermalvalue >
  752. rtlefuse->eeprom_thermalmeter) {
  753. if (delta < 5)
  754. ofdm_index[i] -= 1;
  755. else
  756. ofdm_index[i] -= 2;
  757. } else if (txpwr_level[i] >= 32 &&
  758. txpwr_level[i] <= 38 &&
  759. thermalvalue >
  760. rtlefuse->eeprom_thermalmeter
  761. && delta > 5) {
  762. ofdm_index[i] -= 1;
  763. }
  764. }
  765. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  766. if (thermalvalue >
  767. rtlefuse->eeprom_thermalmeter) {
  768. if (delta < 5)
  769. cck_index -= 1;
  770. else
  771. cck_index -= 2;
  772. } else if (delta > 5 && thermalvalue <
  773. rtlefuse->eeprom_thermalmeter) {
  774. cck_index += 1;
  775. }
  776. } else if (txpwr_level[i] >= 27 &&
  777. txpwr_level[i] <= 32 &&
  778. thermalvalue >
  779. rtlefuse->eeprom_thermalmeter) {
  780. if (delta < 5)
  781. cck_index -= 1;
  782. else
  783. cck_index -= 2;
  784. } else if (txpwr_level[i] >= 32 &&
  785. txpwr_level[i] <= 38 &&
  786. thermalvalue > rtlefuse->eeprom_thermalmeter
  787. && delta > 5) {
  788. cck_index -= 1;
  789. }
  790. for (i = 0; i < rf; i++) {
  791. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  792. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  793. else if (ofdm_index[i] < ofdm_min_index)
  794. ofdm_index[i] = ofdm_min_index;
  795. }
  796. if (cck_index > CCK_TABLE_SIZE - 1)
  797. cck_index = CCK_TABLE_SIZE - 1;
  798. else if (cck_index < 0)
  799. cck_index = 0;
  800. if (is2t) {
  801. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  802. ("new OFDM_A_index=0x%x, "
  803. "OFDM_B_index=0x%x,"
  804. "cck_index=0x%x\n",
  805. ofdm_index[0], ofdm_index[1],
  806. cck_index));
  807. } else {
  808. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  809. ("new OFDM_A_index=0x%x,"
  810. "cck_index=0x%x\n",
  811. ofdm_index[0], cck_index));
  812. }
  813. }
  814. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  815. ele_d =
  816. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  817. val_x = rtlphy->reg_e94;
  818. val_y = rtlphy->reg_e9c;
  819. if (val_x != 0) {
  820. if ((val_x & 0x00000200) != 0)
  821. val_x = val_x | 0xFFFFFC00;
  822. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  823. if ((val_y & 0x00000200) != 0)
  824. val_y = val_y | 0xFFFFFC00;
  825. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  826. value32 = (ele_d << 22) |
  827. ((ele_c & 0x3F) << 16) | ele_a;
  828. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  829. MASKDWORD, value32);
  830. value32 = (ele_c & 0x000003C0) >> 6;
  831. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  832. value32);
  833. value32 = ((val_x * ele_d) >> 7) & 0x01;
  834. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  835. BIT(31), value32);
  836. value32 = ((val_y * ele_d) >> 7) & 0x01;
  837. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  838. BIT(29), value32);
  839. } else {
  840. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  841. MASKDWORD,
  842. ofdmswing_table[ofdm_index[0]]);
  843. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  844. 0x00);
  845. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  846. BIT(31) | BIT(29), 0x00);
  847. }
  848. if (!rtlpriv->dm.cck_inch14) {
  849. rtl_write_byte(rtlpriv, 0xa22,
  850. cckswing_table_ch1ch13[cck_index]
  851. [0]);
  852. rtl_write_byte(rtlpriv, 0xa23,
  853. cckswing_table_ch1ch13[cck_index]
  854. [1]);
  855. rtl_write_byte(rtlpriv, 0xa24,
  856. cckswing_table_ch1ch13[cck_index]
  857. [2]);
  858. rtl_write_byte(rtlpriv, 0xa25,
  859. cckswing_table_ch1ch13[cck_index]
  860. [3]);
  861. rtl_write_byte(rtlpriv, 0xa26,
  862. cckswing_table_ch1ch13[cck_index]
  863. [4]);
  864. rtl_write_byte(rtlpriv, 0xa27,
  865. cckswing_table_ch1ch13[cck_index]
  866. [5]);
  867. rtl_write_byte(rtlpriv, 0xa28,
  868. cckswing_table_ch1ch13[cck_index]
  869. [6]);
  870. rtl_write_byte(rtlpriv, 0xa29,
  871. cckswing_table_ch1ch13[cck_index]
  872. [7]);
  873. } else {
  874. rtl_write_byte(rtlpriv, 0xa22,
  875. cckswing_table_ch14[cck_index]
  876. [0]);
  877. rtl_write_byte(rtlpriv, 0xa23,
  878. cckswing_table_ch14[cck_index]
  879. [1]);
  880. rtl_write_byte(rtlpriv, 0xa24,
  881. cckswing_table_ch14[cck_index]
  882. [2]);
  883. rtl_write_byte(rtlpriv, 0xa25,
  884. cckswing_table_ch14[cck_index]
  885. [3]);
  886. rtl_write_byte(rtlpriv, 0xa26,
  887. cckswing_table_ch14[cck_index]
  888. [4]);
  889. rtl_write_byte(rtlpriv, 0xa27,
  890. cckswing_table_ch14[cck_index]
  891. [5]);
  892. rtl_write_byte(rtlpriv, 0xa28,
  893. cckswing_table_ch14[cck_index]
  894. [6]);
  895. rtl_write_byte(rtlpriv, 0xa29,
  896. cckswing_table_ch14[cck_index]
  897. [7]);
  898. }
  899. if (is2t) {
  900. ele_d = (ofdmswing_table[ofdm_index[1]] &
  901. 0xFFC00000) >> 22;
  902. val_x = rtlphy->reg_eb4;
  903. val_y = rtlphy->reg_ebc;
  904. if (val_x != 0) {
  905. if ((val_x & 0x00000200) != 0)
  906. val_x = val_x | 0xFFFFFC00;
  907. ele_a = ((val_x * ele_d) >> 8) &
  908. 0x000003FF;
  909. if ((val_y & 0x00000200) != 0)
  910. val_y = val_y | 0xFFFFFC00;
  911. ele_c = ((val_y * ele_d) >> 8) &
  912. 0x00003FF;
  913. value32 = (ele_d << 22) |
  914. ((ele_c & 0x3F) << 16) | ele_a;
  915. rtl_set_bbreg(hw,
  916. ROFDM0_XBTXIQIMBALANCE,
  917. MASKDWORD, value32);
  918. value32 = (ele_c & 0x000003C0) >> 6;
  919. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  920. MASKH4BITS, value32);
  921. value32 = ((val_x * ele_d) >> 7) & 0x01;
  922. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  923. BIT(27), value32);
  924. value32 = ((val_y * ele_d) >> 7) & 0x01;
  925. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  926. BIT(25), value32);
  927. } else {
  928. rtl_set_bbreg(hw,
  929. ROFDM0_XBTXIQIMBALANCE,
  930. MASKDWORD,
  931. ofdmswing_table[ofdm_index
  932. [1]]);
  933. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  934. MASKH4BITS, 0x00);
  935. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  936. BIT(27) | BIT(25), 0x00);
  937. }
  938. }
  939. }
  940. if (delta_iqk > 3) {
  941. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  942. rtl92c_phy_iq_calibrate(hw, false);
  943. }
  944. if (rtlpriv->dm.txpower_track_control)
  945. rtlpriv->dm.thermalvalue = thermalvalue;
  946. }
  947. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
  948. }
  949. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  950. struct ieee80211_hw *hw)
  951. {
  952. struct rtl_priv *rtlpriv = rtl_priv(hw);
  953. rtlpriv->dm.txpower_tracking = true;
  954. rtlpriv->dm.txpower_trackinginit = false;
  955. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  956. ("pMgntInfo->txpower_tracking = %d\n",
  957. rtlpriv->dm.txpower_tracking));
  958. }
  959. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  960. {
  961. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  962. }
  963. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  964. {
  965. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  966. }
  967. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  968. struct ieee80211_hw *hw)
  969. {
  970. struct rtl_priv *rtlpriv = rtl_priv(hw);
  971. static u8 tm_trigger;
  972. if (!rtlpriv->dm.txpower_tracking)
  973. return;
  974. if (!tm_trigger) {
  975. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  976. 0x60);
  977. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  978. ("Trigger 92S Thermal Meter!!\n"));
  979. tm_trigger = 1;
  980. return;
  981. } else {
  982. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  983. ("Schedule TxPowerTracking direct call!!\n"));
  984. rtl92c_dm_txpower_tracking_directcall(hw);
  985. tm_trigger = 0;
  986. }
  987. }
  988. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  989. {
  990. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  991. }
  992. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  993. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  994. {
  995. struct rtl_priv *rtlpriv = rtl_priv(hw);
  996. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  997. p_ra->ratr_state = DM_RATR_STA_INIT;
  998. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  999. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  1000. rtlpriv->dm.useramask = true;
  1001. else
  1002. rtlpriv->dm.useramask = false;
  1003. }
  1004. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  1005. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  1006. {
  1007. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1008. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1009. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1010. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1011. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  1012. struct ieee80211_sta *sta = NULL;
  1013. if (is_hal_stop(rtlhal)) {
  1014. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1015. ("<---- driver is going to unload\n"));
  1016. return;
  1017. }
  1018. if (!rtlpriv->dm.useramask) {
  1019. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1020. ("<---- driver does not control rate adaptive mask\n"));
  1021. return;
  1022. }
  1023. if (mac->link_state == MAC80211_LINKED &&
  1024. mac->opmode == NL80211_IFTYPE_STATION) {
  1025. switch (p_ra->pre_ratr_state) {
  1026. case DM_RATR_STA_HIGH:
  1027. high_rssithresh_for_ra = 50;
  1028. low_rssithresh_for_ra = 20;
  1029. break;
  1030. case DM_RATR_STA_MIDDLE:
  1031. high_rssithresh_for_ra = 55;
  1032. low_rssithresh_for_ra = 20;
  1033. break;
  1034. case DM_RATR_STA_LOW:
  1035. high_rssithresh_for_ra = 50;
  1036. low_rssithresh_for_ra = 25;
  1037. break;
  1038. default:
  1039. high_rssithresh_for_ra = 50;
  1040. low_rssithresh_for_ra = 20;
  1041. break;
  1042. }
  1043. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1044. (long)high_rssithresh_for_ra)
  1045. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1046. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1047. (long)low_rssithresh_for_ra)
  1048. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1049. else
  1050. p_ra->ratr_state = DM_RATR_STA_LOW;
  1051. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1052. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1053. ("RSSI = %ld\n",
  1054. rtlpriv->dm.undecorated_smoothed_pwdb));
  1055. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1056. ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
  1057. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1058. ("PreState = %d, CurState = %d\n",
  1059. p_ra->pre_ratr_state, p_ra->ratr_state));
  1060. /* Only the PCI card uses sta in the update rate table
  1061. * callback routine */
  1062. if (rtlhal->interface == INTF_PCI) {
  1063. rcu_read_lock();
  1064. sta = ieee80211_find_sta(mac->vif, mac->bssid);
  1065. }
  1066. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  1067. p_ra->ratr_state);
  1068. p_ra->pre_ratr_state = p_ra->ratr_state;
  1069. if (rtlhal->interface == INTF_PCI)
  1070. rcu_read_unlock();
  1071. }
  1072. }
  1073. }
  1074. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1075. {
  1076. dm_pstable.pre_ccastate = CCA_MAX;
  1077. dm_pstable.cur_ccasate = CCA_MAX;
  1078. dm_pstable.pre_rfstate = RF_MAX;
  1079. dm_pstable.cur_rfstate = RF_MAX;
  1080. dm_pstable.rssi_val_min = 0;
  1081. }
  1082. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1083. {
  1084. static u8 initialize;
  1085. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1086. if (initialize == 0) {
  1087. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1088. MASKDWORD) & 0x1CC000) >> 14;
  1089. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1090. MASKDWORD) & BIT(3)) >> 3;
  1091. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1092. MASKDWORD) & 0xFF000000) >> 24;
  1093. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1094. initialize = 1;
  1095. }
  1096. if (!bforce_in_normal) {
  1097. if (dm_pstable.rssi_val_min != 0) {
  1098. if (dm_pstable.pre_rfstate == RF_NORMAL) {
  1099. if (dm_pstable.rssi_val_min >= 30)
  1100. dm_pstable.cur_rfstate = RF_SAVE;
  1101. else
  1102. dm_pstable.cur_rfstate = RF_NORMAL;
  1103. } else {
  1104. if (dm_pstable.rssi_val_min <= 25)
  1105. dm_pstable.cur_rfstate = RF_NORMAL;
  1106. else
  1107. dm_pstable.cur_rfstate = RF_SAVE;
  1108. }
  1109. } else {
  1110. dm_pstable.cur_rfstate = RF_MAX;
  1111. }
  1112. } else {
  1113. dm_pstable.cur_rfstate = RF_NORMAL;
  1114. }
  1115. if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
  1116. if (dm_pstable.cur_rfstate == RF_SAVE) {
  1117. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1118. 0x1C0000, 0x2);
  1119. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1120. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1121. 0xFF000000, 0x63);
  1122. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1123. 0xC000, 0x2);
  1124. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1125. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1126. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1127. } else {
  1128. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1129. 0x1CC000, reg_874);
  1130. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1131. reg_c70);
  1132. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1133. reg_85c);
  1134. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1135. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1136. }
  1137. dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
  1138. }
  1139. }
  1140. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1141. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1142. {
  1143. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1144. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1145. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1146. if (((mac->link_state == MAC80211_NOLINK)) &&
  1147. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1148. dm_pstable.rssi_val_min = 0;
  1149. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1150. ("Not connected to any\n"));
  1151. }
  1152. if (mac->link_state == MAC80211_LINKED) {
  1153. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1154. dm_pstable.rssi_val_min =
  1155. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1156. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1157. ("AP Client PWDB = 0x%lx\n",
  1158. dm_pstable.rssi_val_min));
  1159. } else {
  1160. dm_pstable.rssi_val_min =
  1161. rtlpriv->dm.undecorated_smoothed_pwdb;
  1162. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1163. ("STA Default Port PWDB = 0x%lx\n",
  1164. dm_pstable.rssi_val_min));
  1165. }
  1166. } else {
  1167. dm_pstable.rssi_val_min =
  1168. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1169. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1170. ("AP Ext Port PWDB = 0x%lx\n",
  1171. dm_pstable.rssi_val_min));
  1172. }
  1173. if (IS_92C_SERIAL(rtlhal->version))
  1174. ;/* rtl92c_dm_1r_cca(hw); */
  1175. else
  1176. rtl92c_dm_rf_saving(hw, false);
  1177. }
  1178. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1179. {
  1180. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1181. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1182. rtl92c_dm_diginit(hw);
  1183. rtl92c_dm_init_dynamic_txpower(hw);
  1184. rtl92c_dm_init_edca_turbo(hw);
  1185. rtl92c_dm_init_rate_adaptive_mask(hw);
  1186. rtl92c_dm_initialize_txpower_tracking(hw);
  1187. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1188. }
  1189. EXPORT_SYMBOL(rtl92c_dm_init);
  1190. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1191. {
  1192. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1193. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1194. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1195. long undecorated_smoothed_pwdb;
  1196. if (!rtlpriv->dm.dynamic_txpower_enable)
  1197. return;
  1198. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1199. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1200. return;
  1201. }
  1202. if ((mac->link_state < MAC80211_LINKED) &&
  1203. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1204. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1205. ("Not connected to any\n"));
  1206. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1207. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1208. return;
  1209. }
  1210. if (mac->link_state >= MAC80211_LINKED) {
  1211. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1212. undecorated_smoothed_pwdb =
  1213. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1214. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1215. ("AP Client PWDB = 0x%lx\n",
  1216. undecorated_smoothed_pwdb));
  1217. } else {
  1218. undecorated_smoothed_pwdb =
  1219. rtlpriv->dm.undecorated_smoothed_pwdb;
  1220. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1221. ("STA Default Port PWDB = 0x%lx\n",
  1222. undecorated_smoothed_pwdb));
  1223. }
  1224. } else {
  1225. undecorated_smoothed_pwdb =
  1226. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1227. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1228. ("AP Ext Port PWDB = 0x%lx\n",
  1229. undecorated_smoothed_pwdb));
  1230. }
  1231. if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1232. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1233. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1234. ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
  1235. } else if ((undecorated_smoothed_pwdb <
  1236. (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1237. (undecorated_smoothed_pwdb >=
  1238. TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1239. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1240. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1241. ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
  1242. } else if (undecorated_smoothed_pwdb <
  1243. (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1244. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1245. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1246. ("TXHIGHPWRLEVEL_NORMAL\n"));
  1247. }
  1248. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1249. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1250. ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1251. rtlphy->current_channel));
  1252. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1253. }
  1254. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1255. }
  1256. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1257. {
  1258. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1259. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1260. bool fw_current_inpsmode = false;
  1261. bool fw_ps_awake = true;
  1262. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1263. (u8 *) (&fw_current_inpsmode));
  1264. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1265. (u8 *) (&fw_ps_awake));
  1266. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1267. fw_ps_awake)
  1268. && (!ppsc->rfchange_inprogress)) {
  1269. rtl92c_dm_pwdb_monitor(hw);
  1270. rtl92c_dm_dig(hw);
  1271. rtl92c_dm_false_alarm_counter_statistics(hw);
  1272. rtl92c_dm_dynamic_bb_powersaving(hw);
  1273. rtl92c_dm_dynamic_txpower(hw);
  1274. rtl92c_dm_check_txpower_tracking(hw);
  1275. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1276. rtl92c_dm_bt_coexist(hw);
  1277. rtl92c_dm_check_edca_turbo(hw);
  1278. }
  1279. }
  1280. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1281. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1282. {
  1283. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1284. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1285. long undecorated_smoothed_pwdb;
  1286. u8 curr_bt_rssi_state = 0x00;
  1287. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1288. undecorated_smoothed_pwdb =
  1289. GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1290. } else {
  1291. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
  1292. undecorated_smoothed_pwdb = 100;
  1293. else
  1294. undecorated_smoothed_pwdb =
  1295. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1296. }
  1297. /* Check RSSI to determine HighPower/NormalPower state for
  1298. * BT coexistence. */
  1299. if (undecorated_smoothed_pwdb >= 67)
  1300. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1301. else if (undecorated_smoothed_pwdb < 62)
  1302. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1303. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1304. if (undecorated_smoothed_pwdb >= 40)
  1305. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1306. else if (undecorated_smoothed_pwdb <= 32)
  1307. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1308. /* Marked RSSI state. It will be used to determine BT coexistence
  1309. * setting later. */
  1310. if (undecorated_smoothed_pwdb < 35)
  1311. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1312. else
  1313. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1314. /* Set Tx Power according to BT status. */
  1315. if (undecorated_smoothed_pwdb >= 30)
  1316. curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
  1317. else if (undecorated_smoothed_pwdb < 25)
  1318. curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
  1319. /* Check BT state related to BT_Idle in B/G mode. */
  1320. if (undecorated_smoothed_pwdb < 15)
  1321. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1322. else
  1323. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1324. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1325. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1326. return true;
  1327. } else {
  1328. return false;
  1329. }
  1330. }
  1331. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1332. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1333. {
  1334. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1335. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1336. u32 polling, ratio_tx, ratio_pri;
  1337. u32 bt_tx, bt_pri;
  1338. u8 bt_state;
  1339. u8 cur_service_type;
  1340. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1341. return false;
  1342. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1343. bt_tx = rtl_read_dword(rtlpriv, 0x488);
  1344. bt_tx = bt_tx & 0x00ffffff;
  1345. bt_pri = rtl_read_dword(rtlpriv, 0x48c);
  1346. bt_pri = bt_pri & 0x00ffffff;
  1347. polling = rtl_read_dword(rtlpriv, 0x490);
  1348. if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
  1349. polling == 0xffffffff && bt_state == 0xff)
  1350. return false;
  1351. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1352. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1353. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1354. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1355. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1356. bt_state = bt_state |
  1357. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1358. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1359. BIT_OFFSET_LEN_MASK_32(2, 1);
  1360. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1361. }
  1362. return true;
  1363. }
  1364. ratio_tx = bt_tx * 1000 / polling;
  1365. ratio_pri = bt_pri * 1000 / polling;
  1366. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1367. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1368. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1369. if ((ratio_tx < 30) && (ratio_pri < 30))
  1370. cur_service_type = BT_IDLE;
  1371. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1372. cur_service_type = BT_SCO;
  1373. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1374. cur_service_type = BT_BUSY;
  1375. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1376. cur_service_type = BT_OTHERBUSY;
  1377. else if (ratio_tx >= 500)
  1378. cur_service_type = BT_PAN;
  1379. else
  1380. cur_service_type = BT_OTHER_ACTION;
  1381. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1382. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1383. bt_state = bt_state |
  1384. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1385. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1386. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1387. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1388. /* Add interrupt migration when bt is not ini
  1389. * idle state (no traffic). */
  1390. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1391. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1392. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1393. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1394. } else {
  1395. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1396. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1397. }
  1398. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1399. return true;
  1400. }
  1401. }
  1402. return false;
  1403. }
  1404. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1405. {
  1406. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1407. static bool media_connect;
  1408. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1409. media_connect = false;
  1410. } else {
  1411. if (!media_connect) {
  1412. media_connect = true;
  1413. return true;
  1414. }
  1415. media_connect = true;
  1416. }
  1417. return false;
  1418. }
  1419. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1420. {
  1421. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1422. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1423. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1424. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1425. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1426. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1427. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1428. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1429. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1430. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1431. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1432. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1433. } else {
  1434. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1435. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1436. }
  1437. } else {
  1438. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1439. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1440. }
  1441. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1442. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1443. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1444. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1445. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1446. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1447. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1448. }
  1449. }
  1450. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
  1451. {
  1452. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1453. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1454. /* Only enable HW BT coexist when BT in "Busy" state. */
  1455. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1456. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1457. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1458. } else {
  1459. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1460. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1461. BT_RSSI_STATE_NORMAL_POWER)) {
  1462. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1463. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1464. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1465. WIRELESS_MODE_N_24G) &&
  1466. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1467. BT_RSSI_STATE_SPECIAL_LOW)) {
  1468. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1469. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1470. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1471. } else {
  1472. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1473. }
  1474. }
  1475. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1476. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1477. else
  1478. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1479. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1480. BT_RSSI_STATE_NORMAL_POWER) {
  1481. rtl92c_bt_set_normal(hw);
  1482. } else {
  1483. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1484. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1485. }
  1486. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1487. rtlpriv->cfg->ops->set_rfreg(hw,
  1488. RF90_PATH_A,
  1489. 0x1e,
  1490. 0xf0, 0xf);
  1491. } else {
  1492. rtlpriv->cfg->ops->set_rfreg(hw,
  1493. RF90_PATH_A, 0x1e, 0xf0,
  1494. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1495. }
  1496. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1497. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1498. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1499. BT_RSSI_STATE_TXPOWER_LOW) {
  1500. rtlpriv->dm.dynamic_txhighpower_lvl =
  1501. TXHIGHPWRLEVEL_BT2;
  1502. } else {
  1503. rtlpriv->dm.dynamic_txhighpower_lvl =
  1504. TXHIGHPWRLEVEL_BT1;
  1505. }
  1506. } else {
  1507. rtlpriv->dm.dynamic_txhighpower_lvl =
  1508. TXHIGHPWRLEVEL_NORMAL;
  1509. }
  1510. rtl92c_phy_set_txpower_level(hw,
  1511. rtlpriv->phy.current_channel);
  1512. }
  1513. }
  1514. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1515. {
  1516. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1517. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1518. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1519. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1520. rtl92c_bt_ant_isolation(hw);
  1521. } else {
  1522. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1523. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1524. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1525. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1526. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1527. }
  1528. }
  1529. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1530. {
  1531. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1532. bool wifi_connect_change;
  1533. bool bt_state_change;
  1534. bool rssi_state_change;
  1535. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1536. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1537. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1538. bt_state_change = rtl92c_bt_state_change(hw);
  1539. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1540. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1541. rtl92c_check_bt_change(hw);
  1542. }
  1543. }
  1544. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);