p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/slab.h>
  17. #include <linux/firmware.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/delay.h>
  20. #include <linux/completion.h>
  21. #include <net/mac80211.h>
  22. #include "p54.h"
  23. #include "lmac.h"
  24. #include "p54pci.h"
  25. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  26. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  27. MODULE_LICENSE("GPL");
  28. MODULE_ALIAS("prism54pci");
  29. MODULE_FIRMWARE("isl3886pci");
  30. static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  31. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  32. { PCI_DEVICE(0x1260, 0x3890) },
  33. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  34. { PCI_DEVICE(0x10b7, 0x6001) },
  35. /* Intersil PRISM Indigo Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3877) },
  37. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  38. { PCI_DEVICE(0x1260, 0x3886) },
  39. /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
  40. { PCI_DEVICE(0x1260, 0xffff) },
  41. { },
  42. };
  43. MODULE_DEVICE_TABLE(pci, p54p_table);
  44. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  45. {
  46. struct p54p_priv *priv = dev->priv;
  47. __le32 reg;
  48. int err;
  49. __le32 *data;
  50. u32 remains, left, device_addr;
  51. P54P_WRITE(int_enable, cpu_to_le32(0));
  52. P54P_READ(int_enable);
  53. udelay(10);
  54. reg = P54P_READ(ctrl_stat);
  55. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  56. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  57. P54P_WRITE(ctrl_stat, reg);
  58. P54P_READ(ctrl_stat);
  59. udelay(10);
  60. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. udelay(10);
  64. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  65. P54P_WRITE(ctrl_stat, reg);
  66. wmb();
  67. /* wait for the firmware to reset properly */
  68. mdelay(10);
  69. err = p54_parse_firmware(dev, priv->firmware);
  70. if (err)
  71. return err;
  72. if (priv->common.fw_interface != FW_LM86) {
  73. dev_err(&priv->pdev->dev, "wrong firmware, "
  74. "please get a LM86(PCI) firmware a try again.\n");
  75. return -EINVAL;
  76. }
  77. data = (__le32 *) priv->firmware->data;
  78. remains = priv->firmware->size;
  79. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  80. while (remains) {
  81. u32 i = 0;
  82. left = min((u32)0x1000, remains);
  83. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  84. P54P_READ(int_enable);
  85. device_addr += 0x1000;
  86. while (i < left) {
  87. P54P_WRITE(direct_mem_win[i], *data++);
  88. i += sizeof(u32);
  89. }
  90. remains -= left;
  91. P54P_READ(int_enable);
  92. }
  93. reg = P54P_READ(ctrl_stat);
  94. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  96. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  97. P54P_WRITE(ctrl_stat, reg);
  98. P54P_READ(ctrl_stat);
  99. udelay(10);
  100. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  101. P54P_WRITE(ctrl_stat, reg);
  102. wmb();
  103. udelay(10);
  104. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  105. P54P_WRITE(ctrl_stat, reg);
  106. wmb();
  107. udelay(10);
  108. /* wait for the firmware to boot properly */
  109. mdelay(100);
  110. return 0;
  111. }
  112. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  113. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  114. struct sk_buff **rx_buf, u32 index)
  115. {
  116. struct p54p_priv *priv = dev->priv;
  117. struct p54p_ring_control *ring_control = priv->ring_control;
  118. u32 limit, idx, i;
  119. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  120. limit = idx;
  121. limit -= index;
  122. limit = ring_limit - limit;
  123. i = idx % ring_limit;
  124. while (limit-- > 1) {
  125. struct p54p_desc *desc = &ring[i];
  126. if (!desc->host_addr) {
  127. struct sk_buff *skb;
  128. dma_addr_t mapping;
  129. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  130. if (!skb)
  131. break;
  132. mapping = pci_map_single(priv->pdev,
  133. skb_tail_pointer(skb),
  134. priv->common.rx_mtu + 32,
  135. PCI_DMA_FROMDEVICE);
  136. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  137. dev_kfree_skb_any(skb);
  138. dev_err(&priv->pdev->dev,
  139. "RX DMA Mapping error\n");
  140. break;
  141. }
  142. desc->host_addr = cpu_to_le32(mapping);
  143. desc->device_addr = 0; // FIXME: necessary?
  144. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  145. desc->flags = 0;
  146. rx_buf[i] = skb;
  147. }
  148. i++;
  149. idx++;
  150. i %= ring_limit;
  151. }
  152. wmb();
  153. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  154. }
  155. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  156. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  157. struct sk_buff **rx_buf)
  158. {
  159. struct p54p_priv *priv = dev->priv;
  160. struct p54p_ring_control *ring_control = priv->ring_control;
  161. struct p54p_desc *desc;
  162. u32 idx, i;
  163. i = (*index) % ring_limit;
  164. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  165. idx %= ring_limit;
  166. while (i != idx) {
  167. u16 len;
  168. struct sk_buff *skb;
  169. dma_addr_t dma_addr;
  170. desc = &ring[i];
  171. len = le16_to_cpu(desc->len);
  172. skb = rx_buf[i];
  173. if (!skb) {
  174. i++;
  175. i %= ring_limit;
  176. continue;
  177. }
  178. if (unlikely(len > priv->common.rx_mtu)) {
  179. if (net_ratelimit())
  180. dev_err(&priv->pdev->dev, "rx'd frame size "
  181. "exceeds length threshold.\n");
  182. len = priv->common.rx_mtu;
  183. }
  184. dma_addr = le32_to_cpu(desc->host_addr);
  185. pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
  186. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  187. skb_put(skb, len);
  188. if (p54_rx(dev, skb)) {
  189. pci_unmap_single(priv->pdev, dma_addr,
  190. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  191. rx_buf[i] = NULL;
  192. desc->host_addr = cpu_to_le32(0);
  193. } else {
  194. skb_trim(skb, 0);
  195. pci_dma_sync_single_for_device(priv->pdev, dma_addr,
  196. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  197. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  198. }
  199. i++;
  200. i %= ring_limit;
  201. }
  202. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
  203. }
  204. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  205. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  206. struct sk_buff **tx_buf)
  207. {
  208. struct p54p_priv *priv = dev->priv;
  209. struct p54p_ring_control *ring_control = priv->ring_control;
  210. struct p54p_desc *desc;
  211. struct sk_buff *skb;
  212. u32 idx, i;
  213. i = (*index) % ring_limit;
  214. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  215. idx %= ring_limit;
  216. while (i != idx) {
  217. desc = &ring[i];
  218. skb = tx_buf[i];
  219. tx_buf[i] = NULL;
  220. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  221. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  222. desc->host_addr = 0;
  223. desc->device_addr = 0;
  224. desc->len = 0;
  225. desc->flags = 0;
  226. if (skb && FREE_AFTER_TX(skb))
  227. p54_free_skb(dev, skb);
  228. i++;
  229. i %= ring_limit;
  230. }
  231. }
  232. static void p54p_tasklet(unsigned long dev_id)
  233. {
  234. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  235. struct p54p_priv *priv = dev->priv;
  236. struct p54p_ring_control *ring_control = priv->ring_control;
  237. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  238. ARRAY_SIZE(ring_control->tx_mgmt),
  239. priv->tx_buf_mgmt);
  240. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  241. ARRAY_SIZE(ring_control->tx_data),
  242. priv->tx_buf_data);
  243. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  244. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  245. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  246. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  247. wmb();
  248. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  249. }
  250. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  251. {
  252. struct ieee80211_hw *dev = dev_id;
  253. struct p54p_priv *priv = dev->priv;
  254. __le32 reg;
  255. reg = P54P_READ(int_ident);
  256. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  257. goto out;
  258. }
  259. P54P_WRITE(int_ack, reg);
  260. reg &= P54P_READ(int_enable);
  261. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  262. tasklet_schedule(&priv->tasklet);
  263. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  264. complete(&priv->boot_comp);
  265. out:
  266. return reg ? IRQ_HANDLED : IRQ_NONE;
  267. }
  268. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  269. {
  270. unsigned long flags;
  271. struct p54p_priv *priv = dev->priv;
  272. struct p54p_ring_control *ring_control = priv->ring_control;
  273. struct p54p_desc *desc;
  274. dma_addr_t mapping;
  275. u32 idx, i;
  276. spin_lock_irqsave(&priv->lock, flags);
  277. idx = le32_to_cpu(ring_control->host_idx[1]);
  278. i = idx % ARRAY_SIZE(ring_control->tx_data);
  279. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  280. PCI_DMA_TODEVICE);
  281. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  282. spin_unlock_irqrestore(&priv->lock, flags);
  283. p54_free_skb(dev, skb);
  284. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  285. return ;
  286. }
  287. priv->tx_buf_data[i] = skb;
  288. desc = &ring_control->tx_data[i];
  289. desc->host_addr = cpu_to_le32(mapping);
  290. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  291. desc->len = cpu_to_le16(skb->len);
  292. desc->flags = 0;
  293. wmb();
  294. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  295. spin_unlock_irqrestore(&priv->lock, flags);
  296. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  297. P54P_READ(dev_int);
  298. }
  299. static void p54p_stop(struct ieee80211_hw *dev)
  300. {
  301. struct p54p_priv *priv = dev->priv;
  302. struct p54p_ring_control *ring_control = priv->ring_control;
  303. unsigned int i;
  304. struct p54p_desc *desc;
  305. P54P_WRITE(int_enable, cpu_to_le32(0));
  306. P54P_READ(int_enable);
  307. udelay(10);
  308. free_irq(priv->pdev->irq, dev);
  309. tasklet_kill(&priv->tasklet);
  310. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  311. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  312. desc = &ring_control->rx_data[i];
  313. if (desc->host_addr)
  314. pci_unmap_single(priv->pdev,
  315. le32_to_cpu(desc->host_addr),
  316. priv->common.rx_mtu + 32,
  317. PCI_DMA_FROMDEVICE);
  318. kfree_skb(priv->rx_buf_data[i]);
  319. priv->rx_buf_data[i] = NULL;
  320. }
  321. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  322. desc = &ring_control->rx_mgmt[i];
  323. if (desc->host_addr)
  324. pci_unmap_single(priv->pdev,
  325. le32_to_cpu(desc->host_addr),
  326. priv->common.rx_mtu + 32,
  327. PCI_DMA_FROMDEVICE);
  328. kfree_skb(priv->rx_buf_mgmt[i]);
  329. priv->rx_buf_mgmt[i] = NULL;
  330. }
  331. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  332. desc = &ring_control->tx_data[i];
  333. if (desc->host_addr)
  334. pci_unmap_single(priv->pdev,
  335. le32_to_cpu(desc->host_addr),
  336. le16_to_cpu(desc->len),
  337. PCI_DMA_TODEVICE);
  338. p54_free_skb(dev, priv->tx_buf_data[i]);
  339. priv->tx_buf_data[i] = NULL;
  340. }
  341. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  342. desc = &ring_control->tx_mgmt[i];
  343. if (desc->host_addr)
  344. pci_unmap_single(priv->pdev,
  345. le32_to_cpu(desc->host_addr),
  346. le16_to_cpu(desc->len),
  347. PCI_DMA_TODEVICE);
  348. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  349. priv->tx_buf_mgmt[i] = NULL;
  350. }
  351. memset(ring_control, 0, sizeof(*ring_control));
  352. }
  353. static int p54p_open(struct ieee80211_hw *dev)
  354. {
  355. struct p54p_priv *priv = dev->priv;
  356. int err;
  357. init_completion(&priv->boot_comp);
  358. err = request_irq(priv->pdev->irq, p54p_interrupt,
  359. IRQF_SHARED, "p54pci", dev);
  360. if (err) {
  361. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  362. return err;
  363. }
  364. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  365. err = p54p_upload_firmware(dev);
  366. if (err) {
  367. free_irq(priv->pdev->irq, dev);
  368. return err;
  369. }
  370. priv->rx_idx_data = priv->tx_idx_data = 0;
  371. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  372. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  373. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
  374. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  375. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
  376. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  377. P54P_READ(ring_control_base);
  378. wmb();
  379. udelay(10);
  380. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  381. P54P_READ(int_enable);
  382. wmb();
  383. udelay(10);
  384. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  385. P54P_READ(dev_int);
  386. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  387. wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
  388. p54p_stop(dev);
  389. return -ETIMEDOUT;
  390. }
  391. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  392. P54P_READ(int_enable);
  393. wmb();
  394. udelay(10);
  395. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  396. P54P_READ(dev_int);
  397. wmb();
  398. udelay(10);
  399. return 0;
  400. }
  401. static int __devinit p54p_probe(struct pci_dev *pdev,
  402. const struct pci_device_id *id)
  403. {
  404. struct p54p_priv *priv;
  405. struct ieee80211_hw *dev;
  406. unsigned long mem_addr, mem_len;
  407. int err;
  408. err = pci_enable_device(pdev);
  409. if (err) {
  410. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  411. return err;
  412. }
  413. mem_addr = pci_resource_start(pdev, 0);
  414. mem_len = pci_resource_len(pdev, 0);
  415. if (mem_len < sizeof(struct p54p_csr)) {
  416. dev_err(&pdev->dev, "Too short PCI resources\n");
  417. goto err_disable_dev;
  418. }
  419. err = pci_request_regions(pdev, "p54pci");
  420. if (err) {
  421. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  422. goto err_disable_dev;
  423. }
  424. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  425. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  426. dev_err(&pdev->dev, "No suitable DMA available\n");
  427. goto err_free_reg;
  428. }
  429. pci_set_master(pdev);
  430. pci_try_set_mwi(pdev);
  431. pci_write_config_byte(pdev, 0x40, 0);
  432. pci_write_config_byte(pdev, 0x41, 0);
  433. dev = p54_init_common(sizeof(*priv));
  434. if (!dev) {
  435. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  436. err = -ENOMEM;
  437. goto err_free_reg;
  438. }
  439. priv = dev->priv;
  440. priv->pdev = pdev;
  441. SET_IEEE80211_DEV(dev, &pdev->dev);
  442. pci_set_drvdata(pdev, dev);
  443. priv->map = ioremap(mem_addr, mem_len);
  444. if (!priv->map) {
  445. dev_err(&pdev->dev, "Cannot map device memory\n");
  446. err = -ENOMEM;
  447. goto err_free_dev;
  448. }
  449. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  450. &priv->ring_control_dma);
  451. if (!priv->ring_control) {
  452. dev_err(&pdev->dev, "Cannot allocate rings\n");
  453. err = -ENOMEM;
  454. goto err_iounmap;
  455. }
  456. priv->common.open = p54p_open;
  457. priv->common.stop = p54p_stop;
  458. priv->common.tx = p54p_tx;
  459. spin_lock_init(&priv->lock);
  460. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  461. err = request_firmware(&priv->firmware, "isl3886pci",
  462. &priv->pdev->dev);
  463. if (err) {
  464. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  465. err = request_firmware(&priv->firmware, "isl3886",
  466. &priv->pdev->dev);
  467. if (err)
  468. goto err_free_common;
  469. }
  470. err = p54p_open(dev);
  471. if (err)
  472. goto err_free_common;
  473. err = p54_read_eeprom(dev);
  474. p54p_stop(dev);
  475. if (err)
  476. goto err_free_common;
  477. err = p54_register_common(dev, &pdev->dev);
  478. if (err)
  479. goto err_free_common;
  480. return 0;
  481. err_free_common:
  482. release_firmware(priv->firmware);
  483. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  484. priv->ring_control, priv->ring_control_dma);
  485. err_iounmap:
  486. iounmap(priv->map);
  487. err_free_dev:
  488. pci_set_drvdata(pdev, NULL);
  489. p54_free_common(dev);
  490. err_free_reg:
  491. pci_release_regions(pdev);
  492. err_disable_dev:
  493. pci_disable_device(pdev);
  494. return err;
  495. }
  496. static void __devexit p54p_remove(struct pci_dev *pdev)
  497. {
  498. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  499. struct p54p_priv *priv;
  500. if (!dev)
  501. return;
  502. p54_unregister_common(dev);
  503. priv = dev->priv;
  504. release_firmware(priv->firmware);
  505. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  506. priv->ring_control, priv->ring_control_dma);
  507. iounmap(priv->map);
  508. pci_release_regions(pdev);
  509. pci_disable_device(pdev);
  510. p54_free_common(dev);
  511. }
  512. #ifdef CONFIG_PM
  513. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  514. {
  515. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  516. struct p54p_priv *priv = dev->priv;
  517. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  518. ieee80211_stop_queues(dev);
  519. p54p_stop(dev);
  520. }
  521. pci_save_state(pdev);
  522. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  523. return 0;
  524. }
  525. static int p54p_resume(struct pci_dev *pdev)
  526. {
  527. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  528. struct p54p_priv *priv = dev->priv;
  529. pci_set_power_state(pdev, PCI_D0);
  530. pci_restore_state(pdev);
  531. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  532. p54p_open(dev);
  533. ieee80211_wake_queues(dev);
  534. }
  535. return 0;
  536. }
  537. #endif /* CONFIG_PM */
  538. static struct pci_driver p54p_driver = {
  539. .name = "p54pci",
  540. .id_table = p54p_table,
  541. .probe = p54p_probe,
  542. .remove = __devexit_p(p54p_remove),
  543. #ifdef CONFIG_PM
  544. .suspend = p54p_suspend,
  545. .resume = p54p_resume,
  546. #endif /* CONFIG_PM */
  547. };
  548. static int __init p54p_init(void)
  549. {
  550. return pci_register_driver(&p54p_driver);
  551. }
  552. static void __exit p54p_exit(void)
  553. {
  554. pci_unregister_driver(&p54p_driver);
  555. }
  556. module_init(p54p_init);
  557. module_exit(p54p_exit);