iwl-4965-lib.c 37 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/sched.h>
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-helpers.h"
  38. #include "iwl-4965-hw.h"
  39. #include "iwl-4965.h"
  40. #include "iwl-sta.h"
  41. void iwl4965_check_abort_status(struct iwl_priv *priv,
  42. u8 frame_count, u32 status)
  43. {
  44. if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
  45. IWL_ERR(priv, "Tx flush command to flush out all frames\n");
  46. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  47. queue_work(priv->workqueue, &priv->tx_flush);
  48. }
  49. }
  50. /*
  51. * EEPROM
  52. */
  53. struct iwl_mod_params iwl4965_mod_params = {
  54. .amsdu_size_8K = 1,
  55. .restart_fw = 1,
  56. /* the rest are 0 by default */
  57. };
  58. void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  59. {
  60. unsigned long flags;
  61. int i;
  62. spin_lock_irqsave(&rxq->lock, flags);
  63. INIT_LIST_HEAD(&rxq->rx_free);
  64. INIT_LIST_HEAD(&rxq->rx_used);
  65. /* Fill the rx_used queue with _all_ of the Rx buffers */
  66. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  67. /* In the reset function, these buffers may have been allocated
  68. * to an SKB, so we need to unmap and free potential storage */
  69. if (rxq->pool[i].page != NULL) {
  70. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  71. PAGE_SIZE << priv->hw_params.rx_page_order,
  72. PCI_DMA_FROMDEVICE);
  73. __iwl_legacy_free_pages(priv, rxq->pool[i].page);
  74. rxq->pool[i].page = NULL;
  75. }
  76. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  77. }
  78. for (i = 0; i < RX_QUEUE_SIZE; i++)
  79. rxq->queue[i] = NULL;
  80. /* Set us so that we have processed and used all buffers, but have
  81. * not restocked the Rx queue with fresh buffers */
  82. rxq->read = rxq->write = 0;
  83. rxq->write_actual = 0;
  84. rxq->free_count = 0;
  85. spin_unlock_irqrestore(&rxq->lock, flags);
  86. }
  87. int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  88. {
  89. u32 rb_size;
  90. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  91. u32 rb_timeout = 0;
  92. if (priv->cfg->mod_params->amsdu_size_8K)
  93. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  94. else
  95. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  96. /* Stop Rx DMA */
  97. iwl_legacy_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  98. /* Reset driver's Rx queue write index */
  99. iwl_legacy_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  100. /* Tell device where to find RBD circular buffer in DRAM */
  101. iwl_legacy_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  102. (u32)(rxq->bd_dma >> 8));
  103. /* Tell device where in DRAM to update its Rx status */
  104. iwl_legacy_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  105. rxq->rb_stts_dma >> 4);
  106. /* Enable Rx DMA
  107. * Direct rx interrupts to hosts
  108. * Rx buffer size 4 or 8k
  109. * RB timeout 0x10
  110. * 256 RBDs
  111. */
  112. iwl_legacy_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  113. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  114. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  115. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  116. rb_size|
  117. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  118. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  119. /* Set interrupt coalescing timer to default (2048 usecs) */
  120. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  121. return 0;
  122. }
  123. static void iwl4965_set_pwr_vmain(struct iwl_priv *priv)
  124. {
  125. /*
  126. * (for documentation purposes)
  127. * to set power to V_AUX, do:
  128. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  129. iwl_legacy_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  130. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  131. ~APMG_PS_CTRL_MSK_PWR_SRC);
  132. */
  133. iwl_legacy_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  134. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  135. ~APMG_PS_CTRL_MSK_PWR_SRC);
  136. }
  137. int iwl4965_hw_nic_init(struct iwl_priv *priv)
  138. {
  139. unsigned long flags;
  140. struct iwl_rx_queue *rxq = &priv->rxq;
  141. int ret;
  142. /* nic_init */
  143. spin_lock_irqsave(&priv->lock, flags);
  144. priv->cfg->ops->lib->apm_ops.init(priv);
  145. /* Set interrupt coalescing calibration timer to default (512 usecs) */
  146. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
  147. spin_unlock_irqrestore(&priv->lock, flags);
  148. iwl4965_set_pwr_vmain(priv);
  149. priv->cfg->ops->lib->apm_ops.config(priv);
  150. /* Allocate the RX queue, or reset if it is already allocated */
  151. if (!rxq->bd) {
  152. ret = iwl_legacy_rx_queue_alloc(priv);
  153. if (ret) {
  154. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  155. return -ENOMEM;
  156. }
  157. } else
  158. iwl4965_rx_queue_reset(priv, rxq);
  159. iwl4965_rx_replenish(priv);
  160. iwl4965_rx_init(priv, rxq);
  161. spin_lock_irqsave(&priv->lock, flags);
  162. rxq->need_update = 1;
  163. iwl_legacy_rx_queue_update_write_ptr(priv, rxq);
  164. spin_unlock_irqrestore(&priv->lock, flags);
  165. /* Allocate or reset and init all Tx and Command queues */
  166. if (!priv->txq) {
  167. ret = iwl4965_txq_ctx_alloc(priv);
  168. if (ret)
  169. return ret;
  170. } else
  171. iwl4965_txq_ctx_reset(priv);
  172. set_bit(STATUS_INIT, &priv->status);
  173. return 0;
  174. }
  175. /**
  176. * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  177. */
  178. static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv,
  179. dma_addr_t dma_addr)
  180. {
  181. return cpu_to_le32((u32)(dma_addr >> 8));
  182. }
  183. /**
  184. * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
  185. *
  186. * If there are slots in the RX queue that need to be restocked,
  187. * and we have free pre-allocated buffers, fill the ranks as much
  188. * as we can, pulling from rx_free.
  189. *
  190. * This moves the 'write' index forward to catch up with 'processed', and
  191. * also updates the memory address in the firmware to reference the new
  192. * target buffer.
  193. */
  194. void iwl4965_rx_queue_restock(struct iwl_priv *priv)
  195. {
  196. struct iwl_rx_queue *rxq = &priv->rxq;
  197. struct list_head *element;
  198. struct iwl_rx_mem_buffer *rxb;
  199. unsigned long flags;
  200. spin_lock_irqsave(&rxq->lock, flags);
  201. while ((iwl_legacy_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  202. /* The overwritten rxb must be a used one */
  203. rxb = rxq->queue[rxq->write];
  204. BUG_ON(rxb && rxb->page);
  205. /* Get next free Rx buffer, remove from free list */
  206. element = rxq->rx_free.next;
  207. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  208. list_del(element);
  209. /* Point to Rx buffer via next RBD in circular buffer */
  210. rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv,
  211. rxb->page_dma);
  212. rxq->queue[rxq->write] = rxb;
  213. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  214. rxq->free_count--;
  215. }
  216. spin_unlock_irqrestore(&rxq->lock, flags);
  217. /* If the pre-allocated buffer pool is dropping low, schedule to
  218. * refill it */
  219. if (rxq->free_count <= RX_LOW_WATERMARK)
  220. queue_work(priv->workqueue, &priv->rx_replenish);
  221. /* If we've added more space for the firmware to place data, tell it.
  222. * Increment device's write pointer in multiples of 8. */
  223. if (rxq->write_actual != (rxq->write & ~0x7)) {
  224. spin_lock_irqsave(&rxq->lock, flags);
  225. rxq->need_update = 1;
  226. spin_unlock_irqrestore(&rxq->lock, flags);
  227. iwl_legacy_rx_queue_update_write_ptr(priv, rxq);
  228. }
  229. }
  230. /**
  231. * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
  232. *
  233. * When moving to rx_free an SKB is allocated for the slot.
  234. *
  235. * Also restock the Rx queue via iwl_rx_queue_restock.
  236. * This is called as a scheduled work item (except for during initialization)
  237. */
  238. static void iwl4965_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  239. {
  240. struct iwl_rx_queue *rxq = &priv->rxq;
  241. struct list_head *element;
  242. struct iwl_rx_mem_buffer *rxb;
  243. struct page *page;
  244. unsigned long flags;
  245. gfp_t gfp_mask = priority;
  246. while (1) {
  247. spin_lock_irqsave(&rxq->lock, flags);
  248. if (list_empty(&rxq->rx_used)) {
  249. spin_unlock_irqrestore(&rxq->lock, flags);
  250. return;
  251. }
  252. spin_unlock_irqrestore(&rxq->lock, flags);
  253. if (rxq->free_count > RX_LOW_WATERMARK)
  254. gfp_mask |= __GFP_NOWARN;
  255. if (priv->hw_params.rx_page_order > 0)
  256. gfp_mask |= __GFP_COMP;
  257. /* Alloc a new receive buffer */
  258. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  259. if (!page) {
  260. if (net_ratelimit())
  261. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  262. "order: %d\n",
  263. priv->hw_params.rx_page_order);
  264. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  265. net_ratelimit())
  266. IWL_CRIT(priv,
  267. "Failed to alloc_pages with %s. "
  268. "Only %u free buffers remaining.\n",
  269. priority == GFP_ATOMIC ?
  270. "GFP_ATOMIC" : "GFP_KERNEL",
  271. rxq->free_count);
  272. /* We don't reschedule replenish work here -- we will
  273. * call the restock method and if it still needs
  274. * more buffers it will schedule replenish */
  275. return;
  276. }
  277. spin_lock_irqsave(&rxq->lock, flags);
  278. if (list_empty(&rxq->rx_used)) {
  279. spin_unlock_irqrestore(&rxq->lock, flags);
  280. __free_pages(page, priv->hw_params.rx_page_order);
  281. return;
  282. }
  283. element = rxq->rx_used.next;
  284. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  285. list_del(element);
  286. spin_unlock_irqrestore(&rxq->lock, flags);
  287. BUG_ON(rxb->page);
  288. rxb->page = page;
  289. /* Get physical address of the RB */
  290. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  291. PAGE_SIZE << priv->hw_params.rx_page_order,
  292. PCI_DMA_FROMDEVICE);
  293. /* dma address must be no more than 36 bits */
  294. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  295. /* and also 256 byte aligned! */
  296. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  297. spin_lock_irqsave(&rxq->lock, flags);
  298. list_add_tail(&rxb->list, &rxq->rx_free);
  299. rxq->free_count++;
  300. priv->alloc_rxb_page++;
  301. spin_unlock_irqrestore(&rxq->lock, flags);
  302. }
  303. }
  304. void iwl4965_rx_replenish(struct iwl_priv *priv)
  305. {
  306. unsigned long flags;
  307. iwl4965_rx_allocate(priv, GFP_KERNEL);
  308. spin_lock_irqsave(&priv->lock, flags);
  309. iwl4965_rx_queue_restock(priv);
  310. spin_unlock_irqrestore(&priv->lock, flags);
  311. }
  312. void iwl4965_rx_replenish_now(struct iwl_priv *priv)
  313. {
  314. iwl4965_rx_allocate(priv, GFP_ATOMIC);
  315. iwl4965_rx_queue_restock(priv);
  316. }
  317. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  318. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  319. * This free routine walks the list of POOL entries and if SKB is set to
  320. * non NULL it is unmapped and freed
  321. */
  322. void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  323. {
  324. int i;
  325. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  326. if (rxq->pool[i].page != NULL) {
  327. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  328. PAGE_SIZE << priv->hw_params.rx_page_order,
  329. PCI_DMA_FROMDEVICE);
  330. __iwl_legacy_free_pages(priv, rxq->pool[i].page);
  331. rxq->pool[i].page = NULL;
  332. }
  333. }
  334. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  335. rxq->bd_dma);
  336. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  337. rxq->rb_stts, rxq->rb_stts_dma);
  338. rxq->bd = NULL;
  339. rxq->rb_stts = NULL;
  340. }
  341. int iwl4965_rxq_stop(struct iwl_priv *priv)
  342. {
  343. /* stop Rx DMA */
  344. iwl_legacy_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  345. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  346. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  347. return 0;
  348. }
  349. int iwl4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  350. {
  351. int idx = 0;
  352. int band_offset = 0;
  353. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  354. if (rate_n_flags & RATE_MCS_HT_MSK) {
  355. idx = (rate_n_flags & 0xff);
  356. return idx;
  357. /* Legacy rate format, search for match in table */
  358. } else {
  359. if (band == IEEE80211_BAND_5GHZ)
  360. band_offset = IWL_FIRST_OFDM_RATE;
  361. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  362. if (iwlegacy_rates[idx].plcp == (rate_n_flags & 0xFF))
  363. return idx - band_offset;
  364. }
  365. return -1;
  366. }
  367. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  368. struct iwl_rx_phy_res *rx_resp)
  369. {
  370. /* data from PHY/DSP regarding signal strength, etc.,
  371. * contents are always there, not configurable by host. */
  372. struct iwl4965_rx_non_cfg_phy *ncphy =
  373. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
  374. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
  375. >> IWL49_AGC_DB_POS;
  376. u32 valid_antennae =
  377. (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
  378. >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
  379. u8 max_rssi = 0;
  380. u32 i;
  381. /* Find max rssi among 3 possible receivers.
  382. * These values are measured by the digital signal processor (DSP).
  383. * They should stay fairly constant even as the signal strength varies,
  384. * if the radio's automatic gain control (AGC) is working right.
  385. * AGC value (see below) will provide the "interesting" info. */
  386. for (i = 0; i < 3; i++)
  387. if (valid_antennae & (1 << i))
  388. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  389. IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  390. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  391. max_rssi, agc);
  392. /* dBm = max_rssi dB - agc dB - constant.
  393. * Higher AGC (higher radio gain) means lower signal. */
  394. return max_rssi - agc - IWL4965_RSSI_OFFSET;
  395. }
  396. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  397. {
  398. u32 decrypt_out = 0;
  399. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  400. RX_RES_STATUS_STATION_FOUND)
  401. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  402. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  403. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  404. /* packet was not encrypted */
  405. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  406. RX_RES_STATUS_SEC_TYPE_NONE)
  407. return decrypt_out;
  408. /* packet was encrypted with unknown alg */
  409. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  410. RX_RES_STATUS_SEC_TYPE_ERR)
  411. return decrypt_out;
  412. /* decryption was not done in HW */
  413. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  414. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  415. return decrypt_out;
  416. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  417. case RX_RES_STATUS_SEC_TYPE_CCMP:
  418. /* alg is CCM: check MIC only */
  419. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  420. /* Bad MIC */
  421. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  422. else
  423. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  424. break;
  425. case RX_RES_STATUS_SEC_TYPE_TKIP:
  426. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  427. /* Bad TTAK */
  428. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  429. break;
  430. }
  431. /* fall through if TTAK OK */
  432. default:
  433. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  434. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  435. else
  436. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  437. break;
  438. }
  439. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  440. decrypt_in, decrypt_out);
  441. return decrypt_out;
  442. }
  443. static void iwl4965_pass_packet_to_mac80211(struct iwl_priv *priv,
  444. struct ieee80211_hdr *hdr,
  445. u16 len,
  446. u32 ampdu_status,
  447. struct iwl_rx_mem_buffer *rxb,
  448. struct ieee80211_rx_status *stats)
  449. {
  450. struct sk_buff *skb;
  451. __le16 fc = hdr->frame_control;
  452. /* We only process data packets if the interface is open */
  453. if (unlikely(!priv->is_open)) {
  454. IWL_DEBUG_DROP_LIMIT(priv,
  455. "Dropping packet while interface is not open.\n");
  456. return;
  457. }
  458. /* In case of HW accelerated crypto and bad decryption, drop */
  459. if (!priv->cfg->mod_params->sw_crypto &&
  460. iwl_legacy_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  461. return;
  462. skb = dev_alloc_skb(128);
  463. if (!skb) {
  464. IWL_ERR(priv, "dev_alloc_skb failed\n");
  465. return;
  466. }
  467. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  468. iwl_legacy_update_stats(priv, false, fc, len);
  469. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  470. ieee80211_rx(priv->hw, skb);
  471. priv->alloc_rxb_page--;
  472. rxb->page = NULL;
  473. }
  474. /* Called for REPLY_RX (legacy ABG frames), or
  475. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  476. void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  477. struct iwl_rx_mem_buffer *rxb)
  478. {
  479. struct ieee80211_hdr *header;
  480. struct ieee80211_rx_status rx_status;
  481. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  482. struct iwl_rx_phy_res *phy_res;
  483. __le32 rx_pkt_status;
  484. struct iwl_rx_mpdu_res_start *amsdu;
  485. u32 len;
  486. u32 ampdu_status;
  487. u32 rate_n_flags;
  488. /**
  489. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  490. * REPLY_RX: physical layer info is in this buffer
  491. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  492. * command and cached in priv->last_phy_res
  493. *
  494. * Here we set up local variables depending on which command is
  495. * received.
  496. */
  497. if (pkt->hdr.cmd == REPLY_RX) {
  498. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  499. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  500. + phy_res->cfg_phy_cnt);
  501. len = le16_to_cpu(phy_res->byte_count);
  502. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  503. phy_res->cfg_phy_cnt + len);
  504. ampdu_status = le32_to_cpu(rx_pkt_status);
  505. } else {
  506. if (!priv->_4965.last_phy_res_valid) {
  507. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  508. return;
  509. }
  510. phy_res = &priv->_4965.last_phy_res;
  511. amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
  512. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  513. len = le16_to_cpu(amsdu->byte_count);
  514. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  515. ampdu_status = iwl4965_translate_rx_status(priv,
  516. le32_to_cpu(rx_pkt_status));
  517. }
  518. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  519. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  520. phy_res->cfg_phy_cnt);
  521. return;
  522. }
  523. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  524. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  525. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  526. le32_to_cpu(rx_pkt_status));
  527. return;
  528. }
  529. /* This will be used in several places later */
  530. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  531. /* rx_status carries information about the packet to mac80211 */
  532. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  533. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  534. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  535. rx_status.freq =
  536. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
  537. rx_status.band);
  538. rx_status.rate_idx =
  539. iwl4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  540. rx_status.flag = 0;
  541. /* TSF isn't reliable. In order to allow smooth user experience,
  542. * this W/A doesn't propagate it to the mac80211 */
  543. /*rx_status.flag |= RX_FLAG_MACTIME_MPDU;*/
  544. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  545. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  546. rx_status.signal = iwl4965_calc_rssi(priv, phy_res);
  547. iwl_legacy_dbg_log_rx_data_frame(priv, len, header);
  548. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
  549. rx_status.signal, (unsigned long long)rx_status.mactime);
  550. /*
  551. * "antenna number"
  552. *
  553. * It seems that the antenna field in the phy flags value
  554. * is actually a bit field. This is undefined by radiotap,
  555. * it wants an actual antenna number but I always get "7"
  556. * for most legacy frames I receive indicating that the
  557. * same frame was received on all three RX chains.
  558. *
  559. * I think this field should be removed in favor of a
  560. * new 802.11n radiotap field "RX chains" that is defined
  561. * as a bitmask.
  562. */
  563. rx_status.antenna =
  564. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  565. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  566. /* set the preamble flag if appropriate */
  567. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  568. rx_status.flag |= RX_FLAG_SHORTPRE;
  569. /* Set up the HT phy flags */
  570. if (rate_n_flags & RATE_MCS_HT_MSK)
  571. rx_status.flag |= RX_FLAG_HT;
  572. if (rate_n_flags & RATE_MCS_HT40_MSK)
  573. rx_status.flag |= RX_FLAG_40MHZ;
  574. if (rate_n_flags & RATE_MCS_SGI_MSK)
  575. rx_status.flag |= RX_FLAG_SHORT_GI;
  576. iwl4965_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  577. rxb, &rx_status);
  578. }
  579. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  580. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  581. void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  582. struct iwl_rx_mem_buffer *rxb)
  583. {
  584. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  585. priv->_4965.last_phy_res_valid = true;
  586. memcpy(&priv->_4965.last_phy_res, pkt->u.raw,
  587. sizeof(struct iwl_rx_phy_res));
  588. }
  589. static int iwl4965_get_single_channel_for_scan(struct iwl_priv *priv,
  590. struct ieee80211_vif *vif,
  591. enum ieee80211_band band,
  592. struct iwl_scan_channel *scan_ch)
  593. {
  594. const struct ieee80211_supported_band *sband;
  595. u16 passive_dwell = 0;
  596. u16 active_dwell = 0;
  597. int added = 0;
  598. u16 channel = 0;
  599. sband = iwl_get_hw_mode(priv, band);
  600. if (!sband) {
  601. IWL_ERR(priv, "invalid band\n");
  602. return added;
  603. }
  604. active_dwell = iwl_legacy_get_active_dwell_time(priv, band, 0);
  605. passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
  606. if (passive_dwell <= active_dwell)
  607. passive_dwell = active_dwell + 1;
  608. channel = iwl_legacy_get_single_channel_number(priv, band);
  609. if (channel) {
  610. scan_ch->channel = cpu_to_le16(channel);
  611. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  612. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  613. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  614. /* Set txpower levels to defaults */
  615. scan_ch->dsp_atten = 110;
  616. if (band == IEEE80211_BAND_5GHZ)
  617. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  618. else
  619. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  620. added++;
  621. } else
  622. IWL_ERR(priv, "no valid channel found\n");
  623. return added;
  624. }
  625. static int iwl4965_get_channels_for_scan(struct iwl_priv *priv,
  626. struct ieee80211_vif *vif,
  627. enum ieee80211_band band,
  628. u8 is_active, u8 n_probes,
  629. struct iwl_scan_channel *scan_ch)
  630. {
  631. struct ieee80211_channel *chan;
  632. const struct ieee80211_supported_band *sband;
  633. const struct iwl_channel_info *ch_info;
  634. u16 passive_dwell = 0;
  635. u16 active_dwell = 0;
  636. int added, i;
  637. u16 channel;
  638. sband = iwl_get_hw_mode(priv, band);
  639. if (!sband)
  640. return 0;
  641. active_dwell = iwl_legacy_get_active_dwell_time(priv, band, n_probes);
  642. passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
  643. if (passive_dwell <= active_dwell)
  644. passive_dwell = active_dwell + 1;
  645. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  646. chan = priv->scan_request->channels[i];
  647. if (chan->band != band)
  648. continue;
  649. channel = chan->hw_value;
  650. scan_ch->channel = cpu_to_le16(channel);
  651. ch_info = iwl_legacy_get_channel_info(priv, band, channel);
  652. if (!iwl_legacy_is_channel_valid(ch_info)) {
  653. IWL_DEBUG_SCAN(priv,
  654. "Channel %d is INVALID for this band.\n",
  655. channel);
  656. continue;
  657. }
  658. if (!is_active || iwl_legacy_is_channel_passive(ch_info) ||
  659. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
  660. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  661. else
  662. scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
  663. if (n_probes)
  664. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  665. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  666. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  667. /* Set txpower levels to defaults */
  668. scan_ch->dsp_atten = 110;
  669. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  670. * power level:
  671. * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
  672. */
  673. if (band == IEEE80211_BAND_5GHZ)
  674. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  675. else
  676. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  677. IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
  678. channel, le32_to_cpu(scan_ch->type),
  679. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  680. "ACTIVE" : "PASSIVE",
  681. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  682. active_dwell : passive_dwell);
  683. scan_ch++;
  684. added++;
  685. }
  686. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  687. return added;
  688. }
  689. int iwl4965_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  690. {
  691. struct iwl_host_cmd cmd = {
  692. .id = REPLY_SCAN_CMD,
  693. .len = sizeof(struct iwl_scan_cmd),
  694. .flags = CMD_SIZE_HUGE,
  695. };
  696. struct iwl_scan_cmd *scan;
  697. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  698. u32 rate_flags = 0;
  699. u16 cmd_len;
  700. u16 rx_chain = 0;
  701. enum ieee80211_band band;
  702. u8 n_probes = 0;
  703. u8 rx_ant = priv->hw_params.valid_rx_ant;
  704. u8 rate;
  705. bool is_active = false;
  706. int chan_mod;
  707. u8 active_chains;
  708. u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
  709. int ret;
  710. lockdep_assert_held(&priv->mutex);
  711. if (vif)
  712. ctx = iwl_legacy_rxon_ctx_from_vif(vif);
  713. if (!priv->scan_cmd) {
  714. priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
  715. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  716. if (!priv->scan_cmd) {
  717. IWL_DEBUG_SCAN(priv,
  718. "fail to allocate memory for scan\n");
  719. return -ENOMEM;
  720. }
  721. }
  722. scan = priv->scan_cmd;
  723. memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
  724. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  725. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  726. if (iwl_legacy_is_any_associated(priv)) {
  727. u16 interval = 0;
  728. u32 extra;
  729. u32 suspend_time = 100;
  730. u32 scan_suspend_time = 100;
  731. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  732. if (priv->is_internal_short_scan)
  733. interval = 0;
  734. else
  735. interval = vif->bss_conf.beacon_int;
  736. scan->suspend_time = 0;
  737. scan->max_out_time = cpu_to_le32(200 * 1024);
  738. if (!interval)
  739. interval = suspend_time;
  740. extra = (suspend_time / interval) << 22;
  741. scan_suspend_time = (extra |
  742. ((suspend_time % interval) * 1024));
  743. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  744. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  745. scan_suspend_time, interval);
  746. }
  747. if (priv->is_internal_short_scan) {
  748. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  749. } else if (priv->scan_request->n_ssids) {
  750. int i, p = 0;
  751. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  752. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  753. /* always does wildcard anyway */
  754. if (!priv->scan_request->ssids[i].ssid_len)
  755. continue;
  756. scan->direct_scan[p].id = WLAN_EID_SSID;
  757. scan->direct_scan[p].len =
  758. priv->scan_request->ssids[i].ssid_len;
  759. memcpy(scan->direct_scan[p].ssid,
  760. priv->scan_request->ssids[i].ssid,
  761. priv->scan_request->ssids[i].ssid_len);
  762. n_probes++;
  763. p++;
  764. }
  765. is_active = true;
  766. } else
  767. IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
  768. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  769. scan->tx_cmd.sta_id = ctx->bcast_sta_id;
  770. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  771. switch (priv->scan_band) {
  772. case IEEE80211_BAND_2GHZ:
  773. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  774. chan_mod = le32_to_cpu(
  775. priv->contexts[IWL_RXON_CTX_BSS].active.flags &
  776. RXON_FLG_CHANNEL_MODE_MSK)
  777. >> RXON_FLG_CHANNEL_MODE_POS;
  778. if (chan_mod == CHANNEL_MODE_PURE_40) {
  779. rate = IWL_RATE_6M_PLCP;
  780. } else {
  781. rate = IWL_RATE_1M_PLCP;
  782. rate_flags = RATE_MCS_CCK_MSK;
  783. }
  784. break;
  785. case IEEE80211_BAND_5GHZ:
  786. rate = IWL_RATE_6M_PLCP;
  787. break;
  788. default:
  789. IWL_WARN(priv, "Invalid scan band\n");
  790. return -EIO;
  791. }
  792. /*
  793. * If active scanning is requested but a certain channel is
  794. * marked passive, we can do active scanning if we detect
  795. * transmissions.
  796. *
  797. * There is an issue with some firmware versions that triggers
  798. * a sysassert on a "good CRC threshold" of zero (== disabled),
  799. * on a radar channel even though this means that we should NOT
  800. * send probes.
  801. *
  802. * The "good CRC threshold" is the number of frames that we
  803. * need to receive during our dwell time on a channel before
  804. * sending out probes -- setting this to a huge value will
  805. * mean we never reach it, but at the same time work around
  806. * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
  807. * here instead of IWL_GOOD_CRC_TH_DISABLED.
  808. */
  809. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  810. IWL_GOOD_CRC_TH_NEVER;
  811. band = priv->scan_band;
  812. if (priv->cfg->scan_rx_antennas[band])
  813. rx_ant = priv->cfg->scan_rx_antennas[band];
  814. priv->scan_tx_ant[band] = iwl4965_toggle_tx_ant(priv,
  815. priv->scan_tx_ant[band],
  816. scan_tx_antennas);
  817. rate_flags |= iwl4965_ant_idx_to_flags(priv->scan_tx_ant[band]);
  818. scan->tx_cmd.rate_n_flags = iwl4965_hw_set_rate_n_flags(rate, rate_flags);
  819. /* In power save mode use one chain, otherwise use all chains */
  820. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  821. /* rx_ant has been set to all valid chains previously */
  822. active_chains = rx_ant &
  823. ((u8)(priv->chain_noise_data.active_chains));
  824. if (!active_chains)
  825. active_chains = rx_ant;
  826. IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
  827. priv->chain_noise_data.active_chains);
  828. rx_ant = iwl4965_first_antenna(active_chains);
  829. }
  830. /* MIMO is not used here, but value is required */
  831. rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
  832. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  833. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
  834. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  835. scan->rx_chain = cpu_to_le16(rx_chain);
  836. if (!priv->is_internal_short_scan) {
  837. cmd_len = iwl_legacy_fill_probe_req(priv,
  838. (struct ieee80211_mgmt *)scan->data,
  839. vif->addr,
  840. priv->scan_request->ie,
  841. priv->scan_request->ie_len,
  842. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  843. } else {
  844. /* use bcast addr, will not be transmitted but must be valid */
  845. cmd_len = iwl_legacy_fill_probe_req(priv,
  846. (struct ieee80211_mgmt *)scan->data,
  847. iwlegacy_bcast_addr, NULL, 0,
  848. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  849. }
  850. scan->tx_cmd.len = cpu_to_le16(cmd_len);
  851. scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
  852. RXON_FILTER_BCON_AWARE_MSK);
  853. if (priv->is_internal_short_scan) {
  854. scan->channel_count =
  855. iwl4965_get_single_channel_for_scan(priv, vif, band,
  856. (void *)&scan->data[le16_to_cpu(
  857. scan->tx_cmd.len)]);
  858. } else {
  859. scan->channel_count =
  860. iwl4965_get_channels_for_scan(priv, vif, band,
  861. is_active, n_probes,
  862. (void *)&scan->data[le16_to_cpu(
  863. scan->tx_cmd.len)]);
  864. }
  865. if (scan->channel_count == 0) {
  866. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  867. return -EIO;
  868. }
  869. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  870. scan->channel_count * sizeof(struct iwl_scan_channel);
  871. cmd.data = scan;
  872. scan->len = cpu_to_le16(cmd.len);
  873. set_bit(STATUS_SCAN_HW, &priv->status);
  874. ret = iwl_legacy_send_cmd_sync(priv, &cmd);
  875. if (ret)
  876. clear_bit(STATUS_SCAN_HW, &priv->status);
  877. return ret;
  878. }
  879. int iwl4965_manage_ibss_station(struct iwl_priv *priv,
  880. struct ieee80211_vif *vif, bool add)
  881. {
  882. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  883. if (add)
  884. return iwl4965_add_bssid_station(priv, vif_priv->ctx,
  885. vif->bss_conf.bssid,
  886. &vif_priv->ibss_bssid_sta_id);
  887. return iwl_legacy_remove_station(priv, vif_priv->ibss_bssid_sta_id,
  888. vif->bss_conf.bssid);
  889. }
  890. void iwl4965_free_tfds_in_queue(struct iwl_priv *priv,
  891. int sta_id, int tid, int freed)
  892. {
  893. lockdep_assert_held(&priv->sta_lock);
  894. if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
  895. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  896. else {
  897. IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
  898. priv->stations[sta_id].tid[tid].tfds_in_queue,
  899. freed);
  900. priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
  901. }
  902. }
  903. #define IWL_TX_QUEUE_MSK 0xfffff
  904. static bool iwl4965_is_single_rx_stream(struct iwl_priv *priv)
  905. {
  906. return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
  907. priv->current_ht_config.single_chain_sufficient;
  908. }
  909. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  910. #define IWL_NUM_RX_CHAINS_SINGLE 2
  911. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  912. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  913. /*
  914. * Determine how many receiver/antenna chains to use.
  915. *
  916. * More provides better reception via diversity. Fewer saves power
  917. * at the expense of throughput, but only when not in powersave to
  918. * start with.
  919. *
  920. * MIMO (dual stream) requires at least 2, but works better with 3.
  921. * This does not determine *which* chains to use, just how many.
  922. */
  923. static int iwl4965_get_active_rx_chain_count(struct iwl_priv *priv)
  924. {
  925. /* # of Rx chains to use when expecting MIMO. */
  926. if (iwl4965_is_single_rx_stream(priv))
  927. return IWL_NUM_RX_CHAINS_SINGLE;
  928. else
  929. return IWL_NUM_RX_CHAINS_MULTIPLE;
  930. }
  931. /*
  932. * When we are in power saving mode, unless device support spatial
  933. * multiplexing power save, use the active count for rx chain count.
  934. */
  935. static int
  936. iwl4965_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  937. {
  938. /* # Rx chains when idling, depending on SMPS mode */
  939. switch (priv->current_ht_config.smps) {
  940. case IEEE80211_SMPS_STATIC:
  941. case IEEE80211_SMPS_DYNAMIC:
  942. return IWL_NUM_IDLE_CHAINS_SINGLE;
  943. case IEEE80211_SMPS_OFF:
  944. return active_cnt;
  945. default:
  946. WARN(1, "invalid SMPS mode %d",
  947. priv->current_ht_config.smps);
  948. return active_cnt;
  949. }
  950. }
  951. /* up to 4 chains */
  952. static u8 iwl4965_count_chain_bitmap(u32 chain_bitmap)
  953. {
  954. u8 res;
  955. res = (chain_bitmap & BIT(0)) >> 0;
  956. res += (chain_bitmap & BIT(1)) >> 1;
  957. res += (chain_bitmap & BIT(2)) >> 2;
  958. res += (chain_bitmap & BIT(3)) >> 3;
  959. return res;
  960. }
  961. /**
  962. * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  963. *
  964. * Selects how many and which Rx receivers/antennas/chains to use.
  965. * This should not be used for scan command ... it puts data in wrong place.
  966. */
  967. void iwl4965_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
  968. {
  969. bool is_single = iwl4965_is_single_rx_stream(priv);
  970. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  971. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  972. u32 active_chains;
  973. u16 rx_chain;
  974. /* Tell uCode which antennas are actually connected.
  975. * Before first association, we assume all antennas are connected.
  976. * Just after first association, iwl4965_chain_noise_calibration()
  977. * checks which antennas actually *are* connected. */
  978. if (priv->chain_noise_data.active_chains)
  979. active_chains = priv->chain_noise_data.active_chains;
  980. else
  981. active_chains = priv->hw_params.valid_rx_ant;
  982. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  983. /* How many receivers should we use? */
  984. active_rx_cnt = iwl4965_get_active_rx_chain_count(priv);
  985. idle_rx_cnt = iwl4965_get_idle_rx_chain_count(priv, active_rx_cnt);
  986. /* correct rx chain count according hw settings
  987. * and chain noise calibration
  988. */
  989. valid_rx_cnt = iwl4965_count_chain_bitmap(active_chains);
  990. if (valid_rx_cnt < active_rx_cnt)
  991. active_rx_cnt = valid_rx_cnt;
  992. if (valid_rx_cnt < idle_rx_cnt)
  993. idle_rx_cnt = valid_rx_cnt;
  994. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  995. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  996. ctx->staging.rx_chain = cpu_to_le16(rx_chain);
  997. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  998. ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  999. else
  1000. ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  1001. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  1002. ctx->staging.rx_chain,
  1003. active_rx_cnt, idle_rx_cnt);
  1004. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  1005. active_rx_cnt < idle_rx_cnt);
  1006. }
  1007. u8 iwl4965_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
  1008. {
  1009. int i;
  1010. u8 ind = ant;
  1011. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  1012. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  1013. if (valid & BIT(ind))
  1014. return ind;
  1015. }
  1016. return ant;
  1017. }
  1018. static const char *iwl4965_get_fh_string(int cmd)
  1019. {
  1020. switch (cmd) {
  1021. IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
  1022. IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
  1023. IWL_CMD(FH_RSCSR_CHNL0_WPTR);
  1024. IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
  1025. IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
  1026. IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
  1027. IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
  1028. IWL_CMD(FH_TSSR_TX_STATUS_REG);
  1029. IWL_CMD(FH_TSSR_TX_ERROR_REG);
  1030. default:
  1031. return "UNKNOWN";
  1032. }
  1033. }
  1034. int iwl4965_dump_fh(struct iwl_priv *priv, char **buf, bool display)
  1035. {
  1036. int i;
  1037. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1038. int pos = 0;
  1039. size_t bufsz = 0;
  1040. #endif
  1041. static const u32 fh_tbl[] = {
  1042. FH_RSCSR_CHNL0_STTS_WPTR_REG,
  1043. FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  1044. FH_RSCSR_CHNL0_WPTR,
  1045. FH_MEM_RCSR_CHNL0_CONFIG_REG,
  1046. FH_MEM_RSSR_SHARED_CTRL_REG,
  1047. FH_MEM_RSSR_RX_STATUS_REG,
  1048. FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
  1049. FH_TSSR_TX_STATUS_REG,
  1050. FH_TSSR_TX_ERROR_REG
  1051. };
  1052. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  1053. if (display) {
  1054. bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
  1055. *buf = kmalloc(bufsz, GFP_KERNEL);
  1056. if (!*buf)
  1057. return -ENOMEM;
  1058. pos += scnprintf(*buf + pos, bufsz - pos,
  1059. "FH register values:\n");
  1060. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  1061. pos += scnprintf(*buf + pos, bufsz - pos,
  1062. " %34s: 0X%08x\n",
  1063. iwl4965_get_fh_string(fh_tbl[i]),
  1064. iwl_legacy_read_direct32(priv, fh_tbl[i]));
  1065. }
  1066. return pos;
  1067. }
  1068. #endif
  1069. IWL_ERR(priv, "FH register values:\n");
  1070. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  1071. IWL_ERR(priv, " %34s: 0X%08x\n",
  1072. iwl4965_get_fh_string(fh_tbl[i]),
  1073. iwl_legacy_read_direct32(priv, fh_tbl[i]));
  1074. }
  1075. return 0;
  1076. }