r82600_edac.c 12 KB

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  1. /*
  2. * Radisys 82600 Embedded chipset Memory Controller kernel module
  3. * (C) 2005 EADS Astrium
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
  8. * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
  9. *
  10. * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11. *
  12. * Written with reference to 82600 High Integration Dual PCI System
  13. * Controller Data Book:
  14. * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15. * references to this document given in []
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/pci.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/edac.h>
  22. #include "edac_core.h"
  23. #define R82600_REVISION " Ver: 2.0.2"
  24. #define EDAC_MOD_STR "r82600_edac"
  25. #define r82600_printk(level, fmt, arg...) \
  26. edac_printk(level, "r82600", fmt, ##arg)
  27. #define r82600_mc_printk(mci, level, fmt, arg...) \
  28. edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  29. /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  30. * supports up to four banks of memory. The four banks can support a mix of
  31. * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  32. * each of which can be any size from 16MB to 512MB. Both registered (control
  33. * signals buffered) and unbuffered DIMM types are supported. Mixing of
  34. * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  35. * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  36. * the CPU bus, 66MHz, 100MHz or 133MHz."
  37. */
  38. #define R82600_NR_CSROWS 4
  39. #define R82600_NR_CHANS 1
  40. #define R82600_NR_DIMMS 4
  41. #define R82600_BRIDGE_ID 0x8200
  42. /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  43. #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
  44. * all bits are R/W
  45. *
  46. * 7 SDRAM ISA Hole Enable
  47. * 6 Flash Page Mode Enable
  48. * 5 ECC Enable: 1=ECC 0=noECC
  49. * 4 DRAM DIMM Type: 1=
  50. * 3 BIOS Alias Disable
  51. * 2 SDRAM BIOS Flash Write Enable
  52. * 1:0 SDRAM Refresh Rate: 00=Disabled
  53. * 01=7.8usec (256Mbit SDRAMs)
  54. * 10=15.6us 11=125usec
  55. */
  56. #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
  57. * More SDRAM related control bits
  58. * all bits are R/W
  59. *
  60. * 15:8 Reserved.
  61. *
  62. * 7:5 Special SDRAM Mode Select
  63. *
  64. * 4 Force ECC
  65. *
  66. * 1=Drive ECC bits to 0 during
  67. * write cycles (i.e. ECC test mode)
  68. *
  69. * 0=Normal ECC functioning
  70. *
  71. * 3 Enhanced Paging Enable
  72. *
  73. * 2 CAS# Latency 0=3clks 1=2clks
  74. *
  75. * 1 RAS# to CAS# Delay 0=3 1=2
  76. *
  77. * 0 RAS# Precharge 0=3 1=2
  78. */
  79. #define R82600_EAP 0x80 /* ECC Error Address Pointer Register
  80. *
  81. * 31 Disable Hardware Scrubbing (RW)
  82. * 0=Scrub on corrected read
  83. * 1=Don't scrub on corrected read
  84. *
  85. * 30:12 Error Address Pointer (RO)
  86. * Upper 19 bits of error address
  87. *
  88. * 11:4 Syndrome Bits (RO)
  89. *
  90. * 3 BSERR# on multibit error (RW)
  91. * 1=enable 0=disable
  92. *
  93. * 2 NMI on Single Bit Eror (RW)
  94. * 1=NMI triggered by SBE n.b. other
  95. * prerequeists
  96. * 0=NMI not triggered
  97. *
  98. * 1 MBE (R/WC)
  99. * read 1=MBE at EAP (see above)
  100. * read 0=no MBE, or SBE occurred first
  101. * write 1=Clear MBE status (must also
  102. * clear SBE)
  103. * write 0=NOP
  104. *
  105. * 1 SBE (R/WC)
  106. * read 1=SBE at EAP (see above)
  107. * read 0=no SBE, or MBE occurred first
  108. * write 1=Clear SBE status (must also
  109. * clear MBE)
  110. * write 0=NOP
  111. */
  112. #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
  113. * Registers
  114. *
  115. * 7:0 Address lines 30:24 - upper limit of
  116. * each row [p57]
  117. */
  118. struct r82600_error_info {
  119. u32 eapr;
  120. };
  121. static unsigned int disable_hardware_scrub;
  122. static struct edac_pci_ctl_info *r82600_pci;
  123. static void r82600_get_error_info(struct mem_ctl_info *mci,
  124. struct r82600_error_info *info)
  125. {
  126. struct pci_dev *pdev;
  127. pdev = to_pci_dev(mci->dev);
  128. pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
  129. if (info->eapr & BIT(0))
  130. /* Clear error to allow next error to be reported [p.62] */
  131. pci_write_bits32(pdev, R82600_EAP,
  132. ((u32) BIT(0) & (u32) BIT(1)),
  133. ((u32) BIT(0) & (u32) BIT(1)));
  134. if (info->eapr & BIT(1))
  135. /* Clear error to allow next error to be reported [p.62] */
  136. pci_write_bits32(pdev, R82600_EAP,
  137. ((u32) BIT(0) & (u32) BIT(1)),
  138. ((u32) BIT(0) & (u32) BIT(1)));
  139. }
  140. static int r82600_process_error_info(struct mem_ctl_info *mci,
  141. struct r82600_error_info *info,
  142. int handle_errors)
  143. {
  144. int error_found;
  145. u32 eapaddr, page;
  146. u32 syndrome;
  147. error_found = 0;
  148. /* bits 30:12 store the upper 19 bits of the 32 bit error address */
  149. eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
  150. /* Syndrome in bits 11:4 [p.62] */
  151. syndrome = (info->eapr >> 4) & 0xFF;
  152. /* the R82600 reports at less than page *
  153. * granularity (upper 19 bits only) */
  154. page = eapaddr >> PAGE_SHIFT;
  155. if (info->eapr & BIT(0)) { /* CE? */
  156. error_found = 1;
  157. if (handle_errors)
  158. edac_mc_handle_ce(mci, page, 0, /* not avail */
  159. syndrome,
  160. edac_mc_find_csrow_by_page(mci, page),
  161. 0, mci->ctl_name);
  162. }
  163. if (info->eapr & BIT(1)) { /* UE? */
  164. error_found = 1;
  165. if (handle_errors)
  166. /* 82600 doesn't give enough info */
  167. edac_mc_handle_ue(mci, page, 0,
  168. edac_mc_find_csrow_by_page(mci, page),
  169. mci->ctl_name);
  170. }
  171. return error_found;
  172. }
  173. static void r82600_check(struct mem_ctl_info *mci)
  174. {
  175. struct r82600_error_info info;
  176. debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
  177. r82600_get_error_info(mci, &info);
  178. r82600_process_error_info(mci, &info, 1);
  179. }
  180. static inline int ecc_enabled(u8 dramcr)
  181. {
  182. return dramcr & BIT(5);
  183. }
  184. static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
  185. u8 dramcr)
  186. {
  187. struct csrow_info *csrow;
  188. int index;
  189. u8 drbar; /* SDRAM Row Boundary Address Register */
  190. u32 row_high_limit, row_high_limit_last;
  191. u32 reg_sdram, ecc_on, row_base;
  192. ecc_on = ecc_enabled(dramcr);
  193. reg_sdram = dramcr & BIT(4);
  194. row_high_limit_last = 0;
  195. for (index = 0; index < mci->nr_csrows; index++) {
  196. csrow = &mci->csrows[index];
  197. /* find the DRAM Chip Select Base address and mask */
  198. pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
  199. debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
  200. row_high_limit = ((u32) drbar << 24);
  201. /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
  202. debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n",
  203. __func__, index, row_high_limit, row_high_limit_last);
  204. /* Empty row [p.57] */
  205. if (row_high_limit == row_high_limit_last)
  206. continue;
  207. row_base = row_high_limit_last;
  208. csrow->first_page = row_base >> PAGE_SHIFT;
  209. csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
  210. csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
  211. /* Error address is top 19 bits - so granularity is *
  212. * 14 bits */
  213. csrow->grain = 1 << 14;
  214. csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
  215. /* FIXME - check that this is unknowable with this chipset */
  216. csrow->dtype = DEV_UNKNOWN;
  217. /* Mode is global on 82600 */
  218. csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
  219. row_high_limit_last = row_high_limit;
  220. }
  221. }
  222. static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
  223. {
  224. struct mem_ctl_info *mci;
  225. u8 dramcr;
  226. u32 eapr;
  227. u32 scrub_disabled;
  228. u32 sdram_refresh_rate;
  229. struct r82600_error_info discard;
  230. debugf0("%s()\n", __func__);
  231. pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
  232. pci_read_config_dword(pdev, R82600_EAP, &eapr);
  233. scrub_disabled = eapr & BIT(31);
  234. sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
  235. debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
  236. sdram_refresh_rate);
  237. debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
  238. mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS, 0);
  239. if (mci == NULL)
  240. return -ENOMEM;
  241. debugf0("%s(): mci = %p\n", __func__, mci);
  242. mci->dev = &pdev->dev;
  243. mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
  244. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  245. /* FIXME try to work out if the chip leads have been used for COM2
  246. * instead on this board? [MA6?] MAYBE:
  247. */
  248. /* On the R82600, the pins for memory bits 72:65 - i.e. the *
  249. * EC bits are shared with the pins for COM2 (!), so if COM2 *
  250. * is enabled, we assume COM2 is wired up, and thus no EDAC *
  251. * is possible. */
  252. mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  253. if (ecc_enabled(dramcr)) {
  254. if (scrub_disabled)
  255. debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
  256. "%#0x\n", __func__, mci, eapr);
  257. } else
  258. mci->edac_cap = EDAC_FLAG_NONE;
  259. mci->mod_name = EDAC_MOD_STR;
  260. mci->mod_ver = R82600_REVISION;
  261. mci->ctl_name = "R82600";
  262. mci->dev_name = pci_name(pdev);
  263. mci->edac_check = r82600_check;
  264. mci->ctl_page_to_phys = NULL;
  265. r82600_init_csrows(mci, pdev, dramcr);
  266. r82600_get_error_info(mci, &discard); /* clear counters */
  267. /* Here we assume that we will never see multiple instances of this
  268. * type of memory controller. The ID is therefore hardcoded to 0.
  269. */
  270. if (edac_mc_add_mc(mci)) {
  271. debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
  272. goto fail;
  273. }
  274. /* get this far and it's successful */
  275. if (disable_hardware_scrub) {
  276. debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
  277. __func__);
  278. pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
  279. }
  280. /* allocating generic PCI control info */
  281. r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  282. if (!r82600_pci) {
  283. printk(KERN_WARNING
  284. "%s(): Unable to create PCI control\n",
  285. __func__);
  286. printk(KERN_WARNING
  287. "%s(): PCI error report via EDAC not setup\n",
  288. __func__);
  289. }
  290. debugf3("%s(): success\n", __func__);
  291. return 0;
  292. fail:
  293. edac_mc_free(mci);
  294. return -ENODEV;
  295. }
  296. /* returns count (>= 0), or negative on error */
  297. static int __devinit r82600_init_one(struct pci_dev *pdev,
  298. const struct pci_device_id *ent)
  299. {
  300. debugf0("%s()\n", __func__);
  301. /* don't need to call pci_enable_device() */
  302. return r82600_probe1(pdev, ent->driver_data);
  303. }
  304. static void __devexit r82600_remove_one(struct pci_dev *pdev)
  305. {
  306. struct mem_ctl_info *mci;
  307. debugf0("%s()\n", __func__);
  308. if (r82600_pci)
  309. edac_pci_release_generic_ctl(r82600_pci);
  310. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  311. return;
  312. edac_mc_free(mci);
  313. }
  314. static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
  315. {
  316. PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
  317. },
  318. {
  319. 0,
  320. } /* 0 terminated list. */
  321. };
  322. MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
  323. static struct pci_driver r82600_driver = {
  324. .name = EDAC_MOD_STR,
  325. .probe = r82600_init_one,
  326. .remove = __devexit_p(r82600_remove_one),
  327. .id_table = r82600_pci_tbl,
  328. };
  329. static int __init r82600_init(void)
  330. {
  331. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  332. opstate_init();
  333. return pci_register_driver(&r82600_driver);
  334. }
  335. static void __exit r82600_exit(void)
  336. {
  337. pci_unregister_driver(&r82600_driver);
  338. }
  339. module_init(r82600_init);
  340. module_exit(r82600_exit);
  341. MODULE_LICENSE("GPL");
  342. MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
  343. "on behalf of EADS Astrium");
  344. MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
  345. module_param(disable_hardware_scrub, bool, 0644);
  346. MODULE_PARM_DESC(disable_hardware_scrub,
  347. "If set, disable the chipset's automatic scrub for CEs");
  348. module_param(edac_op_state, int, 0444);
  349. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");