tpm_nsc.c 10 KB

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  1. /*
  2. * Copyright (C) 2004 IBM Corporation
  3. *
  4. * Authors:
  5. * Leendert van Doorn <leendert@watson.ibm.com>
  6. * Dave Safford <safford@watson.ibm.com>
  7. * Reiner Sailer <sailer@watson.ibm.com>
  8. * Kylene Hall <kjhall@us.ibm.com>
  9. *
  10. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  11. *
  12. * Device driver for TCG/TCPA TPM (trusted platform module).
  13. * Specifications at www.trustedcomputinggroup.org
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation, version 2 of the
  18. * License.
  19. *
  20. */
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include "tpm.h"
  24. /* National definitions */
  25. enum tpm_nsc_addr{
  26. TPM_NSC_IRQ = 0x07,
  27. TPM_NSC_BASE0_HI = 0x60,
  28. TPM_NSC_BASE0_LO = 0x61,
  29. TPM_NSC_BASE1_HI = 0x62,
  30. TPM_NSC_BASE1_LO = 0x63
  31. };
  32. enum tpm_nsc_index {
  33. NSC_LDN_INDEX = 0x07,
  34. NSC_SID_INDEX = 0x20,
  35. NSC_LDC_INDEX = 0x30,
  36. NSC_DIO_INDEX = 0x60,
  37. NSC_CIO_INDEX = 0x62,
  38. NSC_IRQ_INDEX = 0x70,
  39. NSC_ITS_INDEX = 0x71
  40. };
  41. enum tpm_nsc_status_loc {
  42. NSC_STATUS = 0x01,
  43. NSC_COMMAND = 0x01,
  44. NSC_DATA = 0x00
  45. };
  46. /* status bits */
  47. enum tpm_nsc_status {
  48. NSC_STATUS_OBF = 0x01, /* output buffer full */
  49. NSC_STATUS_IBF = 0x02, /* input buffer full */
  50. NSC_STATUS_F0 = 0x04, /* F0 */
  51. NSC_STATUS_A2 = 0x08, /* A2 */
  52. NSC_STATUS_RDY = 0x10, /* ready to receive command */
  53. NSC_STATUS_IBR = 0x20 /* ready to receive data */
  54. };
  55. /* command bits */
  56. enum tpm_nsc_cmd_mode {
  57. NSC_COMMAND_NORMAL = 0x01, /* normal mode */
  58. NSC_COMMAND_EOC = 0x03,
  59. NSC_COMMAND_CANCEL = 0x22
  60. };
  61. /*
  62. * Wait for a certain status to appear
  63. */
  64. static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
  65. {
  66. unsigned long stop;
  67. /* status immediately available check */
  68. *data = inb(chip->vendor.base + NSC_STATUS);
  69. if ((*data & mask) == val)
  70. return 0;
  71. /* wait for status */
  72. stop = jiffies + 10 * HZ;
  73. do {
  74. msleep(TPM_TIMEOUT);
  75. *data = inb(chip->vendor.base + 1);
  76. if ((*data & mask) == val)
  77. return 0;
  78. }
  79. while (time_before(jiffies, stop));
  80. return -EBUSY;
  81. }
  82. static int nsc_wait_for_ready(struct tpm_chip *chip)
  83. {
  84. int status;
  85. unsigned long stop;
  86. /* status immediately available check */
  87. status = inb(chip->vendor.base + NSC_STATUS);
  88. if (status & NSC_STATUS_OBF)
  89. status = inb(chip->vendor.base + NSC_DATA);
  90. if (status & NSC_STATUS_RDY)
  91. return 0;
  92. /* wait for status */
  93. stop = jiffies + 100;
  94. do {
  95. msleep(TPM_TIMEOUT);
  96. status = inb(chip->vendor.base + NSC_STATUS);
  97. if (status & NSC_STATUS_OBF)
  98. status = inb(chip->vendor.base + NSC_DATA);
  99. if (status & NSC_STATUS_RDY)
  100. return 0;
  101. }
  102. while (time_before(jiffies, stop));
  103. dev_info(chip->dev, "wait for ready failed\n");
  104. return -EBUSY;
  105. }
  106. static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
  107. {
  108. u8 *buffer = buf;
  109. u8 data, *p;
  110. u32 size;
  111. __be32 *native_size;
  112. if (count < 6)
  113. return -EIO;
  114. if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
  115. dev_err(chip->dev, "F0 timeout\n");
  116. return -EIO;
  117. }
  118. if ((data =
  119. inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
  120. dev_err(chip->dev, "not in normal mode (0x%x)\n",
  121. data);
  122. return -EIO;
  123. }
  124. /* read the whole packet */
  125. for (p = buffer; p < &buffer[count]; p++) {
  126. if (wait_for_stat
  127. (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
  128. dev_err(chip->dev,
  129. "OBF timeout (while reading data)\n");
  130. return -EIO;
  131. }
  132. if (data & NSC_STATUS_F0)
  133. break;
  134. *p = inb(chip->vendor.base + NSC_DATA);
  135. }
  136. if ((data & NSC_STATUS_F0) == 0 &&
  137. (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
  138. dev_err(chip->dev, "F0 not set\n");
  139. return -EIO;
  140. }
  141. if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
  142. dev_err(chip->dev,
  143. "expected end of command(0x%x)\n", data);
  144. return -EIO;
  145. }
  146. native_size = (__force __be32 *) (buf + 2);
  147. size = be32_to_cpu(*native_size);
  148. if (count < size)
  149. return -EIO;
  150. return size;
  151. }
  152. static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
  153. {
  154. u8 data;
  155. int i;
  156. /*
  157. * If we hit the chip with back to back commands it locks up
  158. * and never set IBF. Hitting it with this "hammer" seems to
  159. * fix it. Not sure why this is needed, we followed the flow
  160. * chart in the manual to the letter.
  161. */
  162. outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
  163. if (nsc_wait_for_ready(chip) != 0)
  164. return -EIO;
  165. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  166. dev_err(chip->dev, "IBF timeout\n");
  167. return -EIO;
  168. }
  169. outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
  170. if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
  171. dev_err(chip->dev, "IBR timeout\n");
  172. return -EIO;
  173. }
  174. for (i = 0; i < count; i++) {
  175. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  176. dev_err(chip->dev,
  177. "IBF timeout (while writing data)\n");
  178. return -EIO;
  179. }
  180. outb(buf[i], chip->vendor.base + NSC_DATA);
  181. }
  182. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  183. dev_err(chip->dev, "IBF timeout\n");
  184. return -EIO;
  185. }
  186. outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);
  187. return count;
  188. }
  189. static void tpm_nsc_cancel(struct tpm_chip *chip)
  190. {
  191. outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
  192. }
  193. static u8 tpm_nsc_status(struct tpm_chip *chip)
  194. {
  195. return inb(chip->vendor.base + NSC_STATUS);
  196. }
  197. static const struct file_operations nsc_ops = {
  198. .owner = THIS_MODULE,
  199. .llseek = no_llseek,
  200. .open = tpm_open,
  201. .read = tpm_read,
  202. .write = tpm_write,
  203. .release = tpm_release,
  204. };
  205. static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
  206. static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
  207. static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
  208. static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
  209. static struct attribute * nsc_attrs[] = {
  210. &dev_attr_pubek.attr,
  211. &dev_attr_pcrs.attr,
  212. &dev_attr_caps.attr,
  213. &dev_attr_cancel.attr,
  214. NULL,
  215. };
  216. static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
  217. static const struct tpm_vendor_specific tpm_nsc = {
  218. .recv = tpm_nsc_recv,
  219. .send = tpm_nsc_send,
  220. .cancel = tpm_nsc_cancel,
  221. .status = tpm_nsc_status,
  222. .req_complete_mask = NSC_STATUS_OBF,
  223. .req_complete_val = NSC_STATUS_OBF,
  224. .req_canceled = NSC_STATUS_RDY,
  225. .attr_group = &nsc_attr_grp,
  226. .miscdev = { .fops = &nsc_ops, },
  227. };
  228. static struct platform_device *pdev = NULL;
  229. static void tpm_nsc_remove(struct device *dev)
  230. {
  231. struct tpm_chip *chip = dev_get_drvdata(dev);
  232. if ( chip ) {
  233. release_region(chip->vendor.base, 2);
  234. tpm_remove_hardware(chip->dev);
  235. }
  236. }
  237. static int tpm_nsc_suspend(struct platform_device *dev, pm_message_t msg)
  238. {
  239. return tpm_pm_suspend(&dev->dev, msg);
  240. }
  241. static int tpm_nsc_resume(struct platform_device *dev)
  242. {
  243. return tpm_pm_resume(&dev->dev);
  244. }
  245. static struct platform_driver nsc_drv = {
  246. .suspend = tpm_nsc_suspend,
  247. .resume = tpm_nsc_resume,
  248. .driver = {
  249. .name = "tpm_nsc",
  250. .owner = THIS_MODULE,
  251. },
  252. };
  253. static int __init init_nsc(void)
  254. {
  255. int rc = 0;
  256. int lo, hi, err;
  257. int nscAddrBase = TPM_ADDR;
  258. struct tpm_chip *chip;
  259. unsigned long base;
  260. /* verify that it is a National part (SID) */
  261. if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
  262. nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
  263. (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
  264. if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
  265. return -ENODEV;
  266. }
  267. err = platform_driver_register(&nsc_drv);
  268. if (err)
  269. return err;
  270. hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
  271. lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
  272. base = (hi<<8) | lo;
  273. /* enable the DPM module */
  274. tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
  275. pdev = platform_device_alloc("tpm_nscl0", -1);
  276. if (!pdev) {
  277. rc = -ENOMEM;
  278. goto err_unreg_drv;
  279. }
  280. pdev->num_resources = 0;
  281. pdev->dev.driver = &nsc_drv.driver;
  282. pdev->dev.release = tpm_nsc_remove;
  283. if ((rc = platform_device_register(pdev)) < 0)
  284. goto err_free_dev;
  285. if (request_region(base, 2, "tpm_nsc0") == NULL ) {
  286. rc = -EBUSY;
  287. goto err_unreg_dev;
  288. }
  289. if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) {
  290. rc = -ENODEV;
  291. goto err_rel_reg;
  292. }
  293. dev_dbg(&pdev->dev, "NSC TPM detected\n");
  294. dev_dbg(&pdev->dev,
  295. "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
  296. tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
  297. tpm_read_index(nscAddrBase,0x27));
  298. dev_dbg(&pdev->dev,
  299. "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
  300. tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
  301. tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
  302. dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
  303. (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
  304. dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
  305. (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
  306. dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
  307. tpm_read_index(nscAddrBase,0x70));
  308. dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
  309. tpm_read_index(nscAddrBase,0x71));
  310. dev_dbg(&pdev->dev,
  311. "NSC DMA channel select0 0x%x, select1 0x%x\n",
  312. tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
  313. dev_dbg(&pdev->dev,
  314. "NSC Config "
  315. "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
  316. tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
  317. tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
  318. tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
  319. tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
  320. tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
  321. dev_info(&pdev->dev,
  322. "NSC TPM revision %d\n",
  323. tpm_read_index(nscAddrBase, 0x27) & 0x1F);
  324. chip->vendor.base = base;
  325. return 0;
  326. err_rel_reg:
  327. release_region(base, 2);
  328. err_unreg_dev:
  329. platform_device_unregister(pdev);
  330. err_free_dev:
  331. kfree(pdev);
  332. err_unreg_drv:
  333. platform_driver_unregister(&nsc_drv);
  334. return rc;
  335. }
  336. static void __exit cleanup_nsc(void)
  337. {
  338. if (pdev) {
  339. tpm_nsc_remove(&pdev->dev);
  340. platform_device_unregister(pdev);
  341. kfree(pdev);
  342. pdev = NULL;
  343. }
  344. platform_driver_unregister(&nsc_drv);
  345. }
  346. module_init(init_nsc);
  347. module_exit(cleanup_nsc);
  348. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  349. MODULE_DESCRIPTION("TPM Driver");
  350. MODULE_VERSION("2.0");
  351. MODULE_LICENSE("GPL");