sd_protocol.c 272 KB

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  1. #include <linux/clk.h>
  2. #include "sd_port.h"
  3. #include "sd_misc.h"
  4. #include "sd_protocol.h"
  5. //Global struct variable, to hold all card information need to operate card
  6. /*static SD_MMC_Card_Info_t _sd_mmc_info = {CARD_TYPE_NONE, //card_type
  7. CARD_TYPE_NONE_SDIO, //sdio_card_type
  8. CARD_INDENTIFICATION_MODE, //operation_mode
  9. SD_BUS_SINGLE, //bus_width
  10. SPEC_VERSION_10_101, //spec_v1.0
  11. SPEC_VERSION_10_12, //spec_v1.0-v1.2
  12. NORMAL_SPEED, //normal_speed
  13. {0}, //raw cid
  14. 0, //card_rca
  15. 0, //blk_len
  16. 0, //blk_nums
  17. SD_MMC_TIME_NAC_DEFAULT, //clks_nac
  18. 0, //function_no
  19. 3000, //clk_unit(default 3000ns)
  20. 0, //write_protected_flag
  21. 0, //inited_flag
  22. 0, //removed_flag
  23. 0, //init_retry
  24. 0, //single_blk_failed
  25. 0, //sdio_init_flag
  26. NULL, //sd_mmc_power
  27. NULL, //sd_mmc_get_ins
  28. NULL, //sd_get_wp
  29. NULL //sd_mmc_io_release
  30. };*/
  31. //SD_MMC_Card_Info_t *sd_mmc_info = &_sd_mmc_info;
  32. extern unsigned sdio_timeout_int_times;
  33. extern unsigned sdio_command_err;
  34. extern unsigned sdio_command_int_num;
  35. static char * sd_error_string[]={
  36. "SD_MMC_NO_ERROR",
  37. "SD_MMC_ERROR_OUT_OF_RANGE", //Bit 31
  38. "SD_MMC_ERROR_ADDRESS", //Bit 30
  39. "SD_MMC_ERROR_BLOCK_LEN", //Bit 29
  40. "SD_MMC_ERROR_ERASE_SEQ", //Bit 28
  41. "SD_MMC_ERROR_ERASE_PARAM", //Bit 27
  42. "SD_MMC_ERROR_WP_VIOLATION", //Bit 26
  43. "SD_ERROR_CARD_IS_LOCKED", //Bit 25
  44. "SD_ERROR_LOCK_UNLOCK_FAILED", //Bit 24
  45. "SD_MMC_ERROR_COM_CRC", //Bit 23
  46. "SD_MMC_ERROR_ILLEGAL_COMMAND", //Bit 22
  47. "SD_ERROR_CARD_ECC_FAILED", //Bit 21
  48. "SD_ERROR_CC", //Bit 20
  49. "SD_MMC_ERROR_GENERAL", //Bit 19
  50. "SD_ERROR_Reserved1", //Bit 18
  51. "SD_ERROR_Reserved2", //Bit 17
  52. "SD_MMC_ERROR_CID_CSD_OVERWRITE", //Bit 16
  53. "SD_ERROR_AKE_SEQ", //Bit 03
  54. "SD_MMC_ERROR_STATE_MISMATCH",
  55. "SD_MMC_ERROR_HEADER_MISMATCH",
  56. "SD_MMC_ERROR_DATA_CRC",
  57. "SD_MMC_ERROR_TIMEOUT",
  58. "SD_MMC_ERROR_DRIVER_FAILURE",
  59. "SD_MMC_ERROR_WRITE_PROTECTED",
  60. "SD_MMC_ERROR_NO_MEMORY",
  61. "SD_ERROR_SWITCH_FUNCTION_COMUNICATION",
  62. "SD_ERROR_NO_FUNCTION_SWITCH",
  63. "SD_MMC_ERROR_NO_CARD_INS",
  64. "SD_MMC_ERROR_READ_DATA_FAILED",
  65. "SD_SDIO_ERROR_NO_FUNCTION"
  66. };
  67. static unsigned char char_mode[4][3] = {{0x10, 0x01, 0},
  68. {0x20, 0x02, 0},
  69. {0x40, 0x04, 0},
  70. {0x80, 0x08, 0}};
  71. //All local function definitions, only used in this .C file
  72. char * sd_error_to_string(int errcode);
  73. void sd_delay_clocks_z(SD_MMC_Card_Info_t *sd_mmc_info, int num_clk);
  74. void sd_delay_clocks_h(SD_MMC_Card_Info_t *sd_mmc_info, int num_clk);
  75. void sd_clear_response(unsigned char * res_buf);
  76. int sd_write_cmd_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * data_buf);
  77. int sd_get_dat0_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * data_buf, unsigned short * crc16);
  78. int sd_get_response_length(SD_Response_Type_t res_type);
  79. int sd_read_response_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * res_buf);
  80. #ifdef SD_MMC_SW_CONTROL
  81. int sd_send_cmd_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned char cmd, unsigned long arg, SD_Response_Type_t res_type, unsigned char * res_buf);
  82. #endif
  83. #ifdef SD_MMC_HW_CONTROL
  84. int sd_send_cmd_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned char cmd, unsigned long arg, SD_Response_Type_t res_type, unsigned char * res_buf, unsigned char *data_buf, unsigned long data_cnt, int retry_flag);
  85. #endif
  86. int sd_check_response_r1(unsigned char cmd, SD_Response_R1_t * r1);
  87. int sd_check_response_r3(unsigned char cmd, SD_Response_R3_t * r3);
  88. int sd_check_response_r4(unsigned char cmd, SDIO_Response_R4_t * r4);
  89. int sd_check_response_r5(unsigned char cmd, SDIO_RW_CMD_Response_R5_t * r5);
  90. int sd_check_response_r6(unsigned char cmd, SD_Response_R6_t * r6);
  91. int sd_check_response_r7(unsigned char cmd, SD_Response_R7_t * r7);
  92. int sd_check_response_r2_cid(unsigned char cmd, SD_Response_R2_CID_t * r2_cid);
  93. int sd_check_response_r2_csd(unsigned char cmd, SD_Response_R2_CSD_t * r2_csd);
  94. int sd_check_response(unsigned char cmd, SD_Response_Type_t res_type, unsigned char * res_buf);
  95. int sd_hw_reset(SD_MMC_Card_Info_t *sd_mmc_info);
  96. int sd_sw_reset(SD_MMC_Card_Info_t *sd_mmc_info);
  97. int sd_voltage_validation(SD_MMC_Card_Info_t *sd_mmc_info);
  98. int sd_identify_process(SD_MMC_Card_Info_t *sd_mmc_info);
  99. int sd_mmc_switch_function(SD_MMC_Card_Info_t *sd_mmc_info);
  100. int sd_check_sdio_card_type(SD_MMC_Card_Info_t *sd_mmc_info);
  101. int sdio_data_transfer_abort(SD_MMC_Card_Info_t *sd_mmc_info, int function_no);
  102. int sdio_card_reset(SD_MMC_Card_Info_t *sd_mmc_info);
  103. void sd_mmc_set_input(SD_MMC_Card_Info_t *sd_mmc_info);
  104. //Read single block data from SD card
  105. int sd_read_single_block(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf);
  106. //Read multi block data from SD card
  107. int sd_read_multi_block(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf);
  108. //Write single block data to SD card
  109. int sd_write_single_block(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf);
  110. //Write multi block data to SD card
  111. int sd_write_multi_block(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf);
  112. //Read Operation Conditions Register
  113. int sd_read_reg_ocr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_OCR_t * ocr);
  114. //Read Card_Identification Register
  115. int sd_read_reg_cid(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_CID_t * cid);
  116. //Read Card-Specific Data Register
  117. int sd_read_reg_csd(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_CSD_t * csd);
  118. //Read Relative Card Address Register
  119. int sd_read_reg_rca(SD_MMC_Card_Info_t *sd_mmc_info, unsigned short * rca);
  120. //Read Driver Stage Register
  121. int sd_read_reg_dsr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_DSR_t * dsr);
  122. //Read SD CARD Configuration Register
  123. int sd_read_reg_scr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_SCR_t * scr);
  124. int sd_check_data_consistency(SD_MMC_Card_Info_t *sd_mmc_info);
  125. void sd_mmc_prepare_power(SD_MMC_Card_Info_t *sd_mmc_info);
  126. void sd_mmc_io_config(SD_MMC_Card_Info_t *sd_mmc_info);
  127. int sd_mmc_staff_init(SD_MMC_Card_Info_t *sd_mmc_info);
  128. int sd_mmc_cmd_test(SD_MMC_Card_Info_t *sd_mmc_info);
  129. int sd_mmc_check_wp(SD_MMC_Card_Info_t *sd_mmc_info);
  130. //Return the string buf address of specific errcode
  131. char * sd_error_to_string(int errcode)
  132. {
  133. return sd_error_string[errcode];
  134. }
  135. //Set clock delay, Z-bit is driven to (respectively kept) HIGH by the pull-up resistors RCMD respectively RDAT.
  136. void sd_delay_clocks_z(SD_MMC_Card_Info_t *sd_mmc_info, int num_clk)
  137. {
  138. int i;
  139. sd_set_cmd_input();
  140. if(sd_mmc_info->operation_mode == CARD_INDENTIFICATION_MODE)
  141. {
  142. for(i = 0; i < num_clk; i++)
  143. {
  144. sd_clk_identify_low();
  145. sd_clk_identify_high();
  146. }
  147. }
  148. else // Tranfer mode
  149. {
  150. for(i = 0; i < num_clk; i++)
  151. {
  152. sd_clk_transfer_low();
  153. sd_clk_transfer_high();
  154. }
  155. }
  156. }
  157. //Set clock delay, P-bit is actively driven to HIGH by the card respectively host output driver.
  158. void sd_delay_clocks_h(SD_MMC_Card_Info_t *sd_mmc_info, int num_clk)
  159. {
  160. int i;
  161. sd_set_cmd_output();
  162. sd_set_cmd_value(1);
  163. if(sd_mmc_info->operation_mode == CARD_INDENTIFICATION_MODE)
  164. {
  165. for(i = 0; i < num_clk; i++)
  166. {
  167. sd_clk_identify_low();
  168. sd_clk_identify_high();
  169. }
  170. }
  171. else // Tranfer mode
  172. {
  173. for(i = 0; i < num_clk; i++)
  174. {
  175. sd_clk_transfer_low();
  176. sd_clk_transfer_high();
  177. }
  178. }
  179. }
  180. //Clear response data buffer
  181. void sd_clear_response(unsigned char * res_buf)
  182. {
  183. int i;
  184. if(res_buf == NULL)
  185. return;
  186. for(i = 0; i < MAX_RESPONSE_BYTES; i++)
  187. res_buf[i]=0;
  188. }
  189. //Put data bytes to cmd line
  190. int sd_write_cmd_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * data_buf)
  191. {
  192. unsigned long data_cnt,data;
  193. int i;
  194. sd_set_cmd_output();
  195. if(sd_mmc_info->operation_mode == CARD_INDENTIFICATION_MODE)
  196. {
  197. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  198. {
  199. for(i=7; i>=0; i--)
  200. {
  201. sd_clk_identify_low();
  202. data = (*data_buf >> i) & 0x01;
  203. sd_set_cmd_value(data);
  204. sd_clk_identify_high();
  205. }
  206. data_buf++;
  207. }
  208. }
  209. else // Tranfer mode
  210. {
  211. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  212. {
  213. for(i=7; i>=0; i--)
  214. {
  215. sd_clk_transfer_low();
  216. data = (*data_buf >> i) & 0x01;
  217. sd_set_cmd_value(data);
  218. sd_clk_transfer_high();
  219. }
  220. data_buf++;
  221. }
  222. }
  223. return SD_MMC_NO_ERROR;
  224. }
  225. //Get data bytes from data0 line
  226. int sd_get_dat0_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * data_buf, unsigned short * crc16)
  227. {
  228. unsigned long data_cnt,data,temp, num_nac=0;
  229. int busy = 1, i;
  230. if(!byte_cnt)
  231. return SD_MMC_NO_ERROR;
  232. memset(data_buf, 0, byte_cnt);
  233. *crc16 = 0;
  234. //wait until data is valid
  235. sd_set_dat0_input();
  236. if(sd_mmc_info->operation_mode == CARD_INDENTIFICATION_MODE)
  237. {
  238. do
  239. {
  240. sd_clk_identify_low();
  241. data = sd_get_dat0_value();
  242. if(!data)
  243. {
  244. busy = 0;
  245. }
  246. sd_clk_identify_high();
  247. num_nac++;
  248. }while(busy && (num_nac < sd_mmc_info->clks_nac));
  249. if(num_nac >= sd_mmc_info->clks_nac)
  250. return SD_MMC_ERROR_TIMEOUT;
  251. //read data
  252. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  253. {
  254. temp = 0;
  255. for(i=0; i<8; i++)
  256. {
  257. sd_clk_identify_low();
  258. data = sd_get_dat0_value();
  259. temp <<= 1;
  260. temp |= data;
  261. sd_clk_identify_high();
  262. }
  263. *data_buf = temp;
  264. data_buf++;
  265. }
  266. //Read CRC16 data
  267. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  268. {
  269. sd_clk_identify_low();
  270. data = sd_get_dat0_value();
  271. *crc16 <<= 1;
  272. *crc16 |= data;
  273. sd_clk_identify_high();
  274. }
  275. //for end bit
  276. sd_clk_identify_low();
  277. sd_clk_identify_high();
  278. }
  279. else // Tranfer mode
  280. {
  281. do
  282. {
  283. sd_clk_transfer_low();
  284. data = sd_get_dat0_value();
  285. if(!data)
  286. {
  287. busy = 0;
  288. }
  289. sd_clk_transfer_high();
  290. num_nac++;
  291. }while(busy && (num_nac < sd_mmc_info->clks_nac));
  292. if(num_nac >= sd_mmc_info->clks_nac)
  293. return SD_MMC_ERROR_TIMEOUT;
  294. //read data
  295. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  296. {
  297. temp = 0;
  298. for(i=0; i<8; i++)
  299. {
  300. sd_clk_transfer_low();
  301. data = sd_get_dat0_value();
  302. temp <<= 1;
  303. temp |= data;
  304. sd_clk_transfer_high();
  305. }
  306. *data_buf = temp;
  307. data_buf++;
  308. }
  309. //Read CRC16 data
  310. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  311. {
  312. sd_clk_transfer_low();
  313. data = sd_get_dat0_value();
  314. *crc16 <<= 1;
  315. *crc16 |= data;
  316. sd_clk_transfer_high();
  317. }
  318. //for end bit
  319. sd_clk_transfer_low();
  320. sd_clk_transfer_high();
  321. }
  322. return SD_MMC_NO_ERROR;
  323. }
  324. //Get response length according to response type
  325. int sd_get_response_length(SD_Response_Type_t res_type)
  326. {
  327. int num_res;
  328. switch(res_type)
  329. {
  330. case RESPONSE_R1:
  331. case RESPONSE_R1B:
  332. case RESPONSE_R3:
  333. case RESPONSE_R4:
  334. case RESPONSE_R5:
  335. case RESPONSE_R6:
  336. case RESPONSE_R7:
  337. num_res = RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH;
  338. break;
  339. case RESPONSE_R2_CID:
  340. case RESPONSE_R2_CSD:
  341. num_res = RESPONSE_R2_CID_CSD_LENGTH;
  342. break;
  343. case RESPONSE_NONE:
  344. num_res = RESPONSE_NONE_LENGTH;
  345. break;
  346. default:
  347. num_res = RESPONSE_NONE_LENGTH;
  348. break;
  349. }
  350. return num_res;
  351. }
  352. //Send command with response
  353. #ifdef SD_MMC_SW_CONTROL
  354. int sd_send_cmd_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned char cmd, unsigned long arg, SD_Response_Type_t res_type, unsigned char * res_buf)
  355. {
  356. int ret = SD_MMC_NO_ERROR, num_res;
  357. unsigned char cmd_buf[6];
  358. cmd_buf[0] = 0x40 | cmd; //0x40: host command, command: 6 bits
  359. cmd_buf[1] = arg >> 24; //Command argument: 32 bits
  360. cmd_buf[2] = arg >> 16;
  361. cmd_buf[3] = arg >> 8;
  362. cmd_buf[4] = (unsigned char)arg;
  363. cmd_buf[5] = sd_cal_crc7(cmd_buf, 5) | 0x01; //Calculate CRC checksum, 7 bits
  364. ret = sd_verify_crc7(cmd_buf, 6);
  365. if(ret)
  366. return SD_MMC_ERROR_COM_CRC;
  367. sd_write_cmd_data(sd_mmc_info, 6, cmd_buf);
  368. if(res_type == RESPONSE_NONE)
  369. {
  370. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC);
  371. return SD_MMC_NO_ERROR;
  372. }
  373. //A delay before dealing with response
  374. sd_delay_clocks_z(sd_mmc_info,SD_MMC_Z_CMD_TO_RES);
  375. num_res = sd_get_response_length(res_type);
  376. sd_clear_response(res_buf);
  377. ret = sd_read_response_data(sd_mmc_info, num_res, res_buf);
  378. if(ret)
  379. return ret;
  380. ret = sd_check_response(cmd, res_type, res_buf);
  381. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC);
  382. return ret;
  383. }
  384. #endif
  385. static const char* cmd_strings[] = {
  386. //0
  387. "SD_MMC_GO_IDLE_STATE",
  388. "MMC_SEND_OP_COND",
  389. "SD_MMC_ALL_SEND_CID",
  390. "SD_MMC_SEND_RELATIVE_ADDR",
  391. "Reserved",
  392. //5
  393. "IO_SEND_OP_COND",
  394. "SD_SET_BUS_WIDTHS", //MMC_SWITCH_FUNTION(6), SD_SWITCH_FUNCTION(46)
  395. "SD_MMC_SELECT_DESELECT_CARD",
  396. "SD_SEND_IF_COND", //MMC_SEND_EXT_CSD(8)
  397. "SD_MMC_SEND_CSD",
  398. //10
  399. "SD_MMC_SEND_CID",
  400. // "SD_READ_DAT_UNTIL_STOP", //replaced by "VOLTAGE_SWITCH"
  401. "VOLTAGE_SWITCH",
  402. "SD_MMC_STOP_TRANSMISSION",
  403. "SD_MMC_SEND_STATUS",
  404. "Reserved",
  405. //15
  406. "SD_MMC_GO_INACTIVE_STATE",
  407. "SD_MMC_SET_BLOCKLEN",
  408. "SD_MMC_READ_SINGLE_BLOCK",
  409. "SD_MMC_READ_MULTIPLE_BLOCK",
  410. "Reserved",
  411. //20
  412. "Reserved",
  413. "Reserved",
  414. "SD_SEND_NUM_WR_BLOCKS",
  415. "SD_SET_WR_BLK_ERASE_COUNT",
  416. "SD_MMC_WRITE_BLOCK",
  417. //25
  418. "SD_MMC_WRITE_MULTIPLE_BLOCK",
  419. "Reserved",
  420. "SD_MMC_PROGRAM_CSD",
  421. "SD_MMC_SET_WRITE_PROT",
  422. "SD_MMC_CLR_WRITE_PROT",
  423. //30
  424. "SD_MMC_SEND_WRITE_PROT",
  425. "Reserved",
  426. "SD_ERASE_WR_BLK_START", //MMC_TAG_SECTOR_START(32)
  427. "SD_ERASE_WR_BLK_END", //MMC_TAG_SECTOR_END(33)
  428. "MMC_UNTAG_SECTOR",
  429. //35
  430. "MMC_TAG_ERASE_GROUP_START",
  431. "MMC_TAG_ERASE_GROUP_END",
  432. "MMC_UNTAG_ERASE_GROUP",
  433. "SD_MMC_ERASE",
  434. "Reserved",
  435. //40
  436. "Reserved",
  437. "SD_APP_OP_COND",
  438. "SD_SET_CLR_CARD_DETECT", //MMC_LOCK_UNLOCK(42)
  439. "SDA reserved",
  440. "SDA reserved",
  441. //45
  442. "SDA reserved",
  443. "SD_SWITCH_FUNCTION",
  444. "SDA reserved",
  445. "SDA reserved",
  446. "SDA reserved",
  447. //50
  448. "SDA reserved",
  449. "SD_SEND_SCR",
  450. "IO_RW_DIRECT",
  451. "IO_RW_EXTENDED",
  452. "SDA reserved",
  453. //55
  454. "SD_APP_CMD",
  455. "SD_GEN_CMD",
  456. "Reserved",
  457. "Reserved",
  458. "Reserved",
  459. //60
  460. "Manufact reserved",
  461. "Manufact reserved",
  462. "Manufact reserved",
  463. "Manufact reserved",
  464. };
  465. #if 0
  466. static void my_print_cmd(unsigned char cmd)
  467. {
  468. if (cmd < 64)
  469. {
  470. printk("CMD%d : %s\n", cmd, cmd_strings[cmd]);
  471. }
  472. else
  473. {
  474. printk("CMD%d : no such cmd\n", cmd);
  475. }
  476. }
  477. #endif
  478. int using_sdxc_controller = 0; //set in sd_io_init()
  479. int sdxc_int_param = 0;
  480. unsigned int sdxc_delay = 20; //5*32=160us
  481. static void my_swap_64(unsigned char *pbuf)
  482. {
  483. unsigned int tmp;
  484. unsigned char *pt;
  485. tmp = *((unsigned int *)pbuf);
  486. pt = (unsigned char *)&tmp;
  487. pbuf[0] = pbuf[7];
  488. pbuf[1] = pbuf[6];
  489. pbuf[2] = pbuf[5];
  490. pbuf[3] = pbuf[4];
  491. pbuf[4] = pt[3];
  492. pbuf[5] = pt[2];
  493. pbuf[6] = pt[1];
  494. pbuf[7] = pt[0];
  495. }
  496. static int my_check = 0;
  497. #define MY_CHECK() { if (my_check) printk("check %d\n", check++); }
  498. unsigned char mycmd = 0;
  499. static int myt1 = 0;
  500. extern struct completion dat0_int_complete;
  501. int sdxc_check_dat0_ready(void)
  502. {
  503. unsigned int sdxc_status = READ_CBUS_REG(SD_REG3_STAT);
  504. SDXC_Status_Reg_t *sdxc_status_reg = (void *)&sdxc_status;
  505. return (sdxc_status_reg->dat_3_0 & 0x01) == 1;
  506. }
  507. ///my_write()
  508. int sdxc_send_cmd_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned char cmd, unsigned long arg, SD_Response_Type_t res_type, unsigned char * res_buf, unsigned char *data_buf, unsigned long data_cnt, int retry_flag)
  509. {
  510. int ret = SD_MMC_NO_ERROR, num_res;
  511. unsigned char *buffer = NULL;
  512. unsigned int value;
  513. int check = 0;
  514. SDXC_Send_Reg_t *sdxc_send_reg;
  515. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg;
  516. SDXC_Status_Reg_t *sdxc_status_reg;
  517. //SDXC_Clk_Reg_t *sdxc_clk_reg;
  518. SDXC_PDMA_Reg_t *sdxc_pdma_reg;
  519. //SDXC_Misc_Reg_t *sdxc_misc_reg;
  520. SDXC_Ictl_Reg_t *sdxc_ictl_reg;
  521. SDXC_Ista_Reg_t *sdxc_ista_reg;
  522. //SDXC_Srst_Reg_t *sdxc_srst_reg;
  523. unsigned int sdxc_send, sdxc_ctrl, sdxc_status, sdxc_pdma;// sdxc_clk, sdxc_misc;
  524. unsigned int sdxc_ictl, sdxc_ista;
  525. unsigned int timeout;
  526. dma_addr_t data_dma_to_device_addr=0;
  527. dma_addr_t data_dma_from_device_addr=0;
  528. int i;
  529. int check_dat0_busy = 0;
  530. //unsigned long tick1;
  531. mycmd = cmd;
  532. /*
  533. my_print_cmd(cmd); //lin
  534. if (cmd == SD_MMC_READ_SINGLE_BLOCK || cmd == SD_MMC_READ_MULTIPLE_BLOCK) {
  535. printk("sd_read : lba=%d, data_buf=%p/%p, data_cnt=%p\n", arg, data_buf, sd_mmc_info->sd_mmc_buf, data_cnt);
  536. }
  537. */
  538. MY_CHECK();
  539. sdxc_send = 0;
  540. sdxc_send_reg = (void *)&sdxc_send;
  541. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  542. sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  543. sdxc_status = READ_CBUS_REG(SD_REG3_STAT);
  544. sdxc_status &= 0xFFF000FF; //clear rx_count & tx_count
  545. sdxc_status_reg = (void *)&sdxc_status;
  546. sdxc_pdma = READ_CBUS_REG(SD_REG6_PDMA);
  547. sdxc_pdma_reg = (void *) &sdxc_pdma;
  548. sdxc_ictl = READ_CBUS_REG(SD_REG9_ICTL);
  549. sdxc_ictl_reg = (void *)&sdxc_ictl;
  550. sdxc_ista = READ_CBUS_REG(SD_REGA_ISTA);
  551. sdxc_ista_reg = (void *)&sdxc_ista;
  552. /*
  553. sdxc_srst = READ_CBUS_REG(SD_REGB_SRST);
  554. sdxc_srst_reg = (void *)&sdxc_srst;
  555. sdxc_srst_reg->main_ctrl_srst = 1;
  556. sdxc_srst_reg->rx_fifo_srst = 1;
  557. sdxc_srst_reg->tx_fifo_srst = 1;
  558. sdxc_srst_reg->dma_srst = 1;
  559. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  560. sd_delay_ms(10);
  561. //may remove
  562. sdxc_srst_reg->main_ctrl_srst = 0;
  563. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  564. */
  565. /*
  566. sdxc_srst = 0x27; //0x3F -- 0x27 : exclude rx_dphy_srst & tx_dphy_srst
  567. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  568. sd_delay_ms(1);
  569. */
  570. if (myt1)
  571. sd_delay_ms(1);
  572. /*
  573. sdxc_srst = 0x27;
  574. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  575. */
  576. if ((cmd == SD_SWITCH_FUNCTION) || (cmd == MMC_SEND_EXT_CSD))
  577. sdxc_send_reg->command_index = cmd-40; //for distinguish ACMD6 and CMD6,Maybe more good way but now I cant find
  578. else
  579. sdxc_send_reg->command_index = cmd;
  580. sd_clear_response(res_buf);
  581. MY_CHECK();
  582. switch(res_type)
  583. {
  584. case RESPONSE_R1:
  585. case RESPONSE_R1B:
  586. case RESPONSE_R3:
  587. case RESPONSE_R4:
  588. case RESPONSE_R6:
  589. case RESPONSE_R5:
  590. case RESPONSE_R7:
  591. sdxc_send_reg->command_has_resp = 1;
  592. sdxc_send_reg->response_length = 0; //48 bits
  593. break;
  594. case RESPONSE_R2_CID:
  595. case RESPONSE_R2_CSD:
  596. sdxc_send_reg->command_has_resp = 1;
  597. sdxc_send_reg->response_length = 1; //136 bits
  598. //sdxx : cmd_send_reg->res_crc7_from_8 = 1; //new not necessary ?
  599. sdxc_send_reg->response_no_crc = 1; //sdxx
  600. break;
  601. case RESPONSE_NONE:
  602. sdxc_send_reg->command_has_resp = 0;
  603. sdxc_send_reg->response_length = 0;
  604. break;
  605. default:
  606. sdxc_send_reg->command_has_resp = 0;
  607. sdxc_send_reg->response_length = 0;
  608. break;
  609. }
  610. //cmd with adtc
  611. switch(cmd)
  612. {
  613. case SD_MMC_SEND_STATUS :
  614. case SD_SEND_TUNNING_PATTERN :
  615. sdxc_send_reg->command_has_data = 1;
  616. sdxc_send_reg->data_direction = 0; //rx
  617. sdxc_send_reg->total_pack = 0;
  618. sdxc_ctrl_reg->pack_len = data_cnt;
  619. buffer = sd_mmc_info->sd_mmc_phy_buf;
  620. break;
  621. case SD_MMC_READ_SINGLE_BLOCK:
  622. case SD_MMC_READ_MULTIPLE_BLOCK:
  623. sdxc_send_reg->command_has_data = 1;
  624. sdxc_send_reg->data_direction = 0; //rx
  625. sdxc_send_reg->total_pack = data_cnt/sd_mmc_info->blk_len - 1;
  626. sdxc_ctrl_reg->pack_len = 0;
  627. buffer = sd_mmc_info->sd_mmc_phy_buf;
  628. break;
  629. case SD_SWITCH_FUNCTION:
  630. case MMC_SEND_EXT_CSD:
  631. sdxc_send_reg->command_has_data = 1;
  632. sdxc_send_reg->data_direction = 0; //rx
  633. sdxc_send_reg->total_pack = 0;
  634. sdxc_ctrl_reg->pack_len = data_cnt;
  635. buffer = sd_mmc_info->sd_mmc_phy_buf;
  636. break;
  637. case SD_MMC_WRITE_BLOCK:
  638. case SD_MMC_WRITE_MULTIPLE_BLOCK:
  639. sdxc_send_reg->command_has_data = 1;
  640. sdxc_send_reg->data_direction = 1; //tx
  641. sdxc_send_reg->total_pack = data_cnt/sd_mmc_info->blk_len - 1;
  642. sdxc_ctrl_reg->pack_len = 0;
  643. buffer = sd_mmc_info->sd_mmc_phy_buf;
  644. break;
  645. case IO_RW_EXTENDED:
  646. if(arg & (1<<27))
  647. {
  648. sdxc_send_reg->total_pack = data_cnt/sd_mmc_info->blk_len - 1;
  649. sdxc_ctrl_reg->pack_len = 0;
  650. }
  651. else
  652. {
  653. sdxc_send_reg->total_pack = 0;
  654. sdxc_ctrl_reg->pack_len = data_cnt;
  655. }
  656. if(arg & (1<<31))
  657. {
  658. sdxc_send_reg->command_has_data = 1;
  659. sdxc_send_reg->data_direction = 1; //tx
  660. //memcpy(sd_mmc_info->sd_mmc_buf, data_buf, data_cnt);
  661. //buffer = sd_mmc_info->sd_mmc_phy_buf;
  662. data_dma_to_device_addr=dma_map_single(NULL, (void *)data_buf, data_cnt, DMA_TO_DEVICE);
  663. buffer = (unsigned char*)data_dma_to_device_addr;
  664. }
  665. else
  666. {
  667. sdxc_send_reg->command_has_data = 1;
  668. sdxc_send_reg->data_direction = 0; //rx
  669. //buffer = sd_mmc_info->sd_mmc_phy_buf;
  670. data_dma_from_device_addr = dma_map_single(NULL, (void *)data_buf, data_cnt, DMA_FROM_DEVICE );
  671. buffer = (unsigned char*)data_dma_from_device_addr;
  672. }
  673. break;
  674. ////case SD_READ_DAT_UNTIL_STOP:
  675. case SD_SEND_NUM_WR_BLOCKS:
  676. case SD_MMC_PROGRAM_CSD:
  677. case SD_MMC_SEND_WRITE_PROT:
  678. case MMC_LOCK_UNLOCK:
  679. case SD_SEND_SCR:
  680. case SD_GEN_CMD:
  681. sdxc_send_reg->command_has_data = 1;
  682. sdxc_send_reg->data_direction = 0; //rx
  683. sdxc_send_reg->total_pack = 0;
  684. sdxc_ctrl_reg->pack_len = data_cnt;
  685. buffer = sd_mmc_info->sd_mmc_phy_buf;
  686. break;
  687. default:
  688. break;
  689. }
  690. //cmd with R1b
  691. switch(cmd)
  692. {
  693. case SD_MMC_STOP_TRANSMISSION:
  694. sdxc_send_reg->data_stop = 1;
  695. case SD_MMC_SET_WRITE_PROT:
  696. case SD_MMC_CLR_WRITE_PROT:
  697. case SD_MMC_ERASE:
  698. case MMC_LOCK_UNLOCK:
  699. //sdxx : cmd_send_reg->check_dat0_busy = 1;
  700. check_dat0_busy = 1;
  701. break;
  702. default:
  703. break;
  704. }
  705. //cmd with R3
  706. switch(cmd)
  707. {
  708. case MMC_SEND_OP_COND:
  709. case SD_APP_OP_COND:
  710. case IO_SEND_OP_COND:
  711. //cmd_send_reg->res_without_crc7 = 1;
  712. sdxc_send_reg->response_no_crc = 1; //sdxx
  713. break;
  714. default:
  715. break;
  716. }
  717. #define SD_MMC_CMD_COUNT 20000//20
  718. #define SD_MMC_READ_BUSY_COUNT 2000000//20
  719. #define SD_MMC_WRITE_BUSY_COUNT 50000000//500000
  720. #define SD_MMC_WAIT_STOP_COUNT 100000000
  721. #define SD_MMC_RETRY_COUNT 2
  722. if((sdxc_send_reg->command_has_data == 1) && (sdxc_send_reg->data_direction == 1))
  723. {
  724. if(cmd == SD_MMC_WRITE_MULTIPLE_BLOCK)
  725. timeout = SD_MMC_WRITE_BUSY_COUNT * (data_cnt/512);
  726. else if(cmd == IO_RW_EXTENDED)
  727. timeout = SD_MMC_WRITE_BUSY_COUNT * (sdxc_send_reg->total_pack + 1);
  728. else
  729. timeout = SD_MMC_WRITE_BUSY_COUNT;
  730. }
  731. else
  732. {
  733. if(cmd == SD_MMC_READ_MULTIPLE_BLOCK)
  734. timeout = SD_MMC_READ_BUSY_COUNT * (data_cnt/512);
  735. else if(cmd == IO_RW_EXTENDED)
  736. timeout = SD_MMC_READ_BUSY_COUNT * (sdxc_send_reg->total_pack + 1);
  737. else
  738. timeout = SD_MMC_CMD_COUNT;
  739. }
  740. MY_CHECK();
  741. if(cmd == SD_MMC_STOP_TRANSMISSION)
  742. timeout = SD_MMC_WAIT_STOP_COUNT;
  743. sdxc_ista |= 0x00007FFF; //sdxx : clear the interrupt status bits
  744. if(sdxc_send_reg->command_has_data) {
  745. WRITE_CBUS_REG(SD_REG5_ADDR, (unsigned long)buffer);
  746. }
  747. if ((sd_mmc_info->card_type == CARD_TYPE_EMMC || sd_mmc_info->card_type == CARD_TYPE_MMC) &&
  748. (cmd == SD_MMC_READ_SINGLE_BLOCK || cmd == SD_MMC_READ_MULTIPLE_BLOCK
  749. || cmd == SD_MMC_WRITE_BLOCK || cmd == SD_MMC_WRITE_MULTIPLE_BLOCK)) {
  750. sdxc_ctrl_reg->endian = 0x00;
  751. }
  752. else {
  753. sdxc_ctrl_reg->endian = 0x03;
  754. if (sdxc_send_reg->command_has_data && (sdxc_send_reg->data_direction == 1)) { //@@ wr
  755. unsigned int packs, count;
  756. unsigned char* pbuf;
  757. packs = sdxc_send_reg->total_pack;
  758. if (sdxc_ctrl_reg->pack_len != 0)
  759. count = sdxc_ctrl_reg->pack_len / 8; // convert byte to int64
  760. else
  761. count = 512 / 8; // convert byte to int64
  762. pbuf = (unsigned char*)data_buf;
  763. do {
  764. for (i = 0; i < count; i++)
  765. {
  766. my_swap_64(pbuf);
  767. pbuf += 8;
  768. }
  769. } while (packs--);
  770. }
  771. }
  772. WRITE_CBUS_REG(SD_REG0_ARGU, arg);
  773. WRITE_CBUS_REG(SD_REGA_ISTA, sdxc_ista);
  774. WRITE_CBUS_REG(SD_REG3_STAT, sdxc_status);
  775. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  776. MY_CHECK();
  777. sdio_command_err = SDIO_NONE_ERR;
  778. sdxc_int_param = 0;
  779. sdio_command_int_num = 0;
  780. if (sdxc_send_reg->command_has_resp)
  781. sdio_command_int_num++;
  782. if (sdxc_send_reg->command_has_data)
  783. sdio_command_int_num++;
  784. init_completion(&dat0_int_complete);
  785. init_completion(&sdio_int_complete);
  786. sdio_open_host_interrupt(SDIO_CMD_INT);
  787. sdio_open_host_interrupt(SDIO_TIMEOUT_INT);
  788. /*
  789. if (check_dat0_busy) {
  790. sdxc_ictl = READ_CBUS_REG(SD_REG9_ICTL);
  791. sdxc_ictl_reg->dat0_ready_int_en = 1;
  792. WRITE_CBUS_REG(SD_REG9_ICTL, sdxc_ictl);
  793. }
  794. */
  795. WRITE_CBUS_REG(SD_REG1_SEND, sdxc_send); //launching sdxc
  796. timeout =50;//0.5s
  797. if (cmd == SD_MMC_READ_SINGLE_BLOCK || cmd == SD_MMC_READ_MULTIPLE_BLOCK
  798. || cmd == SD_MMC_WRITE_BLOCK || cmd == SD_MMC_WRITE_MULTIPLE_BLOCK)
  799. timeout = 500; // 5s
  800. timeout = wait_for_completion_timeout(&sdio_int_complete,timeout);
  801. /*
  802. if (timeout != 0 && check_dat0_busy && !sdxc_check_dat0_ready()) {
  803. //unsigned int timeout2 = 50; // 0.5s
  804. unsigned int timeout2 = 300; // 0.5s
  805. timeout2 = wait_for_completion_timeout(&dat0_int_complete,timeout2);
  806. if(timeout2 == 0) {
  807. printk("[sdxc] dat0 timeout2\n");
  808. if (!sdxc_check_dat0_ready()) {
  809. printk("[sdxc] dat0 not 1\n");
  810. timeout = 0; //set up traps
  811. }
  812. }
  813. }
  814. */
  815. if (timeout != 0 && check_dat0_busy && !sdxc_check_dat0_ready()) {
  816. unsigned int retry_limit;
  817. unsigned int timeout3;
  818. retry_limit = 200;
  819. while (--retry_limit) {
  820. timeout3 = wait_for_completion_timeout(&dat0_int_complete, 1);
  821. if(timeout3 != 0) {
  822. if (!sdxc_check_dat0_ready())
  823. printk("bad dat0 int, sdxc_int_param=%03d\n", sdxc_int_param);
  824. //printk("[sdxc] dat0 int %d\n", 100 - retry_limit);
  825. break;
  826. }
  827. else if (sdxc_check_dat0_ready()) {
  828. //printk("[sdxc] dat0 ready %d\n", 100 - retry_limit);
  829. break;
  830. }
  831. }
  832. if (retry_limit == 0) {
  833. printk("[sdxc] dat0 error\n");
  834. timeout = 0; //set up traps
  835. }
  836. }
  837. sdio_close_host_interrupt(SDIO_CMD_INT);
  838. sdio_close_host_interrupt(SDIO_TIMEOUT_INT);
  839. /*
  840. if (check_dat0_busy) {
  841. sdxc_ictl = READ_CBUS_REG(SD_REG9_ICTL);
  842. sdxc_ictl_reg->dat0_ready_int_en = 0;
  843. WRITE_CBUS_REG(SD_REG9_ICTL, sdxc_ictl);
  844. }
  845. */
  846. if(timeout == 0) {
  847. ret = SD_MMC_ERROR_TIMEOUT;
  848. printk("[sdxc] wait_for_completion_timeout for cmd(%d)=%s\n", cmd, cmd_strings[cmd]);
  849. goto error;
  850. }
  851. MY_CHECK(); // 4
  852. if (sdio_command_err == SDIO_RES_TIMEOUT_ERR || sdio_command_err == SDIO_PACK_TIMEOUT_ERR)
  853. {
  854. printk("sdio_command_err = %s for cmd(%d)=%s\n", sdio_command_err == SDIO_RES_TIMEOUT_ERR ? "SDIO_RES_TIMEOUT_ERR" : "SDIO_PACK_TIMEOUT_ERR", cmd, cmd_strings[cmd]);
  855. ret = SD_MMC_ERROR_TIMEOUT;
  856. goto error;
  857. }
  858. if (sdio_command_err == SDIO_RES_CRC_ERR || sdio_command_err == SDIO_PACK_CRC_ERR)
  859. {
  860. printk("sdio_command_err2 = %s for cmd(%d)=%s\n", sdio_command_err == SDIO_RES_CRC_ERR ? "SDIO_RES_CRC_ERR" : "SDIO_PACK_CRC_ERR", cmd, cmd_strings[cmd]);
  861. ret = SD_MMC_ERROR_COM_CRC;
  862. goto error;
  863. }
  864. /*
  865. if (check_dat0_busy && !sdxc_check_dat0_ready()) {
  866. sdxc_ictl = READ_CBUS_REG(SD_REG9_ICTL);
  867. sdxc_ictl_reg->dat0_ready_int_en = 1;
  868. WRITE_CBUS_REG(SD_REG9_ICTL, sdxc_ictl);
  869. timeout = 50; // 0.5s
  870. timeout = wait_for_completion_timeout(&dat0_int_complete,timeout);
  871. sdxc_ictl_reg->dat0_ready_int_en = 0;
  872. WRITE_CBUS_REG(SD_REG9_ICTL, sdxc_ictl);
  873. if(timeout == 0) {
  874. printk("[sdxc] dat0 timeout\n");
  875. if (!sdxc_check_dat0_ready()) {
  876. ret = SD_MMC_ERROR_TIMEOUT;
  877. printk("[sdxc] dat0 not 1\n");
  878. goto error;
  879. }
  880. }
  881. }
  882. */
  883. //printk("sdxc_int_param=%03d for cmd=%d\n", sdxc_int_param, cmd);
  884. /*
  885. tick1 = jiffies + 200; // 2s
  886. if (check_dat0_busy) {
  887. do {
  888. sdxc_ista = READ_CBUS_REG(SD_REGA_ISTA);
  889. sdxc_ista_reg = (void *)&sdxc_ista;
  890. sdxc_status = READ_CBUS_REG(SD_REG3_STAT);
  891. sdxc_status_reg = (void *)&sdxc_status;
  892. if (time_after(jiffies, tick1)) {
  893. printk("wait for dat0 timeout for cmd(%d)=%s\n", cmd, cmd_strings[cmd]);
  894. break;
  895. }
  896. } while ((sdxc_ista_reg->dat0_ready_int == 0) && ((sdxc_status_reg->dat_3_0 & 0x01) == 0));
  897. //printk("A dat0_ready_int=%d, dat_3_0=%d for cmd(%d)=%s\n", sdxc_ista_reg->dat0_ready_int, sdxc_status_reg->dat_3_0, cmd, cmd_strings[cmd]);
  898. }
  899. printk("sdxc_int_param = %d for cmd=%d\n", sdxc_int_param, cmd);
  900. */
  901. MY_CHECK(); // 5
  902. if (sdxc_send_reg->command_has_resp)
  903. {
  904. /*
  905. { //lin : test resp[39:08]
  906. sdxc_pdma_reg->pio_rd_resp = 0;
  907. WRITE_CBUS_REG(SD_REG6_PDMA, sdxc_pdma);
  908. value = READ_CBUS_REG(SD_REG0_ARGU);
  909. printk("response[39:08]=%08x\n ", value);
  910. for (i = 7; i>= 0; i--)
  911. {
  912. sdxc_pdma_reg->pio_rd_resp = i;
  913. WRITE_CBUS_REG(SD_REG6_PDMA, sdxc_pdma);
  914. value = READ_CBUS_REG(SD_REG0_ARGU);
  915. printk("%08x ", value);
  916. }
  917. printk("\n");
  918. }
  919. */
  920. if (sdxc_send_reg->response_length == 0) //48 bits
  921. {
  922. num_res = 6;
  923. }
  924. else //136 bits
  925. {
  926. num_res = 17;
  927. }
  928. sdxc_pdma_reg->pio_rd_resp = 0;
  929. while (1)
  930. {
  931. sdxc_pdma_reg->pio_rd_resp++;
  932. WRITE_CBUS_REG(SD_REG6_PDMA, sdxc_pdma);
  933. value = READ_CBUS_REG(SD_REG0_ARGU);
  934. res_buf[--num_res] = value & 0xFF;
  935. if (num_res == 0)
  936. break;
  937. res_buf[--num_res] = (value >> 8) & 0xFF;
  938. if (num_res == 0)
  939. break;
  940. res_buf[--num_res] = (value >> 16) & 0xFF;
  941. if (num_res == 0)
  942. break;
  943. res_buf[--num_res] = (value >> 24) & 0xFF;
  944. if (num_res == 0)
  945. break;
  946. }
  947. }
  948. MY_CHECK(); // 6
  949. ret = sd_check_response(cmd, res_type, res_buf);
  950. if(ret)
  951. goto error;
  952. /*error need dma_unmap_single also*/
  953. error:
  954. //printk("sdxc cmd(%d) : sdxc_int_param=%d, sdio_command_err=%d\n", cmd, sdxc_int_param, sdio_command_err);
  955. if(data_dma_from_device_addr)
  956. {
  957. dma_unmap_single(NULL, data_dma_from_device_addr, data_cnt, DMA_FROM_DEVICE);
  958. }
  959. if(data_dma_to_device_addr)
  960. {
  961. dma_unmap_single(NULL, data_dma_to_device_addr, data_cnt, DMA_TO_DEVICE);
  962. }
  963. /* //lin : I fix the sd_read_multi_block_hw() and sd_write_multi_block_hw() already
  964. if((sdxc_send_reg->command_has_data == 1) && (sdxc_send_reg->data_direction == 0) && buffer && (data_buf != sd_mmc_info->sd_mmc_buf)
  965. && (!data_dma_from_device_addr) && (!data_dma_to_device_addr))
  966. {
  967. printk("Not sd_mmc_buf, copying\n");
  968. ////memcpy(data_buf, sd_mmc_info->sd_mmc_buf, data_cnt);
  969. }
  970. */
  971. MY_CHECK(); // 7
  972. return ret;
  973. }
  974. int wait_flag;
  975. //Send command with response
  976. #ifdef SD_MMC_HW_CONTROL
  977. int sd_send_cmd_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned char cmd, unsigned long arg, SD_Response_Type_t res_type, unsigned char * res_buf, unsigned char *data_buf, unsigned long data_cnt, int retry_flag)
  978. {
  979. int ret = SD_MMC_NO_ERROR, num_res;
  980. unsigned char *buffer = NULL;
  981. unsigned int cmd_ext, cmd_send;
  982. MSHW_IRQ_Config_Reg_t *irq_config_reg;
  983. SDIO_Status_IRQ_Reg_t *status_irq_reg;
  984. SDHW_CMD_Send_Reg_t *cmd_send_reg;
  985. SDHW_Extension_Reg_t *cmd_ext_reg;
  986. unsigned int irq_config, status_irq, timeout;
  987. dma_addr_t data_dma_to_device_addr=0;
  988. dma_addr_t data_dma_from_device_addr=0;
  989. if ((sd_mmc_info->io_pad_type == SDXC_CARD_0_5) ||
  990. (sd_mmc_info->io_pad_type == SDXC_BOOT_0_11) ||
  991. (sd_mmc_info->io_pad_type == SDXC_GPIOX_0_9))
  992. using_sdxc_controller = 1;
  993. else
  994. using_sdxc_controller = 0;
  995. if (using_sdxc_controller)
  996. return sdxc_send_cmd_hw(sd_mmc_info, cmd, arg, res_type, res_buf, data_buf, data_cnt, retry_flag);
  997. //my_print_cmd(cmd); //lin
  998. cmd_send = 0;
  999. cmd_send_reg = (void *)&cmd_send;
  1000. if ((cmd == SD_SWITCH_FUNCTION) || (cmd == MMC_SEND_EXT_CSD))
  1001. cmd_send_reg->cmd_data = 0x40 | (cmd-40); //for distinguish ACMD6 and CMD6,Maybe more good way but now I cant find
  1002. else
  1003. cmd_send_reg->cmd_data = 0x40 | cmd;
  1004. cmd_send_reg->use_int_window = 1;
  1005. cmd_ext = 0;
  1006. cmd_ext_reg = (void *)&cmd_ext;
  1007. //if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1008. // cmd_ext_reg->crc_status_4line = 1;
  1009. sd_clear_response(res_buf);
  1010. switch(res_type)
  1011. {
  1012. case RESPONSE_R1:
  1013. case RESPONSE_R1B:
  1014. case RESPONSE_R3:
  1015. case RESPONSE_R4:
  1016. case RESPONSE_R6:
  1017. case RESPONSE_R5:
  1018. case RESPONSE_R7:
  1019. cmd_send_reg->cmd_res_bits = 45; // RESPONSE have 7(cmd)+32(respnse)+7(crc)-1 data
  1020. break;
  1021. case RESPONSE_R2_CID:
  1022. case RESPONSE_R2_CSD:
  1023. cmd_send_reg->cmd_res_bits = 133; // RESPONSE have 7(cmd)+120(respnse)+7(crc)-1 data
  1024. cmd_send_reg->res_crc7_from_8 = 1;
  1025. break;
  1026. case RESPONSE_NONE:
  1027. cmd_send_reg->cmd_res_bits = 0; // NO_RESPONSE
  1028. break;
  1029. default:
  1030. cmd_send_reg->cmd_res_bits = 0; // NO_RESPONSE
  1031. break;
  1032. }
  1033. //cmd with adtc
  1034. switch(cmd)
  1035. {
  1036. case SD_MMC_SEND_STATUS :
  1037. case SD_SEND_TUNNING_PATTERN :
  1038. cmd_send_reg->res_with_data = 1;
  1039. cmd_send_reg->repeat_package_times = 0;
  1040. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1041. cmd_ext_reg->data_rw_number = data_cnt * 8 + (16 - 1) * 4;
  1042. else
  1043. cmd_ext_reg->data_rw_number = data_cnt * 8 + 16 - 1;
  1044. buffer = sd_mmc_info->sd_mmc_phy_buf;
  1045. break;
  1046. case SD_MMC_READ_SINGLE_BLOCK:
  1047. case SD_MMC_READ_MULTIPLE_BLOCK:
  1048. cmd_send_reg->res_with_data = 1;
  1049. cmd_send_reg->repeat_package_times = data_cnt/sd_mmc_info->blk_len - 1;
  1050. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1051. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + (16 - 1) * 4;
  1052. else
  1053. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + 16 - 1;
  1054. buffer = sd_mmc_info->sd_mmc_phy_buf;
  1055. break;
  1056. case SD_SWITCH_FUNCTION:
  1057. case MMC_SEND_EXT_CSD:
  1058. cmd_send_reg->res_with_data = 1;
  1059. cmd_send_reg->repeat_package_times = 0;
  1060. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1061. cmd_ext_reg->data_rw_number = data_cnt * 8 + (16 - 1) * 4;
  1062. else
  1063. cmd_ext_reg->data_rw_number = data_cnt * 8 + 16 - 1;
  1064. buffer = sd_mmc_info->sd_mmc_phy_buf;
  1065. break;
  1066. case SD_MMC_WRITE_BLOCK:
  1067. case SD_MMC_WRITE_MULTIPLE_BLOCK:
  1068. cmd_send_reg->cmd_send_data = 1;
  1069. cmd_send_reg->repeat_package_times = data_cnt/sd_mmc_info->blk_len - 1;
  1070. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1071. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + (16 - 1) * 4;
  1072. else
  1073. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + 16 - 1;
  1074. buffer = sd_mmc_info->sd_mmc_phy_buf;
  1075. wmb();
  1076. break;
  1077. case IO_RW_EXTENDED:
  1078. if(arg & (1<<27))
  1079. {
  1080. cmd_send_reg->repeat_package_times = data_cnt/sd_mmc_info->blk_len - 1;
  1081. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1082. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + (16 - 1) * 4;
  1083. else
  1084. cmd_ext_reg->data_rw_number = sd_mmc_info->blk_len * 8 + (16 - 1);
  1085. }
  1086. else
  1087. {
  1088. cmd_send_reg->repeat_package_times = 0;
  1089. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1090. cmd_ext_reg->data_rw_number = data_cnt * 8 + (16 - 1) * 4;
  1091. else
  1092. cmd_ext_reg->data_rw_number = data_cnt * 8 + (16 - 1);
  1093. }
  1094. if(arg & (1<<31))
  1095. {
  1096. cmd_send_reg->cmd_send_data = 1;
  1097. //memcpy(sd_mmc_info->sd_mmc_buf, data_buf, data_cnt);
  1098. //buffer = sd_mmc_info->sd_mmc_phy_buf;
  1099. data_dma_to_device_addr=dma_map_single(NULL, (void *)data_buf, data_cnt, DMA_TO_DEVICE);
  1100. buffer = (unsigned char*)data_dma_to_device_addr;
  1101. }
  1102. else
  1103. {
  1104. cmd_send_reg->res_with_data = 1;
  1105. //buffer = sd_mmc_info->sd_mmc_phy_buf;
  1106. data_dma_from_device_addr = dma_map_single(NULL, (void *)data_buf, data_cnt, DMA_FROM_DEVICE );
  1107. buffer = (unsigned char*)data_dma_from_device_addr;
  1108. }
  1109. break;
  1110. ////case SD_READ_DAT_UNTIL_STOP:
  1111. case SD_SEND_NUM_WR_BLOCKS:
  1112. case SD_MMC_PROGRAM_CSD:
  1113. case SD_MMC_SEND_WRITE_PROT:
  1114. case MMC_LOCK_UNLOCK:
  1115. case SD_SEND_SCR:
  1116. case SD_GEN_CMD:
  1117. cmd_send_reg->res_with_data = 1;
  1118. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1119. cmd_ext_reg->data_rw_number = data_cnt * 8 + (16 - 1) * 4;
  1120. else
  1121. cmd_ext_reg->data_rw_number = data_cnt * 8 + 16 - 1;
  1122. buffer = sd_mmc_info->sd_mmc_phy_buf;
  1123. break;
  1124. default:
  1125. break;
  1126. }
  1127. //cmd with R1b
  1128. switch(cmd)
  1129. {
  1130. case SD_MMC_STOP_TRANSMISSION:
  1131. case SD_MMC_SET_WRITE_PROT:
  1132. case SD_MMC_CLR_WRITE_PROT:
  1133. case SD_MMC_ERASE:
  1134. case MMC_LOCK_UNLOCK:
  1135. cmd_send_reg->check_dat0_busy = 1;
  1136. break;
  1137. default:
  1138. break;
  1139. }
  1140. //cmd with R3
  1141. switch(cmd)
  1142. {
  1143. case MMC_SEND_OP_COND:
  1144. case SD_APP_OP_COND:
  1145. case IO_SEND_OP_COND:
  1146. cmd_send_reg->res_without_crc7 = 1;
  1147. break;
  1148. default:
  1149. break;
  1150. }
  1151. #define SD_MMC_CMD_COUNT 20000//20
  1152. #define SD_MMC_READ_BUSY_COUNT 2000000//20
  1153. #define SD_MMC_WRITE_BUSY_COUNT 50000000//500000
  1154. //#define SD_MMC_WAIT_STOP_COUNT 100000000
  1155. #define SD_MMC_RETRY_COUNT 2
  1156. if(cmd_send_reg->cmd_send_data)
  1157. {
  1158. if(cmd == SD_MMC_WRITE_MULTIPLE_BLOCK)
  1159. timeout = SD_MMC_WRITE_BUSY_COUNT * (data_cnt/512);
  1160. else if(cmd == IO_RW_EXTENDED)
  1161. timeout = SD_MMC_WRITE_BUSY_COUNT * (cmd_send_reg->repeat_package_times + 1);
  1162. else
  1163. timeout = SD_MMC_WRITE_BUSY_COUNT;
  1164. }
  1165. else
  1166. {
  1167. if(cmd == SD_MMC_READ_MULTIPLE_BLOCK)
  1168. timeout = SD_MMC_READ_BUSY_COUNT * (data_cnt/512);
  1169. else if(cmd == IO_RW_EXTENDED)
  1170. timeout = SD_MMC_READ_BUSY_COUNT * (cmd_send_reg->repeat_package_times + 1);
  1171. else
  1172. timeout = SD_MMC_CMD_COUNT;
  1173. }
  1174. if(cmd == SD_MMC_STOP_TRANSMISSION)
  1175. timeout = SD_MMC_WAIT_STOP_COUNT;
  1176. irq_config = READ_CBUS_REG(SDIO_IRQ_CONFIG);
  1177. irq_config_reg = (void *)&irq_config;
  1178. irq_config_reg->soft_reset = 1;
  1179. WRITE_CBUS_REG(SDIO_IRQ_CONFIG, irq_config);
  1180. status_irq = 0;
  1181. status_irq_reg = (void *)&status_irq;
  1182. status_irq_reg->if_int = 1;
  1183. status_irq_reg->cmd_int = 1;
  1184. status_irq_reg->timing_out_int = 1;
  1185. if(timeout > (sd_mmc_info->sdio_clk_unit*0x1FFF)/1000)
  1186. {
  1187. status_irq_reg->timing_out_count = 0x1FFF;
  1188. //sdio_timeout_int_times = (timeout*1000)/(sd_mmc_info->sdio_clk_unit*0x1FFF);
  1189. sdio_timeout_int_times = timeout/(sd_mmc_info->sdio_clk_unit*0x1FFF/1000);
  1190. }
  1191. else
  1192. {
  1193. status_irq_reg->timing_out_count = (timeout/sd_mmc_info->sdio_clk_unit)*1000;
  1194. sdio_timeout_int_times = 1;
  1195. }
  1196. WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
  1197. WRITE_CBUS_REG(CMD_ARGUMENT, arg);
  1198. WRITE_CBUS_REG(SDIO_EXTENSION, cmd_ext);
  1199. if(buffer != NULL)
  1200. {
  1201. WRITE_CBUS_REG(SDIO_M_ADDR, (unsigned long)buffer);
  1202. }
  1203. init_completion(&sdio_int_complete);
  1204. sdio_open_host_interrupt(SDIO_CMD_INT);
  1205. sdio_open_host_interrupt(SDIO_TIMEOUT_INT);
  1206. WRITE_CBUS_REG(CMD_SEND, cmd_send); //launching sdhc
  1207. timeout =500;/*5s*/
  1208. timeout = wait_for_completion_timeout(&sdio_int_complete,timeout);
  1209. sdio_close_host_interrupt(SDIO_CMD_INT);
  1210. sdio_close_host_interrupt(SDIO_TIMEOUT_INT);
  1211. if(sdio_timeout_int_times == 0 || timeout == 0){
  1212. ret = SD_MMC_ERROR_TIMEOUT;
  1213. if(timeout == 0)
  1214. printk("[sd_send_cmd_hw] wait_for_completion_timeout for cmd(%d)=%s\n", cmd, cmd_strings[cmd]);
  1215. printk("sdio_timeout_int_times = %d; timeout = %d\n",sdio_timeout_int_times,timeout);
  1216. goto error;
  1217. }
  1218. status_irq = READ_CBUS_REG(SDIO_STATUS_IRQ);
  1219. if(cmd_send_reg->cmd_res_bits && !cmd_send_reg->res_without_crc7 && !status_irq_reg->res_crc7_ok && !sd_mmc_info->sdio_read_crc_close){
  1220. ret = SD_MMC_ERROR_COM_CRC;
  1221. goto error;
  1222. }
  1223. num_res = sd_get_response_length(res_type);
  1224. if(num_res > 0)
  1225. {
  1226. unsigned long multi_config = 0;
  1227. SDIO_Multi_Config_Reg_t *multi_config_reg = (void *)&multi_config;
  1228. multi_config_reg->write_read_out_index = 1;
  1229. WRITE_CBUS_REG(SDIO_MULT_CONFIG, multi_config);
  1230. num_res--; // Minus CRC byte
  1231. }
  1232. while(num_res)
  1233. {
  1234. unsigned long data_temp = READ_CBUS_REG(CMD_ARGUMENT);
  1235. res_buf[--num_res] = data_temp & 0xFF;
  1236. if(num_res <= 0)
  1237. break;
  1238. res_buf[--num_res] = (data_temp >> 8) & 0xFF;
  1239. if(num_res <= 0)
  1240. break;
  1241. res_buf[--num_res] = (data_temp >> 16) & 0xFF;
  1242. if(num_res <= 0)
  1243. break;
  1244. res_buf[--num_res] = (data_temp >> 24) & 0xFF;
  1245. }
  1246. ret = sd_check_response(cmd, res_type, res_buf);
  1247. if(ret)
  1248. goto error;
  1249. //cmd with adtc
  1250. switch(cmd)
  1251. {
  1252. ////case SD_READ_DAT_UNTIL_STOP:
  1253. case SD_MMC_READ_SINGLE_BLOCK:
  1254. case SD_MMC_READ_MULTIPLE_BLOCK:
  1255. case SD_SWITCH_FUNCTION:
  1256. case MMC_SEND_EXT_CSD:
  1257. if(!status_irq_reg->data_read_crc16_ok){
  1258. ret = SD_MMC_ERROR_DATA_CRC;
  1259. goto error;
  1260. }
  1261. break;
  1262. case SD_MMC_WRITE_BLOCK:
  1263. case SD_MMC_WRITE_MULTIPLE_BLOCK:
  1264. case SD_MMC_PROGRAM_CSD:
  1265. if(!status_irq_reg->data_write_crc16_ok){
  1266. ret = SD_MMC_ERROR_DATA_CRC;
  1267. goto error;
  1268. }
  1269. break;
  1270. case SD_SEND_NUM_WR_BLOCKS:
  1271. case SD_MMC_SEND_WRITE_PROT:
  1272. case MMC_LOCK_UNLOCK:
  1273. case SD_SEND_SCR:
  1274. case SD_GEN_CMD:
  1275. if(!status_irq_reg->data_read_crc16_ok){
  1276. ret = SD_MMC_ERROR_DATA_CRC;
  1277. goto error;
  1278. }
  1279. break;
  1280. case IO_RW_EXTENDED:
  1281. if(arg & (1<<31))
  1282. {
  1283. if(!status_irq_reg->data_write_crc16_ok){
  1284. ret = SD_MMC_ERROR_DATA_CRC;
  1285. goto error;
  1286. }
  1287. }
  1288. else
  1289. {
  1290. if(!sd_mmc_info->sdio_read_crc_close)
  1291. {
  1292. if(!status_irq_reg->data_read_crc16_ok){
  1293. ret = SD_MMC_ERROR_DATA_CRC;
  1294. goto error;
  1295. }
  1296. }
  1297. }
  1298. break;
  1299. default:
  1300. break;
  1301. }
  1302. /*error need dma_unmap_single also*/
  1303. error:
  1304. if(data_dma_from_device_addr)
  1305. {
  1306. dma_unmap_single(NULL, data_dma_from_device_addr, data_cnt, DMA_FROM_DEVICE);
  1307. }
  1308. if(data_dma_to_device_addr)
  1309. {
  1310. dma_unmap_single(NULL, data_dma_to_device_addr, data_cnt, DMA_TO_DEVICE);
  1311. }
  1312. if(cmd_send_reg->res_with_data && buffer && (data_buf != sd_mmc_info->sd_mmc_buf)
  1313. && (!data_dma_from_device_addr) && (!data_dma_to_device_addr))
  1314. {
  1315. printk("Not sd_mmc_buf2, copying\n");
  1316. memcpy(data_buf, sd_mmc_info->sd_mmc_buf, data_cnt);
  1317. }
  1318. return ret;
  1319. }
  1320. #endif
  1321. //Read SD Response Data
  1322. int sd_read_response_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long byte_cnt, unsigned char * res_buf)
  1323. {
  1324. unsigned long data_cnt, num_ncr = 0;
  1325. unsigned char data, temp;
  1326. int busy = 1, i;
  1327. if(!byte_cnt)
  1328. return SD_MMC_NO_ERROR;
  1329. memset(res_buf, 0, byte_cnt);
  1330. sd_set_cmd_input();
  1331. if(sd_mmc_info->operation_mode == CARD_INDENTIFICATION_MODE)
  1332. {
  1333. //wait until cmd line is valid
  1334. do
  1335. {
  1336. sd_clk_identify_low();
  1337. data = sd_get_cmd_value();
  1338. if(!data)
  1339. {
  1340. busy = 0;
  1341. break;
  1342. }
  1343. sd_clk_identify_high();
  1344. num_ncr++;
  1345. }while(busy && (num_ncr < SD_MMC_TIME_NCR_MAX));
  1346. if(num_ncr >= SD_MMC_TIME_NCR_MAX)
  1347. return SD_MMC_ERROR_TIMEOUT;
  1348. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  1349. {
  1350. temp = 0;
  1351. for(i=0; i<8; i++)
  1352. {
  1353. sd_clk_identify_low();
  1354. data = sd_get_cmd_value();
  1355. temp <<= 1;
  1356. temp |= data;
  1357. sd_clk_identify_high();
  1358. }
  1359. *res_buf = temp;
  1360. res_buf++;
  1361. }
  1362. }
  1363. else // Tranfer mode
  1364. {
  1365. //wait until cmd line is valid
  1366. do
  1367. {
  1368. sd_clk_transfer_low();
  1369. data = sd_get_cmd_value();
  1370. if(!data)
  1371. {
  1372. busy = 0;
  1373. break;
  1374. }
  1375. sd_clk_transfer_high();
  1376. num_ncr++;
  1377. }while(busy && (num_ncr < SD_MMC_TIME_NCR_MAX));
  1378. if(num_ncr >= SD_MMC_TIME_NCR_MAX)
  1379. return SD_MMC_ERROR_TIMEOUT;
  1380. for(data_cnt = 0; data_cnt < byte_cnt; data_cnt++)
  1381. {
  1382. temp = 0;
  1383. for(i=0; i<8; i++)
  1384. {
  1385. sd_clk_transfer_low();
  1386. data = sd_get_cmd_value();
  1387. temp <<= 1;
  1388. temp |= data;
  1389. sd_clk_transfer_high();
  1390. }
  1391. *res_buf = temp;
  1392. res_buf++;
  1393. }
  1394. }
  1395. return SD_MMC_NO_ERROR;
  1396. }
  1397. //Check R1 response and return the result
  1398. int sd_check_response_r1(unsigned char cmd, SD_Response_R1_t * r1)
  1399. {
  1400. #ifdef SD_MMC_HW_CONTROL
  1401. if(SD_WORK_MODE == CARD_HW_MODE)
  1402. {
  1403. return SD_MMC_NO_ERROR;
  1404. //if(0)//if ((r1->command & 0x3F) != cmd)
  1405. }
  1406. #endif
  1407. #ifdef SD_MMC_SW_CONTROL
  1408. if(SD_WORK_MODE == CARD_SW_MODE)
  1409. {
  1410. if (r1->command != cmd)
  1411. return SD_MMC_ERROR_HEADER_MISMATCH;
  1412. if (r1->card_status.OUT_OF_RANGE)
  1413. return SD_MMC_ERROR_OUT_OF_RANGE;
  1414. else if (r1->card_status.ADDRESS_ERROR)
  1415. return SD_MMC_ERROR_ADDRESS;
  1416. else if (r1->card_status.BLOCK_LEN_ERROR)
  1417. return SD_MMC_ERROR_BLOCK_LEN;
  1418. else if (r1->card_status.ERASE_SEQ_ERROR)
  1419. return SD_MMC_ERROR_ERASE_SEQ;
  1420. else if (r1->card_status.ERASE_PARAM)
  1421. return SD_MMC_ERROR_ERASE_PARAM;
  1422. else if (r1->card_status.WP_VIOLATION)
  1423. return SD_MMC_ERROR_WP_VIOLATION;
  1424. else if (r1->card_status.CARD_IS_LOCKED)
  1425. return SD_ERROR_CARD_IS_LOCKED;
  1426. else if (r1->card_status.LOCK_UNLOCK_FAILED)
  1427. return SD_ERROR_LOCK_UNLOCK_FAILED;
  1428. else if (r1->card_status.COM_CRC_ERROR)
  1429. return SD_MMC_ERROR_COM_CRC;
  1430. else if (r1->card_status.ILLEGAL_COMMAND)
  1431. return SD_MMC_ERROR_ILLEGAL_COMMAND;
  1432. else if (r1->card_status.CARD_ECC_FAILED)
  1433. return SD_ERROR_CARD_ECC_FAILED;
  1434. else if (r1->card_status.CC_ERROR)
  1435. return SD_ERROR_CC;
  1436. else if (r1->card_status.ERROR)
  1437. return SD_MMC_ERROR_GENERAL;
  1438. else if (r1->card_status.CID_CSD_OVERWRITE)
  1439. return SD_MMC_ERROR_CID_CSD_OVERWRITE;
  1440. else if (r1->card_status.AKE_SEQ_ERROR)
  1441. return SD_ERROR_AKE_SEQ;
  1442. }
  1443. #endif
  1444. return SD_MMC_NO_ERROR;
  1445. }
  1446. //Check R3 response and return the result
  1447. int sd_check_response_r3(unsigned char cmd, SD_Response_R3_t * r3)
  1448. {
  1449. #ifdef SD_MMC_HW_CONTROL
  1450. if(SD_WORK_MODE == CARD_HW_MODE)
  1451. {
  1452. if(0)//if ((r3->reserved1 & 0x3F) != 0x3F)
  1453. return SD_MMC_ERROR_HEADER_MISMATCH;
  1454. }
  1455. #endif
  1456. #ifdef SD_MMC_SW_CONTROL
  1457. if(SD_WORK_MODE == CARD_SW_MODE)
  1458. {
  1459. if ((r3->reserved1 != 0x3F))// || (r3->reserved2 != 0x7F))
  1460. return SD_MMC_ERROR_HEADER_MISMATCH;
  1461. }
  1462. #endif
  1463. return SD_MMC_NO_ERROR;
  1464. }
  1465. int sd_check_response_r4(unsigned char cmd, SDIO_Response_R4_t * r4)
  1466. {
  1467. #ifdef SD_MMC_HW_CONTROL
  1468. if(SD_WORK_MODE == CARD_HW_MODE)
  1469. {
  1470. if(0)//if ((r3->reserved1 & 0x3F) != 0x3F)
  1471. return SD_MMC_ERROR_HEADER_MISMATCH;
  1472. }
  1473. #endif
  1474. #ifdef SD_MMC_SW_CONTROL
  1475. if(SD_WORK_MODE == CARD_SW_MODE)
  1476. {
  1477. if ((r4->reserved1 != 0x3F))// || (r3->reserved2 != 0x7F))
  1478. return SD_MMC_ERROR_HEADER_MISMATCH;
  1479. }
  1480. #endif
  1481. return SD_MMC_NO_ERROR;
  1482. }
  1483. int sd_check_response_r5(unsigned char cmd, SDIO_RW_CMD_Response_R5_t * r5)
  1484. {
  1485. #ifdef SD_MMC_HW_CONTROL
  1486. if(SD_WORK_MODE == CARD_HW_MODE)
  1487. {
  1488. if(0)//if ((r6->command & 0x3F) != SD_MMC_SEND_RELATIVE_ADDR)
  1489. return SD_MMC_ERROR_HEADER_MISMATCH;
  1490. }
  1491. #endif
  1492. #ifdef SD_MMC_SW_CONTROL
  1493. if(SD_WORK_MODE == CARD_SW_MODE)
  1494. {
  1495. if ((r5->command == IO_RW_DIRECT) || (r5->command == IO_RW_EXTENDED))
  1496. return SD_MMC_NO_ERROR;
  1497. return SD_MMC_ERROR_HEADER_MISMATCH;
  1498. }
  1499. #endif
  1500. return SD_MMC_NO_ERROR;
  1501. }
  1502. //Check R6 response and return the result
  1503. int sd_check_response_r6(unsigned char cmd, SD_Response_R6_t * r6)
  1504. {
  1505. #ifdef SD_MMC_HW_CONTROL
  1506. if(SD_WORK_MODE == CARD_HW_MODE)
  1507. {
  1508. if(0)//if ((r6->command & 0x3F) != SD_MMC_SEND_RELATIVE_ADDR)
  1509. return SD_MMC_ERROR_HEADER_MISMATCH;
  1510. }
  1511. #endif
  1512. #ifdef SD_MMC_SW_CONTROL
  1513. if(SD_WORK_MODE == CARD_SW_MODE)
  1514. {
  1515. if (r6->command != SD_MMC_SEND_RELATIVE_ADDR)
  1516. return SD_MMC_ERROR_HEADER_MISMATCH;
  1517. }
  1518. #endif
  1519. return SD_MMC_NO_ERROR;
  1520. }
  1521. int sd_check_response_r7(unsigned char cmd, SD_Response_R7_t * r7)
  1522. {
  1523. #ifdef SD_MMC_HW_CONTROL
  1524. if(SD_WORK_MODE == CARD_HW_MODE)
  1525. {
  1526. if(0)//if ((r6->command & 0x3F) != SD_MMC_SEND_RELATIVE_ADDR)
  1527. return SD_MMC_ERROR_HEADER_MISMATCH;
  1528. }
  1529. #endif
  1530. #ifdef SD_MMC_SW_CONTROL
  1531. if(SD_WORK_MODE == CARD_SW_MODE)
  1532. {
  1533. if (r7->command != SD_SEND_IF_COND)
  1534. return SD_MMC_ERROR_HEADER_MISMATCH;
  1535. }
  1536. #endif
  1537. return SD_MMC_NO_ERROR;
  1538. }
  1539. //Check R2_CID response and return the result
  1540. int sd_check_response_r2_cid(unsigned char cmd, SD_Response_R2_CID_t * r2_cid)
  1541. {
  1542. #ifdef SD_MMC_HW_CONTROL
  1543. if(SD_WORK_MODE == CARD_HW_MODE)
  1544. {
  1545. if(0)//if ((r2_cid->reserved & 0x3F) != 0x3F)
  1546. return SD_MMC_ERROR_HEADER_MISMATCH;
  1547. }
  1548. #endif
  1549. #ifdef SD_MMC_SW_CONTROL
  1550. if(SD_WORK_MODE == CARD_SW_MODE)
  1551. {
  1552. if (r2_cid->reserved != 0x3F)
  1553. return SD_MMC_ERROR_HEADER_MISMATCH;
  1554. }
  1555. #endif
  1556. return SD_MMC_NO_ERROR;
  1557. }
  1558. //Check R2_CSD response and return the result
  1559. int sd_check_response_r2_csd(unsigned char cmd, SD_Response_R2_CSD_t * r2_csd)
  1560. {
  1561. #ifdef SD_MMC_HW_CONTROL
  1562. if(SD_WORK_MODE == CARD_HW_MODE)
  1563. {
  1564. if(0)//if ((r2_csd->reserved & 0x3F)!= 0x3F)
  1565. return SD_MMC_ERROR_HEADER_MISMATCH;
  1566. }
  1567. #endif
  1568. #ifdef SD_MMC_SW_CONTROL
  1569. if(SD_WORK_MODE == CARD_SW_MODE)
  1570. {
  1571. if(r2_csd->reserved != 0x3F)
  1572. return SD_MMC_ERROR_HEADER_MISMATCH;
  1573. }
  1574. #endif
  1575. return SD_MMC_NO_ERROR;
  1576. }
  1577. //Check response and return the result
  1578. int sd_check_response(unsigned char cmd, SD_Response_Type_t res_type, unsigned char * res_buf)
  1579. {
  1580. int ret = SD_MMC_NO_ERROR;
  1581. switch(res_type)
  1582. {
  1583. case RESPONSE_R1:
  1584. case RESPONSE_R1B:
  1585. ret = sd_check_response_r1(cmd, (SD_Response_R1_t *)res_buf);
  1586. break;
  1587. case RESPONSE_R3:
  1588. ret = sd_check_response_r3(cmd, (SD_Response_R3_t *)res_buf);
  1589. break;
  1590. case RESPONSE_R4:
  1591. ret = sd_check_response_r4(cmd, (SDIO_Response_R4_t *)res_buf);
  1592. break;
  1593. case RESPONSE_R5:
  1594. ret = sd_check_response_r5(cmd, (SDIO_RW_CMD_Response_R5_t *)res_buf);
  1595. break;
  1596. case RESPONSE_R6:
  1597. ret = sd_check_response_r6(cmd, (SD_Response_R6_t *)res_buf);
  1598. break;
  1599. case RESPONSE_R2_CID:
  1600. ret = sd_check_response_r2_cid(cmd, (SD_Response_R2_CID_t *)res_buf);
  1601. break;
  1602. case RESPONSE_R2_CSD:
  1603. ret = sd_check_response_r2_csd(cmd, (SD_Response_R2_CSD_t *)res_buf);
  1604. break;
  1605. case RESPONSE_NONE:
  1606. break;
  1607. default:
  1608. break;
  1609. }
  1610. return ret;
  1611. }
  1612. static void my_disp_sdhc_regs(void);
  1613. void try_to_fix_error(SD_MMC_Card_Info_t *sd_mmc_info)
  1614. {
  1615. unsigned int sdxc_srst;
  1616. SDXC_PDMA_Reg_t *sdxc_pdma_reg;
  1617. unsigned int sdxc_pdma;
  1618. if ((sd_mmc_info->io_pad_type != SDXC_CARD_0_5) &&
  1619. (sd_mmc_info->io_pad_type != SDXC_BOOT_0_11) &&
  1620. (sd_mmc_info->io_pad_type != SDXC_GPIOX_0_9))
  1621. return;
  1622. printk("try to fix error\n");
  1623. //my_disp_sdhc_regs();
  1624. {
  1625. unsigned int value4, value6, value2, value3;
  1626. value4 = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  1627. value6 = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  1628. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  1629. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  1630. printk("MUX4:[0x%08x]/[0x%02x], MUX6:[0x%08x]/[0x%02x], MUX2:[0x%08x]/[0x%03x], MUX3:[0x%08x]/[0x%02x]\n",
  1631. value4, (value4 >> 26) & 0x1F, value6, (value6 >> 24) & 0x3F, value2, (value2 >> 16) & 0xFFF, value3, (value3 >> 31) & 0x01);
  1632. }
  1633. {
  1634. unsigned int value, value2, value3;
  1635. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  1636. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  1637. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_5);
  1638. printk("MUX2-sdxc:[0x%08x]/[0x%02x], MUX4:[0x%08x]/[0x%02x], MUX5:[0x%08x]/[0x%02x]\n",
  1639. value, (value >> 4) & 0x1F, value2, (value2 >> 26) & 0x1F, value3, (value3 >> 10) & 0x1F);
  1640. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  1641. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  1642. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_8);
  1643. printk("MUX2-sdhc:[0x%08x]/[0x%02x], MUX6:[0x%08x]/[0x%02x], MUX8:[0x%08x]/[0x%02x]\n",
  1644. value, (value >> 10) & 0x3F, value2, (value2 >> 24) & 0x3F, value3, (value3 >> 0) & 0x3F);
  1645. }
  1646. sdxc_pdma = READ_CBUS_REG(SD_REG6_PDMA);
  1647. sdxc_pdma_reg = (void *) &sdxc_pdma;
  1648. sdxc_pdma_reg->rx_manual_flush = 1;
  1649. WRITE_CBUS_REG(SD_REG6_PDMA, sdxc_pdma);
  1650. sdxc_srst = 0x3F; //0x3F -- 0x27 : exclude rx_dphy_srst & tx_dphy_srst
  1651. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  1652. sd_delay_ms(1);
  1653. sdxc_srst = 0x00;
  1654. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  1655. sd_delay_ms(1);
  1656. }
  1657. //Read single block data from SD card
  1658. #ifdef SD_MMC_HW_CONTROL
  1659. int sd_read_single_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf)
  1660. {
  1661. int ret, read_retry_count, read_single_block_hw_failed = 0;
  1662. unsigned long data_addr;
  1663. unsigned char response[MAX_RESPONSE_BYTES];
  1664. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  1665. {
  1666. data_addr = lba;
  1667. }
  1668. else
  1669. {
  1670. data_addr = sd_mmc_info->blk_len;
  1671. data_addr *= lba;
  1672. }
  1673. for(read_retry_count=0; read_retry_count<3; read_retry_count++)
  1674. {
  1675. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_READ_SINGLE_BLOCK, data_addr, RESPONSE_R1, response, data_buf, sd_mmc_info->blk_len, 1);
  1676. if(ret)
  1677. {
  1678. printk(" sd_read_single_block_hw ret %d \n", ret);
  1679. read_single_block_hw_failed++;
  1680. continue;
  1681. }
  1682. else
  1683. break;
  1684. }
  1685. if(read_single_block_hw_failed >= 3)
  1686. return SD_MMC_ERROR_READ_DATA_FAILED;
  1687. if(ret)
  1688. return ret;
  1689. return SD_MMC_NO_ERROR;
  1690. }
  1691. #endif
  1692. //Read single block data from SD card
  1693. #ifdef SD_MMC_SW_CONTROL
  1694. int sd_read_single_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf)
  1695. {
  1696. unsigned long data = 0, res = 0, temp = 0;
  1697. int ret, data_busy = 1, res_busy = 1;
  1698. unsigned long res_cnt = 0, data_cnt = 0, num_nac = 0, num_ncr = 0;
  1699. unsigned short crc16_array[4] = {0, 0, 0, 0};
  1700. unsigned short crc16 = 0;
  1701. unsigned char response[MAX_RESPONSE_BYTES];
  1702. unsigned long data_addr, loop_num;
  1703. int i,j;
  1704. #ifdef SD_MMC_CRC_CHECK
  1705. unsigned short crc_check = 0, crc_check_array[4]={0,0,0,0};
  1706. int error=0;
  1707. //unsigned char *org_buf=data_buf;
  1708. #endif
  1709. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  1710. {
  1711. sd_set_dat0_3_input();
  1712. }
  1713. else
  1714. {
  1715. sd_set_dat0_input();
  1716. }
  1717. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  1718. {
  1719. data_addr = lba;
  1720. }
  1721. else
  1722. {
  1723. data_addr = sd_mmc_info->blk_len;
  1724. data_addr *= lba;
  1725. }
  1726. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_READ_SINGLE_BLOCK, data_addr, RESPONSE_NONE, 0);
  1727. if(ret)
  1728. return ret;
  1729. sd_clear_response(response);
  1730. sd_delay_clocks_z(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  1731. sd_set_cmd_input();
  1732. //wait until both response and data is valid
  1733. do
  1734. {
  1735. sd_clk_transfer_low();
  1736. res = sd_get_cmd_value();
  1737. data = sd_get_dat0_value();
  1738. if (res_busy)
  1739. {
  1740. if (res)
  1741. num_ncr++;
  1742. else
  1743. res_busy = 0;
  1744. }
  1745. else
  1746. {
  1747. if (res_cnt < (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8))
  1748. {
  1749. response[res_cnt>>3] <<= 1;
  1750. response[res_cnt>>3] |= res;
  1751. res_cnt++;
  1752. }
  1753. }
  1754. if (data_busy)
  1755. {
  1756. if (data)
  1757. num_nac++;
  1758. else
  1759. data_busy = 0;
  1760. }
  1761. else
  1762. {
  1763. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  1764. {
  1765. data = sd_get_dat0_3_value();
  1766. temp <<= 4;
  1767. temp |= data;
  1768. #ifdef SD_MMC_CRC_CHECK
  1769. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  1770. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  1771. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  1772. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  1773. #endif
  1774. if((data_cnt & 0x01) == 1)
  1775. {
  1776. #ifdef AMLOGIC_CHIP_SUPPORT
  1777. if((unsigned long)data_buf == 0x3400000)
  1778. {
  1779. WRITE_BYTE_TO_FIFO(temp);
  1780. }
  1781. else
  1782. #endif
  1783. {
  1784. *data_buf = temp;
  1785. data_buf++;
  1786. }
  1787. temp = 0; //one byte received, clear temp varialbe
  1788. }
  1789. }
  1790. else //only data0 lines
  1791. {
  1792. data = sd_get_dat0_value();
  1793. temp <<= 1;
  1794. temp |= data;
  1795. if((data_cnt & 0x07) == 7)
  1796. {
  1797. #ifdef AMLOGIC_CHIP_SUPPORT
  1798. if((unsigned)data_buf == 0x3400000)
  1799. {
  1800. WRITE_BYTE_TO_FIFO(temp);
  1801. }
  1802. else
  1803. #endif
  1804. {
  1805. *data_buf = temp;
  1806. data_buf++;
  1807. }
  1808. #ifdef SD_MMC_CRC_CHECK
  1809. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  1810. #endif
  1811. temp = 0; //one byte received, clear temp varialbe
  1812. }
  1813. }
  1814. data_cnt++;
  1815. }
  1816. sd_clk_transfer_high();
  1817. if(!res_busy && !data_busy)
  1818. {
  1819. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  1820. {
  1821. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x01) == 0))
  1822. {
  1823. data_cnt >>= 1;
  1824. break;
  1825. }
  1826. }
  1827. else
  1828. {
  1829. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x07) == 0))
  1830. {
  1831. data_cnt >>= 3;
  1832. break;
  1833. }
  1834. }
  1835. }
  1836. }while((num_ncr < SD_MMC_TIME_NCR_MAX) && (num_nac < sd_mmc_info->clks_nac));
  1837. if((num_ncr >= SD_MMC_TIME_NCR_MAX) || (num_nac >= sd_mmc_info->clks_nac))
  1838. return SD_MMC_ERROR_TIMEOUT;
  1839. //Read data and response
  1840. loop_num = sd_mmc_info->blk_len;
  1841. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  1842. {
  1843. #ifdef AMLOGIC_CHIP_SUPPORT
  1844. if((unsigned long)data_buf == 0x3400000)
  1845. {
  1846. for(; data_cnt < loop_num; data_cnt++)
  1847. {
  1848. temp = 0; //clear temp varialbe
  1849. for(i = 0; i < 2; i++)
  1850. {
  1851. sd_clk_transfer_low();
  1852. data = sd_get_dat0_3_value();
  1853. temp <<= 4;
  1854. temp |= data;
  1855. sd_clk_transfer_high();
  1856. #ifdef SD_MMC_CRC_CHECK
  1857. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  1858. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  1859. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  1860. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  1861. #endif
  1862. }
  1863. WRITE_BYTE_TO_FIFO(temp);
  1864. }
  1865. }
  1866. else
  1867. #endif
  1868. {
  1869. for(; data_cnt < loop_num; data_cnt++)
  1870. {
  1871. temp = 0; //clear temp varialbe
  1872. for(i = 0; i < 2; i++)
  1873. {
  1874. sd_clk_transfer_low();
  1875. data = sd_get_dat0_3_value();
  1876. temp <<= 4;
  1877. temp |= data;
  1878. sd_clk_transfer_high();
  1879. #ifdef SD_MMC_CRC_CHECK
  1880. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  1881. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  1882. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  1883. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  1884. #endif
  1885. }
  1886. *data_buf = temp;
  1887. data_buf++;
  1888. }
  1889. }
  1890. //Read CRC16 data
  1891. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  1892. {
  1893. sd_clk_transfer_low();
  1894. crc16_array[0] <<= 1;
  1895. crc16_array[1] <<= 1;
  1896. crc16_array[2] <<= 1;
  1897. crc16_array[3] <<= 1;
  1898. data = sd_get_dat0_3_value();
  1899. crc16_array[0] |= (data & 0x01);
  1900. crc16_array[1] |= ((data >> 1) & 0x01);
  1901. crc16_array[2] |= ((data >> 2) & 0x01);
  1902. crc16_array[3] |= ((data >> 3) & 0x01);
  1903. sd_clk_transfer_high();
  1904. }
  1905. #ifdef SD_MMC_CRC_CHECK
  1906. for(i=0; i<4; i++)
  1907. {
  1908. //crc_check_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  1909. if(crc16_array[i] != crc_check_array[i])
  1910. {
  1911. error = SD_MMC_ERROR_DATA_CRC;
  1912. break;
  1913. }
  1914. }
  1915. #endif
  1916. }
  1917. else //only data0 lines
  1918. {
  1919. #ifdef AMLOGIC_CHIP_SUPPORT
  1920. if((unsigned)data_buf == 0x3400000)
  1921. {
  1922. for(; data_cnt < loop_num; data_cnt++)
  1923. {
  1924. temp = 0; //clear temp varialbe
  1925. for(j = 0; j < 8; j++)
  1926. {
  1927. sd_clk_transfer_low();
  1928. data = sd_get_dat0_value();
  1929. temp <<= 1;
  1930. temp |= data;
  1931. sd_clk_transfer_high();
  1932. }
  1933. WRITE_BYTE_TO_FIFO(temp);
  1934. #ifdef SD_MMC_CRC_CHECK
  1935. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  1936. #endif
  1937. }
  1938. }
  1939. else
  1940. #endif
  1941. {
  1942. for(; data_cnt < loop_num; data_cnt++)
  1943. {
  1944. temp = 0; //clear temp varialbe
  1945. for(j = 0; j < 8; j++)
  1946. {
  1947. sd_clk_transfer_low();
  1948. data = sd_get_dat0_value();
  1949. temp <<= 1;
  1950. temp |= data;
  1951. sd_clk_transfer_high();
  1952. }
  1953. *data_buf = temp;
  1954. data_buf++;
  1955. #ifdef SD_MMC_CRC_CHECK
  1956. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  1957. #endif
  1958. }
  1959. }
  1960. //Read CRC16 data
  1961. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  1962. {
  1963. sd_clk_transfer_low();
  1964. data = sd_get_dat0_value();
  1965. crc16 <<= 1;
  1966. crc16 |= data;
  1967. sd_clk_transfer_high();
  1968. }
  1969. #ifdef SD_MMC_CRC_CHECK
  1970. if(crc16 != crc_check)
  1971. error = SD_MMC_ERROR_DATA_CRC;
  1972. #endif
  1973. }
  1974. sd_clk_transfer_low(); //for end bit
  1975. sd_clk_transfer_high();
  1976. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC); //Clock delay, Z type
  1977. #ifdef SD_MMC_CRC_CHECK
  1978. if(error == SD_MMC_ERROR_DATA_CRC)
  1979. {
  1980. //#ifdef SD_MMC_DEBUG
  1981. //Debug_Printf("#%s error occured in sd_read_single_block()!\n", sd_error_to_string(error));
  1982. //#endif
  1983. return error;
  1984. }
  1985. #endif
  1986. return SD_MMC_NO_ERROR;
  1987. }
  1988. #endif
  1989. #ifdef SD_MMC_HW_CONTROL
  1990. int sd_read_multi_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf)
  1991. {
  1992. int ret, read_retry_count, i, read_multi_block_hw_failed = 0;
  1993. unsigned long data_addr, lba_num, data_offset = 0;
  1994. unsigned char response[MAX_RESPONSE_BYTES];
  1995. unsigned char * orig_phy_buf = sd_mmc_info->sd_mmc_phy_buf;
  1996. unsigned char * orig_virt_buf = sd_mmc_info->sd_mmc_buf;
  1997. if(lba_cnt == 0)
  1998. return SD_MMC_ERROR_BLOCK_LEN;
  1999. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2000. {
  2001. data_addr = lba;
  2002. }
  2003. else
  2004. {
  2005. data_addr = sd_mmc_info->blk_len;
  2006. data_addr *= lba;
  2007. }
  2008. if(sd_mmc_info->read_multi_block_failed == 0)
  2009. {
  2010. while(lba_cnt)
  2011. {
  2012. if(lba_cnt > sd_mmc_info->max_blk_count)
  2013. lba_num = sd_mmc_info->max_blk_count;
  2014. else
  2015. lba_num = lba_cnt;
  2016. if((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2017. data_addr += data_offset/512;
  2018. else
  2019. data_addr += data_offset;
  2020. data_buf += data_offset;
  2021. sd_mmc_info->sd_mmc_phy_buf += data_offset;
  2022. for(read_retry_count=0; read_retry_count<3; read_retry_count++)
  2023. {
  2024. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_READ_MULTIPLE_BLOCK, data_addr, RESPONSE_R1, response, data_buf, sd_mmc_info->blk_len*lba_num, 1);
  2025. if(ret)
  2026. {
  2027. read_multi_block_hw_failed++;
  2028. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2029. if(ret)
  2030. goto out;
  2031. else {
  2032. try_to_fix_error(sd_mmc_info);
  2033. continue;
  2034. }
  2035. }
  2036. else
  2037. break;
  2038. }
  2039. if(read_multi_block_hw_failed >= 3)
  2040. {
  2041. printk("read multi failed, switch to single afterward\n");
  2042. sd_mmc_info->read_multi_block_failed = 1;
  2043. ret = SD_MMC_ERROR_READ_DATA_FAILED;
  2044. goto out;
  2045. }
  2046. if(ret)
  2047. {
  2048. goto out;
  2049. }
  2050. else //fix stop
  2051. {
  2052. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2053. if(ret)
  2054. goto out;
  2055. }
  2056. lba_cnt -= lba_num;
  2057. data_offset = lba_num*512;
  2058. }
  2059. }
  2060. else
  2061. {
  2062. for(i=0; i<lba_cnt; i++)
  2063. {
  2064. ret = sd_read_single_block_hw(sd_mmc_info, lba++, data_buf);
  2065. if(ret)
  2066. goto out;
  2067. #ifdef AMLOGIC_CHIP_SUPPORT
  2068. data_buf += (((unsigned long)data_buf == 0x3400000) ? 0 : sd_mmc_info->blk_len);
  2069. #else
  2070. BUG_ON(512 != sd_mmc_info->blk_len);/*convert blk_len in sd_identify_process*/
  2071. data_offset = sd_mmc_info->blk_len;
  2072. data_buf += data_offset;
  2073. sd_mmc_info->sd_mmc_phy_buf += data_offset;
  2074. sd_mmc_info->sd_mmc_buf += data_offset;
  2075. #endif
  2076. }
  2077. }
  2078. ret = SD_MMC_NO_ERROR;
  2079. out :
  2080. sd_mmc_info->sd_mmc_phy_buf = orig_phy_buf;
  2081. sd_mmc_info->sd_mmc_buf = orig_virt_buf;
  2082. return ret;
  2083. }
  2084. #endif
  2085. #ifdef SD_MMC_SW_CONTROL
  2086. int sd_read_multi_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf)
  2087. {
  2088. unsigned long data = 0, res = 0, temp = 0;
  2089. int ret, data_busy = 1, res_busy = 1;
  2090. unsigned long res_cnt = 0, data_cnt = 0, num_nac = 0, num_ncr = 0;
  2091. unsigned short crc16_array[4] = {0, 0, 0, 0};
  2092. unsigned short crc16 = 0;
  2093. unsigned char response[MAX_RESPONSE_BYTES];
  2094. unsigned long data_addr,loop_num,blk_cnt;
  2095. int i,j;
  2096. #ifdef SD_MMC_CRC_CHECK
  2097. unsigned short crc_check = 0, crc_check_array[4]={0,0,0,0};
  2098. int error=0;
  2099. unsigned char *org_buf=data_buf;
  2100. #endif
  2101. if(lba_cnt == 0)
  2102. return SD_MMC_ERROR_BLOCK_LEN;
  2103. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2104. {
  2105. sd_set_dat0_3_input();
  2106. }
  2107. else
  2108. {
  2109. sd_set_dat0_input();
  2110. }
  2111. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2112. {
  2113. data_addr = lba;
  2114. }
  2115. else
  2116. {
  2117. data_addr = sd_mmc_info->blk_len;
  2118. data_addr *= lba;
  2119. }
  2120. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_READ_MULTIPLE_BLOCK, data_addr, RESPONSE_NONE, 0);
  2121. if(ret)
  2122. return ret;
  2123. sd_clear_response(response);
  2124. sd_delay_clocks_z(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  2125. sd_set_cmd_input();
  2126. //wait until both response and data is valid
  2127. do
  2128. {
  2129. sd_clk_transfer_low();
  2130. res = sd_get_cmd_value();
  2131. data = sd_get_dat0_value();
  2132. if (res_busy)
  2133. {
  2134. if (res)
  2135. num_ncr++;
  2136. else
  2137. res_busy = 0;
  2138. }
  2139. else
  2140. {
  2141. if (res_cnt < (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8))
  2142. {
  2143. response[res_cnt>>3] <<= 1;
  2144. response[res_cnt>>3] |= res;
  2145. res_cnt++;
  2146. }
  2147. }
  2148. if (data_busy)
  2149. {
  2150. if (data)
  2151. num_nac++;
  2152. else
  2153. data_busy = 0;
  2154. }
  2155. else
  2156. {
  2157. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  2158. {
  2159. data = sd_get_dat0_3_value();
  2160. temp <<= 4;
  2161. temp |= data;
  2162. #ifdef SD_MMC_CRC_CHECK
  2163. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  2164. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  2165. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  2166. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  2167. #endif
  2168. if((data_cnt & 0x01) == 1)
  2169. {
  2170. #ifdef AMLOGIC_CHIP_SUPPORT
  2171. if((unsigned long)data_buf == 0x3400000)
  2172. {
  2173. WRITE_BYTE_TO_FIFO(temp);
  2174. }
  2175. else
  2176. #endif
  2177. {
  2178. *data_buf = temp;
  2179. data_buf++;
  2180. }
  2181. temp = 0; //one byte received, clear temp varialbe
  2182. }
  2183. }
  2184. else //only data0 lines
  2185. {
  2186. data = sd_get_dat0_value();
  2187. temp <<= 1;
  2188. temp |= data;
  2189. if((data_cnt & 0x07) == 7)
  2190. {
  2191. #ifdef AMLOGIC_CHIP_SUPPORT
  2192. if((unsigned)data_buf == 0x3400000)
  2193. {
  2194. WRITE_BYTE_TO_FIFO(temp);
  2195. }
  2196. else
  2197. #endif
  2198. {
  2199. *data_buf = temp;
  2200. data_buf++;
  2201. }
  2202. #ifdef SD_MMC_CRC_CHECK
  2203. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  2204. #endif
  2205. temp = 0; //one byte received, clear temp varialbe
  2206. }
  2207. }
  2208. data_cnt++;
  2209. }
  2210. sd_clk_transfer_high();
  2211. if(!res_busy && !data_busy)
  2212. {
  2213. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  2214. {
  2215. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x01) == 0))
  2216. {
  2217. data_cnt >>= 1;
  2218. break;
  2219. }
  2220. }
  2221. else
  2222. {
  2223. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x07) == 0))
  2224. {
  2225. data_cnt >>= 3;
  2226. break;
  2227. }
  2228. }
  2229. }
  2230. }while((num_ncr < SD_MMC_TIME_NCR_MAX) && (num_nac < sd_mmc_info->clks_nac));
  2231. if((num_ncr >= SD_MMC_TIME_NCR_MAX) || (num_nac >= sd_mmc_info->clks_nac))
  2232. return SD_MMC_ERROR_TIMEOUT;
  2233. //Read all data blocks
  2234. loop_num = sd_mmc_info->blk_len;
  2235. for (blk_cnt = 0; blk_cnt < lba_cnt; blk_cnt++)
  2236. {
  2237. //wait until data is valid
  2238. num_nac = 0;
  2239. do
  2240. {
  2241. if(!data_busy)
  2242. break;
  2243. sd_clk_transfer_low();
  2244. data = sd_get_dat0_value();
  2245. if(data)
  2246. {
  2247. num_nac++;
  2248. }
  2249. else
  2250. {
  2251. data_busy = 0;
  2252. }
  2253. sd_clk_transfer_high();
  2254. }while(data_busy && (num_nac < sd_mmc_info->clks_nac));
  2255. if(num_nac >= sd_mmc_info->clks_nac)
  2256. return SD_MMC_ERROR_TIMEOUT;
  2257. //Read data
  2258. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  2259. {
  2260. #ifdef AMLOGIC_CHIP_SUPPORT
  2261. if((unsigned long)data_buf == 0x3400000)
  2262. {
  2263. for(; data_cnt < loop_num; data_cnt++)
  2264. {
  2265. temp = 0; //clear temp varialbe
  2266. for(i = 0; i < 2; i++)
  2267. {
  2268. sd_clk_transfer_low();
  2269. data = sd_get_dat0_3_value();
  2270. temp <<= 4;
  2271. temp |= data;
  2272. sd_clk_transfer_high();
  2273. #ifdef SD_MMC_CRC_CHECK
  2274. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  2275. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  2276. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  2277. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  2278. #endif
  2279. }
  2280. WRITE_BYTE_TO_FIFO(temp);
  2281. }
  2282. }
  2283. else
  2284. #endif
  2285. {
  2286. for(; data_cnt < loop_num; data_cnt++)
  2287. {
  2288. temp = 0; //clear temp varialbe
  2289. for(i = 0; i < 2; i++)
  2290. {
  2291. sd_clk_transfer_low();
  2292. data = sd_get_dat0_3_value();
  2293. temp <<= 4;
  2294. temp |= data;
  2295. sd_clk_transfer_high();
  2296. #ifdef SD_MMC_CRC_CHECK
  2297. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  2298. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  2299. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  2300. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  2301. #endif
  2302. }
  2303. *data_buf = temp;
  2304. data_buf++;
  2305. }
  2306. }
  2307. //Read CRC16 data
  2308. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  2309. {
  2310. sd_clk_transfer_low();
  2311. crc16_array[0] <<= 1;
  2312. crc16_array[1] <<= 1;
  2313. crc16_array[2] <<= 1;
  2314. crc16_array[3] <<= 1;
  2315. data = sd_get_dat0_3_value();
  2316. crc16_array[0] |= (data & 0x01);
  2317. crc16_array[1] |= ((data >> 1) & 0x01);
  2318. crc16_array[2] |= ((data >> 2) & 0x01);
  2319. crc16_array[3] |= ((data >> 3) & 0x01);
  2320. sd_clk_transfer_high();
  2321. }
  2322. #ifdef SD_MMC_CRC_CHECK
  2323. for(i=0; i<4; i++)
  2324. {
  2325. //crc_check_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  2326. if(crc16_array[i] != crc_check_array[i])
  2327. {
  2328. error = SD_MMC_ERROR_DATA_CRC;
  2329. break;
  2330. }
  2331. }
  2332. #endif
  2333. }
  2334. else //only data0 lines
  2335. {
  2336. #ifdef AMLOGIC_CHIP_SUPPORT
  2337. if((unsigned long)data_buf == 0x3400000)
  2338. {
  2339. for(; data_cnt < loop_num; data_cnt++)
  2340. {
  2341. temp = 0; //clear temp varialbe
  2342. for(j = 0; j < 8; j++)
  2343. {
  2344. sd_clk_transfer_low();
  2345. data = sd_get_dat0_value();
  2346. temp <<= 1;
  2347. temp |= data;
  2348. sd_clk_transfer_high();
  2349. }
  2350. WRITE_BYTE_TO_FIFO(temp);
  2351. #ifdef SD_MMC_CRC_CHECK
  2352. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  2353. #endif
  2354. }
  2355. }
  2356. else
  2357. #endif
  2358. {
  2359. for(; data_cnt < loop_num; data_cnt++)
  2360. {
  2361. temp = 0; //clear temp varialbe
  2362. for(j = 0; j < 8; j++)
  2363. {
  2364. sd_clk_transfer_low();
  2365. data = sd_get_dat0_value();
  2366. temp <<= 1;
  2367. temp |= data;
  2368. sd_clk_transfer_high();
  2369. }
  2370. *data_buf = temp;
  2371. data_buf++;
  2372. #ifdef SD_MMC_CRC_CHECK
  2373. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  2374. #endif
  2375. }
  2376. }
  2377. //Read CRC16 data
  2378. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  2379. {
  2380. sd_clk_transfer_low();
  2381. data = sd_get_dat0_value();
  2382. crc16 <<= 1;
  2383. crc16 |= data;
  2384. sd_clk_transfer_high();
  2385. }
  2386. #ifdef SD_MMC_CRC_CHECK
  2387. if(crc16 != crc_check)
  2388. error = SD_MMC_ERROR_DATA_CRC;
  2389. #endif
  2390. }
  2391. sd_clk_transfer_low(); //for end bit
  2392. sd_clk_transfer_high();
  2393. data_busy = 1;
  2394. data_cnt = 0;
  2395. #ifdef SD_MMC_CRC_CHECK
  2396. org_buf = data_buf;
  2397. crc_check = 0;
  2398. crc_check_array[0] = crc_check_array[1] = crc_check_array[2] = crc_check_array[3] = 0;
  2399. #endif
  2400. }
  2401. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC); //Clock delay, Z type
  2402. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response);
  2403. #ifdef SD_MMC_CRC_CHECK
  2404. if(error == SD_MMC_ERROR_DATA_CRC)
  2405. {
  2406. //#ifdef SD_MMC_DEBUG
  2407. //Debug_Printf("#%s error occured in sd_read_multi_block()!\n", sd_error_to_string(error));
  2408. //#endif
  2409. return error;
  2410. }
  2411. #endif
  2412. return ret;
  2413. }
  2414. #endif
  2415. #ifdef SD_MMC_HW_CONTROL
  2416. int sd_write_single_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf)
  2417. {
  2418. int ret, write_retry_count;
  2419. unsigned long data_addr;
  2420. unsigned char response[MAX_RESPONSE_BYTES];
  2421. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  2422. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2423. {
  2424. data_addr = lba;
  2425. }
  2426. else
  2427. {
  2428. data_addr = sd_mmc_info->blk_len;
  2429. data_addr *= lba;
  2430. }
  2431. for(write_retry_count=0; write_retry_count<4; write_retry_count++)
  2432. {
  2433. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_WRITE_BLOCK, data_addr, RESPONSE_R1, response, data_buf, sd_mmc_info->blk_len, 1);
  2434. if(ret == SD_MMC_ERROR_DATA_CRC || ret == SD_MMC_ERROR_COM_CRC)
  2435. {
  2436. if(sd_mmc_info->spec_version || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  2437. {
  2438. memset(status_data_buf, 0, 64);
  2439. #ifdef SD_MMC_HW_CONTROL
  2440. if(SD_WORK_MODE == CARD_HW_MODE)
  2441. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  2442. #endif
  2443. }
  2444. //for some sdhc card write problem on 7216 picframe
  2445. continue;
  2446. }
  2447. else
  2448. {
  2449. break;
  2450. }
  2451. }
  2452. if(write_retry_count >= 4)
  2453. return SD_MMC_ERROR_DATA_CRC;
  2454. if(ret)
  2455. return ret;
  2456. return SD_MMC_NO_ERROR;
  2457. }
  2458. #endif
  2459. #ifdef SD_MMC_SW_CONTROL
  2460. int sd_write_single_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned char * data_buf)
  2461. {
  2462. int ret, i, j;
  2463. unsigned long crc_status, data;
  2464. unsigned long data_cnt = 0;
  2465. unsigned char * org_buf = data_buf;
  2466. unsigned short crc16_array[4] = {0, 0, 0, 0};
  2467. unsigned short crc16;
  2468. unsigned char response[MAX_RESPONSE_BYTES];
  2469. unsigned long data_addr,loop_num;
  2470. //Set data lines busy
  2471. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2472. {
  2473. sd_set_dat0_3_output();
  2474. sd_clk_transfer_low();
  2475. sd_set_dat0_3_value(0x0F);
  2476. sd_clk_transfer_high();
  2477. }
  2478. else
  2479. {
  2480. sd_set_dat0_output();
  2481. sd_clk_transfer_low();
  2482. sd_set_dat0_value(0x01);
  2483. sd_clk_transfer_high();
  2484. }
  2485. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2486. {
  2487. data_addr = lba;
  2488. }
  2489. else
  2490. {
  2491. data_addr = sd_mmc_info->blk_len;
  2492. data_addr *= lba;
  2493. }
  2494. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_WRITE_BLOCK, data_addr, RESPONSE_R1, response);
  2495. if(ret)
  2496. return ret;
  2497. //Nwr cycles delay
  2498. sd_delay_clocks_h(sd_mmc_info, SD_MMC_TIME_NWR);
  2499. //Start bit
  2500. sd_clk_transfer_low();
  2501. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2502. {
  2503. sd_set_dat0_3_value(0x00);
  2504. }
  2505. else
  2506. {
  2507. sd_set_dat0_value(0x00);
  2508. }
  2509. sd_clk_transfer_high();
  2510. //Write data
  2511. loop_num = sd_mmc_info->blk_len;
  2512. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2513. {
  2514. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  2515. {
  2516. for(i=1; i>=0; i--)
  2517. {
  2518. sd_clk_transfer_low();
  2519. data = (*data_buf >> (i<<2)) & 0x0F;
  2520. sd_set_dat0_3_value(data);
  2521. sd_clk_transfer_high();
  2522. }
  2523. data_buf++;
  2524. }
  2525. //Caculate CRC16 value and write to line
  2526. for(i=0; i<4; i++)
  2527. {
  2528. crc16_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  2529. }
  2530. //Write CRC16
  2531. for(i=15; i>=0; i--)
  2532. {
  2533. sd_clk_transfer_low();
  2534. data = 0;
  2535. for(j=3; j>=0; j--)
  2536. {
  2537. data <<= 1;
  2538. data |= (crc16_array[j] >> i) & 0x0001;
  2539. }
  2540. sd_set_dat0_3_value(data);
  2541. sd_clk_transfer_high();
  2542. }
  2543. }
  2544. else //only dat0 line
  2545. {
  2546. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  2547. {
  2548. for(i=7; i>=0; i--)
  2549. {
  2550. sd_clk_transfer_low();
  2551. data = (*data_buf >> i) & 0x01;
  2552. sd_set_dat0_value(data);
  2553. sd_clk_transfer_high();
  2554. }
  2555. data_buf++;
  2556. }
  2557. //Caculate CRC16 value and write to line
  2558. crc16 = sd_cal_crc16(org_buf, sd_mmc_info->blk_len);
  2559. //Write CRC16
  2560. for(i=15; i>=0; i--)
  2561. {
  2562. sd_clk_transfer_low();
  2563. data = (crc16 >> i) & 0x0001;
  2564. sd_set_dat0_value(data);
  2565. sd_clk_transfer_high();
  2566. }
  2567. }
  2568. //End bit
  2569. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2570. {
  2571. sd_clk_transfer_low();
  2572. sd_set_dat0_3_value(0x0F);
  2573. sd_clk_transfer_high();
  2574. sd_set_dat0_3_input();
  2575. }
  2576. else
  2577. {
  2578. sd_clk_transfer_low();
  2579. sd_set_dat0_value(0x01);
  2580. sd_clk_transfer_high();
  2581. sd_set_dat0_input();
  2582. }
  2583. sd_delay_clocks_h(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  2584. crc_status = 0;
  2585. //Check CRC status
  2586. sd_set_dat0_input();
  2587. for(i = 0; i < 5; i++)
  2588. {
  2589. sd_clk_transfer_low();
  2590. data = sd_get_dat0_value();
  2591. crc_status <<= 1;
  2592. crc_status |= data;
  2593. sd_clk_transfer_high();
  2594. }
  2595. if (crc_status == 0x0A) //1011, CRC error
  2596. return SD_MMC_ERROR_DATA_CRC;
  2597. else if (crc_status == 0x0F) //1111, Programming error
  2598. return SD_MMC_ERROR_DRIVER_FAILURE;
  2599. //0101, CRC ok
  2600. //Check busy
  2601. sd_start_timer(SD_PROGRAMMING_TIMEOUT);
  2602. do
  2603. {
  2604. sd_clk_transfer_low();
  2605. data = sd_get_dat0_value();
  2606. sd_clk_transfer_high();
  2607. if(data)
  2608. break;
  2609. }while(!sd_check_timer());
  2610. if(sd_check_timeout())
  2611. {
  2612. return SD_MMC_ERROR_TIMEOUT;
  2613. }
  2614. return SD_MMC_NO_ERROR;
  2615. }
  2616. #endif
  2617. #ifdef SD_MMC_HW_CONTROL
  2618. int sd_write_multi_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf)
  2619. {
  2620. int ret, write_retry_count;
  2621. unsigned long lba_num, data_addr, data_offset = 0;
  2622. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  2623. unsigned char response[MAX_RESPONSE_BYTES];
  2624. unsigned char * orig_phy_buf = sd_mmc_info->sd_mmc_phy_buf;
  2625. unsigned char * orig_virt_buf = sd_mmc_info->sd_mmc_buf;
  2626. if(lba_cnt == 0)
  2627. return SD_MMC_ERROR_BLOCK_LEN;
  2628. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2629. {
  2630. data_addr = lba;
  2631. }
  2632. else
  2633. {
  2634. data_addr = sd_mmc_info->blk_len;
  2635. data_addr *= lba;
  2636. }
  2637. if(sd_mmc_info->write_multi_block_failed)
  2638. {
  2639. for(lba_num=lba; lba_num<(lba+lba_cnt); lba_num++)
  2640. {
  2641. ret = sd_write_single_block_hw(sd_mmc_info, lba_num, data_buf);
  2642. if(ret)
  2643. goto out;
  2644. BUG_ON(512 != sd_mmc_info->blk_len);/*convert blk_len in sd_identify_process*/
  2645. data_offset = sd_mmc_info->blk_len;
  2646. data_buf += data_offset;
  2647. sd_mmc_info->sd_mmc_phy_buf += data_offset;
  2648. sd_mmc_info->sd_mmc_buf += data_offset;
  2649. }
  2650. }
  2651. else
  2652. {
  2653. while(lba_cnt)
  2654. {
  2655. if(lba_cnt > sd_mmc_info->max_blk_count)
  2656. lba_num = sd_mmc_info->max_blk_count;
  2657. else
  2658. lba_num = lba_cnt;
  2659. /*
  2660. if(sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  2661. {
  2662. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, NULL, 0, 0);
  2663. if (ret)
  2664. goto out;
  2665. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_WR_BLK_ERASE_COUNT, lba_num, RESPONSE_R1, response, NULL, 0, 0);
  2666. if (ret)
  2667. goto out;
  2668. }
  2669. */
  2670. if((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2671. data_addr += data_offset/512;
  2672. else
  2673. data_addr += data_offset;
  2674. data_buf += data_offset;
  2675. sd_mmc_info->sd_mmc_phy_buf += data_offset;
  2676. for(write_retry_count=0; write_retry_count<4; write_retry_count++)
  2677. {
  2678. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_WRITE_MULTIPLE_BLOCK, data_addr, RESPONSE_R1, response, data_buf, lba_num*512, 1);
  2679. if(ret == SD_MMC_ERROR_DATA_CRC || ret == SD_MMC_ERROR_COM_CRC)
  2680. {
  2681. printk("sd write fail case 1\n");
  2682. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2683. if(ret)
  2684. {
  2685. printk("sd write fail case 2\n");
  2686. goto out;
  2687. }
  2688. else
  2689. {
  2690. printk("sd write fail case 3\n");
  2691. if(sd_mmc_info->spec_version || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  2692. {
  2693. /*status should not cover data, get status at data_offset & read data cover it*/
  2694. status_data_buf = sd_mmc_info->sd_mmc_buf+data_offset;
  2695. memset(status_data_buf, 0, 64);
  2696. #ifdef SD_MMC_HW_CONTROL
  2697. if(SD_WORK_MODE == CARD_HW_MODE)
  2698. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  2699. #endif
  2700. //for some sdhc card write problem on 7216 picframe
  2701. }
  2702. continue;
  2703. }
  2704. }
  2705. /*
  2706. else if(ret == SD_MMC_ERROR_TIMEOUT)
  2707. {
  2708. printk("sd write fail case 11\n");
  2709. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2710. if(ret)
  2711. {
  2712. printk("sd write fail case 12\n");
  2713. goto out;
  2714. }
  2715. else
  2716. {
  2717. printk("sd write fail case 13\n");
  2718. continue;
  2719. }
  2720. }
  2721. */
  2722. else if(ret == SD_MMC_ERROR_TIMEOUT)
  2723. {
  2724. printk("sd write fail case 31\n");
  2725. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2726. {
  2727. int i = 10;
  2728. while (ret != SD_MMC_NO_ERROR && i--) {
  2729. msleep(5);
  2730. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2731. }
  2732. if (ret != SD_MMC_NO_ERROR)
  2733. printk("sorryxxx, send STOP cmd failed\n");
  2734. else if (i != 10)
  2735. printk("sendingxxx stop retry %d times\n", 10 - i);
  2736. }
  2737. if(ret)
  2738. {
  2739. printk("sd write fail case 32\n");
  2740. goto out;
  2741. }
  2742. else
  2743. {
  2744. printk("sd write fail case 33\n");
  2745. continue;
  2746. }
  2747. }
  2748. else
  2749. {
  2750. if (ret != SD_MMC_NO_ERROR)
  2751. printk("failed here\n");
  2752. break;
  2753. }
  2754. }
  2755. if(write_retry_count >= 4)
  2756. {
  2757. printk("write multi failed, switch to single afterward\n");
  2758. sd_mmc_info->write_multi_block_failed = 1;
  2759. ret = SD_MMC_ERROR_DATA_CRC;
  2760. goto out;
  2761. }
  2762. if(ret)
  2763. {
  2764. printk("sd write fail case 5, data_addr=%d, lba_num=%d\n", (unsigned int)data_addr, (unsigned int)lba_num);
  2765. goto out;
  2766. }
  2767. else //fix stop
  2768. {
  2769. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2770. {
  2771. int i = 10;
  2772. while (ret != SD_MMC_NO_ERROR && i--) {
  2773. msleep(5);
  2774. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  2775. }
  2776. if (ret != SD_MMC_NO_ERROR)
  2777. printk("sorry, send STOP cmd failed\n");
  2778. else if (i != 10)
  2779. printk("sending stop retry %d times\n", 10 - i);
  2780. }
  2781. if(ret)
  2782. goto out;
  2783. }
  2784. lba_cnt -= lba_num;
  2785. data_offset = lba_num*512;
  2786. }
  2787. }
  2788. ret = SD_MMC_NO_ERROR;
  2789. out :
  2790. sd_mmc_info->sd_mmc_phy_buf = orig_phy_buf;
  2791. sd_mmc_info->sd_mmc_buf = orig_virt_buf;
  2792. return ret;
  2793. }
  2794. #endif
  2795. #ifdef SD_MMC_SW_CONTROL
  2796. int sd_write_multi_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long lba_cnt, unsigned char * data_buf)
  2797. {
  2798. int ret,i,j;
  2799. unsigned long crc_status, data;
  2800. unsigned long data_cnt = 0;
  2801. unsigned char * org_buf = data_buf;
  2802. unsigned short crc16_array[4] = {0, 0, 0, 0};
  2803. unsigned short crc16;
  2804. unsigned char char_mode[4][3] = {{0x10, 0x01, 0},
  2805. {0x20, 0x02, 0},
  2806. {0x40, 0x04, 0},
  2807. {0x80, 0x08, 0}};
  2808. unsigned char response[MAX_RESPONSE_BYTES];
  2809. unsigned long data_addr,loop_num,blk_cnt;
  2810. if(lba_cnt == 0)
  2811. return SD_MMC_ERROR_BLOCK_LEN;
  2812. if (sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  2813. {
  2814. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  2815. if (ret) return ret;
  2816. ret = sd_send_cmd_sw(sd_mmc_info, SD_SET_WR_BLK_ERASE_COUNT, lba_cnt, RESPONSE_R1, response);
  2817. if (ret) return ret;
  2818. }
  2819. //Set data lines busy
  2820. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2821. {
  2822. sd_set_dat0_3_output();
  2823. sd_clk_transfer_low();
  2824. sd_set_dat0_3_value(0x0F);
  2825. sd_clk_transfer_high();
  2826. }
  2827. else
  2828. {
  2829. sd_set_dat0_output();
  2830. sd_clk_transfer_low();
  2831. sd_set_dat0_value(0x01);
  2832. sd_clk_transfer_high();
  2833. }
  2834. if ((sd_mmc_info->card_type == CARD_TYPE_SDHC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  2835. {
  2836. data_addr = lba;
  2837. }
  2838. else
  2839. {
  2840. data_addr = sd_mmc_info->blk_len;
  2841. data_addr *= lba;
  2842. }
  2843. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_WRITE_MULTIPLE_BLOCK, data_addr, RESPONSE_R1, response);
  2844. if(ret)
  2845. return ret;
  2846. loop_num = sd_mmc_info->blk_len;
  2847. for(blk_cnt = 0; blk_cnt < lba_cnt; blk_cnt++)
  2848. {
  2849. org_buf = data_buf;
  2850. //Nwr cycles delay
  2851. sd_delay_clocks_h(sd_mmc_info, SD_MMC_TIME_NWR);
  2852. //Start bit
  2853. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2854. {
  2855. sd_set_dat0_3_output();
  2856. sd_clk_transfer_low();
  2857. sd_set_dat0_3_value(0x00);
  2858. sd_clk_transfer_high();
  2859. }
  2860. else
  2861. {
  2862. sd_set_dat0_output();
  2863. sd_clk_transfer_low();
  2864. sd_set_dat0_value(0x00);
  2865. sd_clk_transfer_high();
  2866. }
  2867. //Write data
  2868. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2869. {
  2870. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  2871. {
  2872. for(i=1; i>=0; i--)
  2873. {
  2874. sd_clk_transfer_low();
  2875. data = (*data_buf >> (i<<2)) & 0x0F;
  2876. sd_set_dat0_3_value(data);
  2877. sd_clk_transfer_high();
  2878. }
  2879. data_buf++;
  2880. }
  2881. //Caculate CRC16 value and write to line
  2882. for(i=0; i<4; i++)
  2883. {
  2884. crc16_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  2885. }
  2886. //Write CRC16
  2887. for(i=15; i>=0; i--)
  2888. {
  2889. sd_clk_transfer_low();
  2890. data = 0;
  2891. for(j=3; j>=0; j--)
  2892. {
  2893. data <<= 1;
  2894. data |= (crc16_array[j] >> i) & 0x0001;
  2895. }
  2896. sd_set_dat0_3_value(data);
  2897. sd_clk_transfer_high();
  2898. }
  2899. }
  2900. else // only dat0 line
  2901. {
  2902. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  2903. {
  2904. for(i=7; i>=0; i--)
  2905. {
  2906. sd_clk_transfer_low();
  2907. data = (*data_buf >> i) & 0x01;
  2908. sd_set_dat0_value(data);
  2909. sd_clk_transfer_high();
  2910. }
  2911. data_buf++;
  2912. }
  2913. //Caculate CRC16 value and write to line
  2914. crc16 = sd_cal_crc16(org_buf, sd_mmc_info->blk_len);
  2915. //Write CRC16
  2916. for(i=15; i>=0; i--)
  2917. {
  2918. sd_clk_transfer_low();
  2919. data = (crc16 >> i) & 0x0001;
  2920. sd_set_dat0_value(data);
  2921. sd_clk_transfer_high();
  2922. }
  2923. }
  2924. //End bit
  2925. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  2926. {
  2927. sd_clk_transfer_low();
  2928. sd_set_dat0_3_value(0x0F);
  2929. sd_clk_transfer_high();
  2930. sd_set_dat0_3_input();
  2931. }
  2932. else
  2933. {
  2934. sd_clk_transfer_low();
  2935. sd_set_dat0_value(0x01);
  2936. sd_clk_transfer_high();
  2937. sd_set_dat0_input();
  2938. }
  2939. sd_delay_clocks_h(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  2940. crc_status = 0;
  2941. //Check CRC status
  2942. sd_set_dat0_input();
  2943. for(i = 0; i < 5; i++)
  2944. {
  2945. sd_clk_transfer_low();
  2946. data = sd_get_dat0_value();
  2947. crc_status <<= 1;
  2948. crc_status |= data;
  2949. sd_clk_transfer_high();
  2950. }
  2951. if (crc_status == 0x0A) //1010, CRC error
  2952. return SD_MMC_ERROR_DATA_CRC;
  2953. else if (crc_status == 0x0F) //1111, Programming error
  2954. return SD_MMC_ERROR_DRIVER_FAILURE;
  2955. //0101, CRC ok
  2956. //Check busy
  2957. sd_start_timer(SD_PROGRAMMING_TIMEOUT);
  2958. do
  2959. {
  2960. sd_clk_transfer_low();
  2961. data = sd_get_dat0_value();
  2962. sd_clk_transfer_high();
  2963. if(data)
  2964. break;
  2965. }while(!sd_check_timer());
  2966. if(sd_check_timeout())
  2967. {
  2968. return SD_MMC_ERROR_TIMEOUT;
  2969. }
  2970. }
  2971. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0 , RESPONSE_R1B, response);
  2972. if(ret)
  2973. return ret;
  2974. //Check busy
  2975. sd_start_timer(SD_PROGRAMMING_TIMEOUT);
  2976. do
  2977. {
  2978. sd_clk_transfer_low();
  2979. data = sd_get_dat0_value();
  2980. sd_clk_transfer_high();
  2981. if(data)
  2982. break;
  2983. }while(!sd_check_timer());
  2984. if(sd_check_timeout())
  2985. {
  2986. return SD_MMC_ERROR_TIMEOUT;
  2987. }
  2988. return SD_MMC_NO_ERROR;
  2989. }
  2990. #endif
  2991. //Functions for SD INIT
  2992. int sd_hw_reset(SD_MMC_Card_Info_t *sd_mmc_info)
  2993. {
  2994. int ret=SD_MMC_NO_ERROR;
  2995. sd_mmc_info->operation_mode = CARD_INDENTIFICATION_MODE;
  2996. #ifdef SD_MMC_HW_CONTROL
  2997. if(SD_WORK_MODE == CARD_HW_MODE)
  2998. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_GO_IDLE_STATE, 0, RESPONSE_NONE, 0, 0, 0, 1);
  2999. #endif
  3000. #ifdef SD_MMC_SW_CONTROL
  3001. if(SD_WORK_MODE == CARD_SW_MODE)
  3002. {
  3003. sd_delay_clocks_h(sd_mmc_info, 74); //74 is enough according to spec
  3004. sd_delay_ms(1);
  3005. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_GO_IDLE_STATE, 0, RESPONSE_NONE, 0);
  3006. }
  3007. #endif
  3008. return ret;
  3009. }
  3010. int sd_sw_reset(SD_MMC_Card_Info_t *sd_mmc_info)
  3011. {
  3012. int ret=SD_MMC_NO_ERROR;
  3013. sd_mmc_info->operation_mode = CARD_INDENTIFICATION_MODE;
  3014. #ifdef SD_MMC_HW_CONTROL
  3015. if(SD_WORK_MODE == CARD_HW_MODE)
  3016. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_GO_IDLE_STATE, 0, RESPONSE_NONE, 0, 0, 0, 1);
  3017. #endif
  3018. #ifdef SD_MMC_SW_CONTROL
  3019. if(SD_WORK_MODE == CARD_SW_MODE)
  3020. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_GO_IDLE_STATE, 0, RESPONSE_NONE, 0);
  3021. #endif
  3022. return ret;
  3023. }
  3024. //lin
  3025. /*
  3026. static int sd_change_to_low_voltage(SD_MMC_Card_Info_t *sd_mmc_info)
  3027. {
  3028. unsigned char response[MAX_RESPONSE_BYTES];
  3029. //SD_Response_R1_t * r1;
  3030. int ret = 0;
  3031. #ifdef SD_MMC_HW_CONTROL
  3032. if(SD_WORK_MODE == CARD_HW_MODE) //CMD11
  3033. ret = sd_send_cmd_hw(sd_mmc_info, VOLTAGE_SWITCH, 0, RESPONSE_R1, response, 0, 0, 0);
  3034. #endif
  3035. #ifdef SD_MMC_SW_CONTROL
  3036. if(SD_WORK_MODE == CARD_SW_MODE)
  3037. ret = sd_send_cmd_sw(sd_mmc_info, VOLTAGE_SWITCH, 0, RESPONSE_R1, response);
  3038. #endif
  3039. if (ret)
  3040. {
  3041. sd_mmc_info->support_uhs_mode = 0; //fail to switch to 1.8v, so pretend to not support UHS
  3042. return ret;
  3043. }
  3044. else
  3045. {
  3046. printk("Start switch to 1.8V\n");
  3047. return SD_MMC_NO_ERROR;
  3048. }
  3049. }
  3050. */
  3051. int sd_voltage_validation(SD_MMC_Card_Info_t *sd_mmc_info)
  3052. {
  3053. unsigned char response[MAX_RESPONSE_BYTES];
  3054. SD_Response_R3_t * r3;
  3055. SD_Response_R7_t * r7;
  3056. SDIO_Response_R4_t *r4;
  3057. int ret = 0,error = 0,delay_time,delay_cnt;
  3058. //sd_delay_ms(10);
  3059. delay_time = 10;
  3060. delay_cnt = 1;
  3061. //Detect if SD card is inserted first
  3062. printk("sd_mmc_info->card_type=%d\n",sd_mmc_info->card_type);
  3063. printk("begin SDIO check ......\n");
  3064. do
  3065. {
  3066. #ifdef SD_MMC_HW_CONTROL
  3067. if(SD_WORK_MODE == CARD_HW_MODE)
  3068. ret = sd_send_cmd_hw(sd_mmc_info, IO_SEND_OP_COND, 0x00200000, RESPONSE_R4, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  3069. #endif
  3070. #ifdef SD_MMC_SW_CONTROL
  3071. if(SD_WORK_MODE == CARD_SW_MODE)
  3072. ret = sd_send_cmd_sw(sd_mmc_info, IO_SEND_OP_COND, 0x00200000, RESPONSE_R4, response); // 0x00200000: 3.3v~3.4v
  3073. #endif
  3074. #ifdef SD_MMC_HW_CONTROL
  3075. if(SD_WORK_MODE == CARD_HW_MODE)
  3076. ret = sd_send_cmd_hw(sd_mmc_info, IO_SEND_OP_COND, 0x00200000, RESPONSE_R4, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  3077. #endif
  3078. #ifdef SD_MMC_SW_CONTROL
  3079. if(SD_WORK_MODE == CARD_SW_MODE)
  3080. ret = sd_send_cmd_sw(sd_mmc_info, IO_SEND_OP_COND, 0x00200000, RESPONSE_R4, response); // 0x00200000: 3.3v~3.4v
  3081. #endif
  3082. if(ret == SD_MMC_ERROR_TIMEOUT)
  3083. {
  3084. printk("SEND OP timeout @1\n");
  3085. error = sd_hw_reset(sd_mmc_info);
  3086. if(error)
  3087. {
  3088. #ifdef SD_MMC_DEBUG
  3089. Debug_Printf("#%s error occured in sd_hw_reset()\n", sd_error_to_string(error));
  3090. #endif
  3091. return error;
  3092. }
  3093. break;
  3094. }
  3095. else
  3096. {
  3097. r4 = (SDIO_Response_R4_t *)response;
  3098. if(r4->Card_Ready)
  3099. {
  3100. sd_mmc_info->card_type = CARD_TYPE_SDIO;
  3101. sd_mmc_info->sdio_function_nums = r4->IO_Function_No;
  3102. if(r4->Memory_Present)
  3103. break;
  3104. else {
  3105. #ifdef SD_MMC_DEBUG
  3106. Debug_Printf("Actual delay time in sdio_voltage_validation() = %d ms\n", delay_time*delay_cnt);
  3107. #endif
  3108. return SD_MMC_NO_ERROR;
  3109. }
  3110. }
  3111. sd_delay_ms(delay_time);
  3112. delay_cnt++;
  3113. }
  3114. } while(delay_cnt < (SD_MMC_IDENTIFY_TIMEOUT/delay_time)); //lin
  3115. printk("begin SD&SDHC check ......\n");
  3116. sd_delay_ms(10);
  3117. #ifdef SD_MMC_HW_CONTROL
  3118. if(SD_WORK_MODE == CARD_HW_MODE)
  3119. ret = sd_send_cmd_hw(sd_mmc_info, SD_SEND_IF_COND, 0x000001aa, RESPONSE_R7, response, 0, 0, 0);
  3120. #endif
  3121. #ifdef SD_MMC_SW_CONTROL
  3122. if(SD_WORK_MODE == CARD_SW_MODE)
  3123. ret = sd_send_cmd_sw(sd_mmc_info, SD_SEND_IF_COND, 0x000001aa, RESPONSE_R7, response);
  3124. #endif
  3125. if(ret)
  3126. {
  3127. if(ret == SD_MMC_ERROR_TIMEOUT) {
  3128. printk("SEND IF timeout @2\n");
  3129. error = sd_hw_reset(sd_mmc_info);
  3130. if(error)
  3131. {
  3132. #ifdef SD_MMC_DEBUG
  3133. Debug_Printf("#%s error occured in sd_hw_reset()\n", sd_error_to_string(error));
  3134. #endif
  3135. return error;
  3136. }
  3137. }
  3138. else
  3139. return ret;
  3140. }
  3141. else
  3142. {
  3143. r7 = (SD_Response_R7_t *)response;
  3144. if(r7->cmd_version == 0 && r7->voltage_accept == 1 && r7->check_pattern == 0xAA)
  3145. {
  3146. printk("set type to SDHC\n");
  3147. sd_mmc_info->card_type = CARD_TYPE_SDHC;
  3148. }
  3149. else
  3150. {
  3151. printk("set type to SD\n");
  3152. sd_mmc_info->card_type = CARD_TYPE_SD;
  3153. }
  3154. }
  3155. delay_cnt = 2;
  3156. do
  3157. {
  3158. #ifdef SD_MMC_HW_CONTROL
  3159. if(SD_WORK_MODE == CARD_HW_MODE)
  3160. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response, 0, 0, 0);
  3161. #endif
  3162. #ifdef SD_MMC_SW_CONTROL
  3163. if(SD_WORK_MODE == CARD_SW_MODE)
  3164. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response);
  3165. #endif
  3166. if(ret)
  3167. {
  3168. if(ret == SD_MMC_ERROR_TIMEOUT)
  3169. break;
  3170. sd_delay_ms(delay_time);
  3171. delay_cnt++;
  3172. continue;
  3173. }
  3174. //lin : merge
  3175. ////if(sd_mmc_info->card_type == CARD_TYPE_SDHC)
  3176. ////{
  3177. #ifdef SD_MMC_HW_CONTROL
  3178. if(SD_WORK_MODE == CARD_HW_MODE) //0x40200000 : add S18R
  3179. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_OP_COND, 0x41200000, RESPONSE_R3, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  3180. #endif
  3181. #ifdef SD_MMC_SW_CONTROL
  3182. if(SD_WORK_MODE == CARD_SW_MODE)
  3183. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_OP_COND, 0x41200000, RESPONSE_R3, response); // 0x00200000: 3.3v~3.4v
  3184. #endif
  3185. /*
  3186. printk("APP OP SDHC\n");
  3187. }
  3188. else
  3189. {
  3190. #ifdef SD_MMC_HW_CONTROL
  3191. if(SD_WORK_MODE == CARD_HW_MODE) //0x00200000 : add HCS
  3192. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_OP_COND, 0x40200000, RESPONSE_R3, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  3193. #endif
  3194. #ifdef SD_MMC_SW_CONTROL
  3195. if(SD_WORK_MODE == CARD_SW_MODE)
  3196. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_OP_COND, 0x40200000, RESPONSE_R3, response); // 0x00200000: 3.3v~3.4v
  3197. #endif
  3198. printk("APP OP SD\n");
  3199. }
  3200. */
  3201. r3 = (SD_Response_R3_t *)response;
  3202. if(ret == SD_MMC_NO_ERROR && r3->ocr.Card_Busy)
  3203. {
  3204. #ifdef SD_MMC_DEBUG
  3205. Debug_Printf("Actual delay time in sd_voltage_validation() = %d ms\n", delay_time*delay_cnt);
  3206. #endif
  3207. if(!r3->ocr.Card_Capacity_Status)
  3208. {
  3209. printk("Change from %d to SD\n", sd_mmc_info->card_type);
  3210. sd_mmc_info->card_type = CARD_TYPE_SD;
  3211. }
  3212. printk("S18A : %d\n", r3->ocr.S18A);
  3213. sd_mmc_info->support_uhs_mode = r3->ocr.S18A;
  3214. if (sd_mmc_info->support_uhs_mode)
  3215. {
  3216. ////return sd_change_to_low_voltage(sd_mmc_info);
  3217. return SD_MMC_NO_ERROR;
  3218. }
  3219. else
  3220. {
  3221. return SD_MMC_NO_ERROR;
  3222. }
  3223. }
  3224. sd_delay_ms(delay_time);
  3225. delay_cnt++;
  3226. } while(delay_cnt < (SD_MMC_IDENTIFY_TIMEOUT/delay_time)); //lin
  3227. printk("begin MMC check ......\n");
  3228. sd_sw_reset(sd_mmc_info);
  3229. sd_delay_ms(10);
  3230. delay_cnt = 2;
  3231. //No SD card, detect if MMC card is inserted then
  3232. do
  3233. {
  3234. #ifdef SD_MMC_HW_CONTROL
  3235. if(SD_WORK_MODE == CARD_HW_MODE)
  3236. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SEND_OP_COND, 0x40FF8000, RESPONSE_R3, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  3237. #endif
  3238. #ifdef SD_MMC_SW_CONTROL
  3239. if(SD_WORK_MODE == CARD_SW_MODE)
  3240. ret = sd_send_cmd_sw(sd_mmc_info, MMC_SEND_OP_COND, 0x40FF8000, RESPONSE_R3, response); // 0x00200000: 3.3v~3.4v
  3241. #endif
  3242. r3 = (SD_Response_R3_t *)response;
  3243. if(ret == SD_MMC_ERROR_TIMEOUT)
  3244. {
  3245. break;
  3246. }
  3247. else if((ret == SD_MMC_NO_ERROR) && r3->ocr.Card_Busy)
  3248. {
  3249. #ifdef SD_MMC_DEBUG
  3250. Debug_Printf("Actual delay time in sd_voltage_validation() = %d ms\n", delay_time*delay_cnt);
  3251. #endif
  3252. if(!r3->ocr.Card_Capacity_Status)
  3253. sd_mmc_info->card_type = CARD_TYPE_MMC;
  3254. else
  3255. sd_mmc_info->card_type = CARD_TYPE_EMMC;
  3256. printk("set type to %s\n", sd_mmc_info->card_type == CARD_TYPE_MMC ? "mmc" : "emmc");
  3257. return SD_MMC_NO_ERROR;
  3258. }
  3259. sd_delay_ms(delay_time);
  3260. delay_cnt++;
  3261. } while(delay_cnt < (SD_MMC_IDENTIFY_TIMEOUT/delay_time)); //lin
  3262. #ifdef SD_MMC_DEBUG
  3263. Debug_Printf("No any SD/MMC card detected!\n");
  3264. #endif
  3265. return SD_MMC_ERROR_DRIVER_FAILURE;
  3266. }
  3267. static void my_disp_csdv2(SDHC_REG_CSD_t *csd)
  3268. {
  3269. unsigned int i;
  3270. unsigned char *pcsd;
  3271. printk("\n********** CSD v2 **************\n");
  3272. pcsd = (unsigned char *)csd;
  3273. for (i = 0; i < sizeof(SDHC_REG_CSD_t); i++)
  3274. {
  3275. printk("%02x:", pcsd[i]);
  3276. }
  3277. printk("\nCSD_STRUCTURE[2]=%d\n", csd->CSD_STRUCTURE);
  3278. printk("Reserved1[6]=%d\n", csd->Reserved1);
  3279. printk("TAAC[8]=%d\n", csd->TAAC);
  3280. printk("NSAC[8]=%d\n", csd->NSAC);
  3281. printk("TRAN_SPEED[8]=%d\n", csd->TRAN_SPEED);
  3282. printk("CCC[8+4]=0x%x\n", (csd->CCC_high <<4) | csd->CCC_low); //
  3283. printk("READ_BL_LEN[4]=%d\n", csd->READ_BL_LEN);
  3284. printk("READ_BL_PARTIAL[1]=%d\n", csd->READ_BL_PARTIAL);
  3285. printk("WRITE_BLK_MISALIGN[1]=%d\n", csd->WRITE_BLK_MISALIGN);
  3286. printk("READ_BLK_MISALIGN[1]=%d\n", csd->READ_BLK_MISALIGN);
  3287. printk("DSR_IMP[1]=%d\n", csd->DSR_IMP);
  3288. printk("Reserved2[4]=%d\n", csd->Reserved2);
  3289. printk("Reserved3[2]=%d\n", csd->Reserved3);
  3290. printk("C_SIZE[6+8+8]=%d\n", (csd->C_SIZE_high << 16) | (csd->C_SIZE_mid << 8) | csd->C_SIZE_low); //
  3291. printk("Reserved4[1]=%d\n", csd->Reserved4);
  3292. printk("ERASE_BLK_EN[1]=%d\n", csd->ERASE_BLK_EN);
  3293. printk("SECTOR_SIZE[6+1]=%d\n", (csd->SECTOR_SIZE_high << 1) | csd->SECTOR_SIZE_low); //
  3294. printk("WP_GRP_SIZE[7]=%d\n", csd->WP_GRP_SIZE);
  3295. printk("WP_GRP_ENABLE[1]=%d\n", csd->WP_GRP_ENABLE);
  3296. printk("Reserved5[2]=%d\n", csd->Reserved5);
  3297. printk("R2W_FACTOR[3]=%d\n", csd->R2W_FACTOR);
  3298. printk("WRITE_BL_LEN[2+2]=%d\n", (csd->WRITE_BL_LEN_high << 2) | csd->WRITE_BL_LEN_low); //
  3299. printk("WRITE_BL_PARTIAL[1]=%d\n", csd->WRITE_BL_PARTIAL);
  3300. printk("Reserved6[5]=%d\n", csd->Reserved6);
  3301. printk("FILE_FORMAT_GRP[1]=%d\n", csd->FILE_FORMAT_GRP);
  3302. printk("COPY[1]=%d\n", csd->COPY);
  3303. printk("PERM_WRITE_PROTECT[1]=%d\n", csd->PERM_WRITE_PROTECT);
  3304. printk("TMP_WRITE_PROTECT[1]=%d\n", csd->TMP_WRITE_PROTECT);
  3305. printk("FILE_FORMAT[2]=%d\n", csd->FILE_FORMAT);
  3306. printk("Reserved7[2]=%d\n", csd->Reserved7);
  3307. printk("CRC[7]=%d\n", csd->CRC);
  3308. printk("NotUsed[1]=%d\n\n", csd->NotUsed);
  3309. }
  3310. static void my_disp_csdv1(SD_REG_CSD_t *csd)
  3311. {
  3312. unsigned int i;
  3313. unsigned char *pcsd;
  3314. printk("\n********** CSD v1 **************\n");
  3315. pcsd = (unsigned char *)csd;
  3316. for (i = 0; i < sizeof(SD_REG_CSD_t); i++)
  3317. {
  3318. printk("%02x:", pcsd[i]);
  3319. }
  3320. printk("\nCSD_STRUCTURE[2]=%d\n", csd->CSD_STRUCTURE);
  3321. printk("MMC_SPEC_VERS[4]=%d\n", csd->MMC_SPEC_VERS);
  3322. printk("Reserved1[2]=%d\n", csd->Reserved1);
  3323. printk("TAAC[8]=%d\n", csd->TAAC);
  3324. printk("NSAC[8]=%d\n", csd->NSAC);
  3325. printk("TRAN_SPEED[8]=%d\n", csd->TRAN_SPEED);
  3326. printk("CCC[8+4]=%d\n", (csd->CCC_high << 4) | csd->CCC_low); //
  3327. printk("READ_BL_LEN[4]=%d\n", csd->READ_BL_LEN);
  3328. printk("READ_BL_PARTIAL[1]=%d\n", csd->READ_BL_PARTIAL);
  3329. printk("WRITE_BLK_MISALIGN[1]=%d\n", csd->WRITE_BLK_MISALIGN);
  3330. printk("READ_BLK_MISALIGN[1]=%d\n", csd->READ_BLK_MISALIGN);
  3331. printk("DSR_IMP[1]=%d\n", csd->DSR_IMP);
  3332. printk("Reserved2[2]=%d\n", csd->Reserved2);
  3333. printk("C_SIZE[2+8+2]=%d\n", (csd->C_SIZE_high << 10) | (csd->C_SIZE_mid << 2) | csd->C_SIZE_low); //
  3334. printk("VDD_R_CURR_MIN[3]=%d\n", csd->VDD_R_CURR_MIN);
  3335. printk("VDD_R_CURR_MAX[3]=%d\n", csd->VDD_R_CURR_MAX);
  3336. printk("VDD_W_CURR_MIN[3]=%d\n", csd->VDD_W_CURR_MIN);
  3337. printk("VDD_W_CURR_MAX[3]=%d\n", csd->VDD_W_CURR_MAX);
  3338. printk("C_SIZE_MULT[2+1]=%d\n", (csd->C_SIZE_MULT_high << 1) | csd->C_SIZE_MULT_low); //
  3339. printk("ERASE_BLK_EN[1]=%d\n", csd->ERASE_BLK_EN);
  3340. printk("SECTOR_SIZE[6+1]=%d\n", (csd->SECTOR_SIZE_high <<1) | csd->SECTOR_SIZE_low); //
  3341. printk("WP_GRP_SIZE[7]=%d\n", csd->WP_GRP_SIZE);
  3342. printk("Reserved3[2]=%d\n", csd->Reserved3);
  3343. printk("R2W_FACTOR[3]=%d\n", csd->R2W_FACTOR);
  3344. printk("WRITE_BL_LEN[2+2]=%d\n", (csd->WRITE_BL_LEN_high << 2) | csd->WRITE_BL_LEN_low); //
  3345. printk("WRITE_BL_PARTIAL[1]=%d\n", csd->WRITE_BL_PARTIAL);
  3346. printk("Reserved4[5]=%d\n", csd->Reserved4);
  3347. printk("WP_GRP_ENABLE[1]=%d\n", csd->WP_GRP_ENABLE);
  3348. printk("FILE_FORMAT_GRP[1]=%d\n", csd->FILE_FORMAT_GRP);
  3349. printk("COPY[1]=%d\n", csd->COPY);
  3350. printk("PERM_WRITE_PROTECT[1]=%d\n", csd->PERM_WRITE_PROTECT);
  3351. printk("TMP_WRITE_PROTECT[1]=%d\n", csd->TMP_WRITE_PROTECT);
  3352. printk("FILE_FORMAT[2]=%d\n", csd->FILE_FORMAT);
  3353. printk("Reserved5[2]=%d\n", csd->Reserved5);
  3354. printk("CRC[7]=%d\n", csd->CRC);
  3355. printk("NotUsed[1]=%d\n\n", csd->NotUsed);
  3356. }
  3357. static void my_disp_csd_ext(MMC_REG_EXT_CSD_t *csd)
  3358. {
  3359. unsigned int i;
  3360. unsigned char *pcsd;
  3361. printk("\n********** CSD ext **************\n");
  3362. pcsd = (unsigned char *)csd;
  3363. for (i = 0; i < sizeof(MMC_REG_EXT_CSD_t); i++)
  3364. {
  3365. printk("%02x:", pcsd[i]);
  3366. if ((i % 32) == 31)
  3367. printk("\n");
  3368. }
  3369. printk("\nSEC_BAD_BLK_MGMNT=%d\n", csd->SEC_BAD_BLK_MGMNT);
  3370. printk("ENH_START_ADDR[4B]=%d\n", *((unsigned *)&csd->ENH_START_ADDR));
  3371. printk("ENH_SIZE_MULT[3B]=%d\n", (csd->ENH_SIZE_MULT[0]<<16) + (csd->ENH_SIZE_MULT[1]<<8) + (csd->ENH_SIZE_MULT[2]));
  3372. //printk("GP_SIZE_MULT=%d\n", csd->GP_SIZE_MULT);
  3373. printk("PARTITION_SETTING_COMPLETED=%d\n", csd->PARTITION_SETTING_COMPLETED);
  3374. printk("PARTITIONS_ATTRIBUTE=%d\n", csd->PARTITIONS_ATTRIBUTE);
  3375. printk("MAX_ENH_SIZE_MULT[3B]=%d\n", (csd->MAX_ENH_SIZE_MULT[0]<<16) + (csd->MAX_ENH_SIZE_MULT[1]<<8) + (csd->MAX_ENH_SIZE_MULT[2]));
  3376. printk("PARTITIONING_SUPPORT=%d\n", csd->PARTITIONING_SUPPORT);
  3377. printk("HPI_MGMT=%d\n", csd->HPI_MGMT);
  3378. //printk("=%d\n", csd->);
  3379. printk("SEC_COUNT[4B]=%d\n", *((unsigned *)&csd->SEC_COUNT));
  3380. printk("S_CMD_SET=%d\n\n", csd->S_CMD_SET);
  3381. }
  3382. //lin
  3383. /*
  3384. static void my_disp_ssr(SD_REG_SSR_t *ssr)
  3385. {
  3386. unsigned int i;
  3387. unsigned char *pssr;
  3388. printk("\n********** SSR **************\n");
  3389. pssr = (unsigned char *)ssr;
  3390. for (i = 0; i < sizeof(SD_REG_SSR_t); i++)
  3391. {
  3392. printk("%02x:", pssr[i]);
  3393. }
  3394. printk("\nDAT_BUS_WIDTH[2]=%d\n", ssr->DAT_BUS_WIDTH);
  3395. printk("SECURE_MODE[1]=%d\n", ssr->SECURE_MODE);
  3396. printk("Reserved1[5+2]=%d\n", (ssr->Reserved1_1 << 2) | ssr->Reserved1_2); //
  3397. printk("Reserved2[6]=%d\n", ssr->Reserved2);
  3398. printk("SD_CARD_TYPE[16]=%d\n", ssr->SD_CARD_TYPE);
  3399. printk("SIZE_OF_PROTECTED_AREA[32]=%d\n", ssr->SIZE_OF_PROTECTED_AREA);
  3400. printk("SPEED_CLASS[8]=%d\n", ssr->SPEED_CLASS);
  3401. printk("PERPORMANCE_MOVE[8]=%d\n", ssr->PERPORMANCE_MOVE);
  3402. printk("AU_SIZE[4]=%d\n", ssr->AU_SIZE);
  3403. printk("Reserved3[4]=%d\n", ssr->Reserved3);
  3404. printk("ERASE_SIZE[16]=%d\n", ssr->ERASE_SIZE);
  3405. printk("ERASE_TIMEOUT[6]=%d\n", ssr->ERASE_TIMEOUT);
  3406. printk("ERASE_OFFSET[2]=%d\n", ssr->ERASE_OFFSET);
  3407. }
  3408. //SSR(512) is translated in DAT
  3409. static int sd_read_reg_ssr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_SSR_t *ssr)
  3410. {
  3411. int ret;
  3412. unsigned char response[MAX_RESPONSE_BYTES];
  3413. sd_clear_response(response);
  3414. if (SD_WORK_MODE == CARD_HW_MODE)
  3415. {
  3416. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, NULL, 0, 1);
  3417. if (ret)
  3418. return ret;
  3419. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_STATUS, 0, RESPONSE_R1, response, sd_mmc_info->sd_mmc_buf, sizeof(SD_REG_SSR_t), 1);
  3420. if (ret)
  3421. return ret;
  3422. memcpy(ssr, sd_mmc_info->sd_mmc_buf, sizeof(SD_REG_SSR_t));
  3423. }
  3424. return SD_MMC_NO_ERROR;
  3425. }
  3426. */
  3427. //sys pll = 800M
  3428. ////#define CLK_DIV_IDENTIFY 1999 //400K
  3429. #define CLK_DIV_IDENTIFY 3999 //IDENTIFY (200KHz)
  3430. #define CLK_DIV_25M 31 //DS, SDR12 (25MHz)
  3431. #define CLK_DIV_50M 15 //HS, SDR25, DDR50 (50MHz)
  3432. #define CLK_DIV_100M 7 //SDR50 (100MHz)
  3433. #define CLK_DIV_208M 3 //SDR104 (208MHz)
  3434. #define CLK_DIV_HS_MMC 7
  3435. #define CLK_DIV_HS_SDIO 7
  3436. int sd_identify_process(SD_MMC_Card_Info_t *sd_mmc_info)
  3437. {
  3438. int ret = 0, slot_id, times;
  3439. unsigned temp; ///< for compiler bug
  3440. unsigned delay_time, delay_cnt = 0;
  3441. unsigned char response[MAX_RESPONSE_BYTES];
  3442. SD_Response_R2_CSD_t * r2_csd = NULL;
  3443. SDHC_Response_R2_CSD_t * sdhc_r2_csd = NULL;
  3444. SD_Response_R6_t * sd_response_r6;
  3445. unsigned c_size;
  3446. unsigned char c_size_multi;
  3447. unsigned char read_reg_data, write_reg_data;
  3448. unsigned sdio_config;
  3449. SDIO_Config_Reg_t *config_reg = NULL;
  3450. unsigned char *mmc_ext_csd_buf = sd_mmc_info->sd_mmc_buf;
  3451. MMC_REG_EXT_CSD_t *mmc_ext_csd_reg;
  3452. //Request all devices to send their CIDs
  3453. if(sd_mmc_info->card_type != CARD_TYPE_SDIO)
  3454. {
  3455. #ifdef SD_MMC_HW_CONTROL
  3456. if(SD_WORK_MODE == CARD_HW_MODE)
  3457. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID, response, 0, 0, 1);
  3458. #endif
  3459. #ifdef SD_MMC_SW_CONTROL
  3460. if(SD_WORK_MODE == CARD_SW_MODE)
  3461. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID, response);
  3462. #endif
  3463. }
  3464. sd_delay_ms(50); //for MUSE 64MB CARD sd_identify_process timeout
  3465. //sd_delay_ms(10); //for samsung card
  3466. /* Assign IDs to all devices found */
  3467. slot_id = 1;
  3468. delay_time = 10;
  3469. while(delay_cnt < SD_IDENTIFICATION_TIMEOUT/TIMER_1MS)
  3470. {
  3471. #ifdef SD_MMC_HW_CONTROL
  3472. if(SD_WORK_MODE == CARD_HW_MODE)
  3473. {
  3474. if(sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC || sd_mmc_info->card_type == CARD_TYPE_SDIO)
  3475. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, slot_id<<16, RESPONSE_R6, response, 0, 0, 0); ///* Send out a byte to read RCA*/
  3476. else if((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  3477. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, slot_id<<16, RESPONSE_R1, response, 0, 0, 0); ///* Send out a byte to read RCA*/
  3478. }
  3479. #endif
  3480. #ifdef SD_MMC_SW_CONTROL
  3481. if(SD_WORK_MODE == CARD_SW_MODE)
  3482. {
  3483. if(sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC || sd_mmc_info->card_type == CARD_TYPE_SDIO)
  3484. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, slot_id<<16, RESPONSE_R6, response); ///* Send out a byte to read RCA*/
  3485. else if((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  3486. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, slot_id<<16, RESPONSE_R1, response); ///* Send out a byte to read RCA*/
  3487. }
  3488. #endif
  3489. sd_response_r6 = (SD_Response_R6_t *)response;
  3490. /* Check for SD card */
  3491. if((sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC || sd_mmc_info->card_type == CARD_TYPE_SDIO) && (ret == SD_MMC_NO_ERROR))
  3492. break;
  3493. /* Get device information and assign an RCA to it. */
  3494. if (((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC)) && ( ret == SD_MMC_NO_ERROR))
  3495. {
  3496. /* There isn't any more device found */
  3497. break;
  3498. }
  3499. else if((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  3500. {
  3501. /* The RCA is returned in pc->LastResponse[4] */
  3502. slot_id += 1;
  3503. }
  3504. sd_delay_ms(delay_time);
  3505. delay_cnt += delay_time;
  3506. }
  3507. if(delay_cnt >= SD_IDENTIFICATION_TIMEOUT/TIMER_1MS)
  3508. {
  3509. return SD_MMC_ERROR_DRIVER_FAILURE;
  3510. }
  3511. if(sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC || sd_mmc_info->card_type == CARD_TYPE_SDIO)
  3512. sd_mmc_info->card_rca = ((SD_Response_R6_t *)response)->rca_high << 8 | ((SD_Response_R6_t *)response)->rca_low;
  3513. else if((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  3514. sd_mmc_info->card_rca = slot_id;
  3515. printk("Got RCA = %d\n", sd_mmc_info->card_rca);
  3516. if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  3517. {
  3518. #ifdef SD_MMC_HW_CONTROL
  3519. if(SD_WORK_MODE == CARD_HW_MODE)
  3520. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD, sd_mmc_info->card_rca<<16, RESPONSE_R1B, response, 0, 0, 1);
  3521. #endif
  3522. #ifdef SD_MMC_SW_CONTROL
  3523. if(SD_WORK_MODE == CARD_SW_MODE)
  3524. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD, sd_mmc_info->card_rca<<16, RESPONSE_R1B, response);
  3525. #endif
  3526. ret = sdio_read_reg(sd_mmc_info, 0, BUS_Interface_Control_REG, &read_reg_data);
  3527. if(ret)
  3528. return ret;
  3529. sd_mmc_info->operation_mode = DATA_TRANSFER_MODE;
  3530. write_reg_data = ((read_reg_data & 0xfc) | SDIO_Wide_bus_Bit);
  3531. ret = sdio_write_reg(sd_mmc_info, 0, BUS_Interface_Control_REG, &write_reg_data, SDIO_Read_After_Write);
  3532. if(ret)
  3533. {
  3534. write_reg_data = SDIO_Single_bus_Bit;
  3535. ret = sdio_write_reg(sd_mmc_info, 0, BUS_Interface_Control_REG, &write_reg_data, SDIO_Read_After_Write);
  3536. if(ret)
  3537. return ret;
  3538. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3539. return SD_MMC_NO_ERROR;
  3540. }
  3541. else
  3542. {
  3543. sd_mmc_info->bus_width = SD_BUS_WIDE;
  3544. #ifdef SD_MMC_HW_CONTROL
  3545. if(SD_WORK_MODE == CARD_HW_MODE)
  3546. {
  3547. sdio_config = 0;
  3548. config_reg = (void *)&sdio_config;
  3549. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  3550. config_reg->bus_width = 1;
  3551. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  3552. }
  3553. #endif
  3554. return SD_MMC_NO_ERROR;
  3555. }
  3556. }
  3557. ret = sd_read_reg_cid(sd_mmc_info, &sd_mmc_info->raw_cid);
  3558. if(ret)
  3559. return ret;
  3560. #ifdef SD_MMC_HW_CONTROL
  3561. if(SD_WORK_MODE == CARD_HW_MODE)
  3562. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_CSD, sd_mmc_info->card_rca<<16, RESPONSE_R2_CSD, response, 0, 0, 1);
  3563. #endif
  3564. #ifdef SD_MMC_SW_CONTROL
  3565. if(SD_WORK_MODE == CARD_SW_MODE)
  3566. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SEND_CSD, sd_mmc_info->card_rca<<16, RESPONSE_R2_CSD, response);
  3567. #endif
  3568. if(ret)
  3569. {
  3570. #ifdef SD_MMC_DEBUG
  3571. Debug_Printf("#%s error occured at line: %d in file %s\n", sd_error_to_string(ret),__LINE__,__FILE__);
  3572. #endif
  3573. return ret;
  3574. }
  3575. if(sd_mmc_info->card_type == CARD_TYPE_SDHC)
  3576. {
  3577. sdhc_r2_csd = (SDHC_Response_R2_CSD_t *)response;
  3578. my_disp_csdv2((SDHC_REG_CSD_t *)&sdhc_r2_csd->csd);
  3579. }
  3580. else
  3581. {
  3582. r2_csd = (SD_Response_R2_CSD_t *)response;
  3583. my_disp_csdv1((SD_REG_CSD_t *)&r2_csd->csd);
  3584. }
  3585. if((sd_mmc_info->card_type == CARD_TYPE_MMC) || (sd_mmc_info->card_type == CARD_TYPE_EMMC))
  3586. sd_mmc_info->mmc_spec_version = r2_csd->csd.MMC_SPEC_VERS;
  3587. if(sd_mmc_info->card_type == CARD_TYPE_SDHC)
  3588. {
  3589. sd_mmc_info->clks_nac = 50000;
  3590. c_size = (sdhc_r2_csd->csd.C_SIZE_high << 16) | (sdhc_r2_csd->csd.C_SIZE_mid << 8) | (sdhc_r2_csd->csd.C_SIZE_low);
  3591. sd_mmc_info->blk_nums = (c_size + 1) << 10;
  3592. sd_mmc_info->blk_len = 512;
  3593. }
  3594. else
  3595. {
  3596. sd_mmc_info->clks_nac = sd_cal_clks_nac(r2_csd->csd.TAAC, r2_csd->csd.NSAC);
  3597. c_size = (r2_csd->csd.C_SIZE_high << 10) | (r2_csd->csd.C_SIZE_mid << 2) | r2_csd->csd.C_SIZE_low;
  3598. c_size_multi = (r2_csd->csd.C_SIZE_MULT_high << 1) | r2_csd->csd.C_SIZE_MULT_low;
  3599. temp = (c_size+1) * (1 << (c_size_multi+2));
  3600. sd_mmc_info->blk_nums = temp;
  3601. sd_mmc_info->blk_len = 1 << r2_csd->csd.READ_BL_LEN;
  3602. if(sd_mmc_info->blk_len != 512)
  3603. {
  3604. printk("!!! convert blk_len !!!\n");
  3605. temp = sd_mmc_info->blk_len;
  3606. if((temp % 512) != 0)
  3607. return SD_MMC_ERROR_BLOCK_LEN;
  3608. times = temp / 512;
  3609. temp = sd_mmc_info->blk_nums;
  3610. temp *= times;
  3611. sd_mmc_info->blk_nums = temp;
  3612. sd_mmc_info->blk_len = 512;
  3613. }
  3614. }
  3615. #ifdef SD_MMC_HW_CONTROL
  3616. if(SD_WORK_MODE == CARD_HW_MODE)
  3617. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD, sd_mmc_info->card_rca<<16, RESPONSE_R1B, response, 0, 0, 1);
  3618. #endif
  3619. #ifdef SD_MMC_SW_CONTROL
  3620. if(SD_WORK_MODE == CARD_SW_MODE)
  3621. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD, sd_mmc_info->card_rca<<16, RESPONSE_R1B, response);
  3622. #endif
  3623. if (ret)
  3624. return ret;
  3625. if(sd_mmc_info->card_type == CARD_TYPE_EMMC)
  3626. {
  3627. ret = sd_send_cmd_hw(sd_mmc_info,MMC_SEND_EXT_CSD, 0, RESPONSE_R1, response, mmc_ext_csd_buf, sizeof(MMC_REG_EXT_CSD_t), 1);
  3628. if(ret)
  3629. return ret;
  3630. mmc_ext_csd_reg = (MMC_REG_EXT_CSD_t *)mmc_ext_csd_buf;
  3631. //my_disp_csd_ext(mmc_ext_csd_reg);
  3632. sd_mmc_info->blk_nums = *((unsigned *)&mmc_ext_csd_reg->SEC_COUNT);
  3633. sd_mmc_info->blk_len = 512;
  3634. }
  3635. printk("total block nums : 0x%x(%d)\n",sd_mmc_info->blk_nums, sd_mmc_info->blk_nums);
  3636. if(sd_mmc_info->card_type == CARD_TYPE_SD || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  3637. {
  3638. SD_REG_SCR_t scr;
  3639. ret = sd_read_reg_scr(sd_mmc_info, &scr);
  3640. if(ret)
  3641. {
  3642. #ifdef SD_MMC_DEBUG
  3643. Debug_Printf("#%s error occured at line: %d in file %s\n", sd_error_to_string(ret),__LINE__,__FILE__);
  3644. #endif
  3645. return ret;
  3646. }
  3647. sd_mmc_info->spec_version = scr.SD_SPEC;
  3648. if (scr.SD_SPEC3)
  3649. sd_mmc_info->spec_version += 1;
  3650. if(sd_mmc_info->disable_wide_bus)
  3651. scr.SD_BUS_WIDTHS = SD_BUS_SINGLE;
  3652. if(!scr.SD_BUS_WIDTHS)
  3653. scr.SD_BUS_WIDTHS = SD_BUS_WIDE | SD_BUS_SINGLE;
  3654. if(scr.SD_BUS_WIDTHS & SD_BUS_WIDE)
  3655. {//then set to 4bits width
  3656. #ifdef SD_MMC_HW_CONTROL
  3657. if(SD_WORK_MODE == CARD_HW_MODE)
  3658. {
  3659. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  3660. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x02, RESPONSE_R1, response, 0, 0, 1); //0 1bit, 10=4bits
  3661. }
  3662. #endif
  3663. #ifdef SD_MMC_SW_CONTROL
  3664. if(SD_WORK_MODE == CARD_SW_MODE)
  3665. {
  3666. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  3667. ret = sd_send_cmd_sw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x02, RESPONSE_R1, response); //0 1bit, 10=4bits
  3668. }
  3669. #endif
  3670. if(ret)
  3671. {
  3672. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3673. }
  3674. else
  3675. {
  3676. sd_mmc_info->bus_width = SD_BUS_WIDE;
  3677. #ifdef SD_MMC_HW_CONTROL
  3678. if(SD_WORK_MODE == CARD_HW_MODE)
  3679. {
  3680. if (using_sdxc_controller)
  3681. {
  3682. unsigned long sdxc_ctrl = 0;
  3683. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  3684. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  3685. sdxc_ctrl_reg->dat_width = 1;
  3686. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  3687. }
  3688. else
  3689. {
  3690. unsigned long sdio_config = 0;
  3691. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  3692. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  3693. config_reg->bus_width = 1;
  3694. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  3695. }
  3696. }
  3697. #endif
  3698. }
  3699. }
  3700. else
  3701. {//then set to 1bits width
  3702. #ifdef SD_MMC_HW_CONTROL
  3703. if(SD_WORK_MODE == CARD_HW_MODE)
  3704. {
  3705. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  3706. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x00, RESPONSE_R1, response, 0, 0, 1); //0 1bit, 10=4bits
  3707. }
  3708. #endif
  3709. #ifdef SD_MMC_SW_CONTROL
  3710. if(SD_WORK_MODE == CARD_SW_MODE)
  3711. {
  3712. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  3713. ret = sd_send_cmd_sw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x00, RESPONSE_R1, response); //0 1bit, 10=4bits
  3714. }
  3715. #endif
  3716. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3717. }
  3718. }
  3719. else //MMC card
  3720. {
  3721. if(sd_mmc_info->mmc_spec_version == SPEC_VERSION_40_41)
  3722. {
  3723. #ifdef SD_MMC_HW_CONTROL
  3724. if(SD_WORK_MODE == CARD_HW_MODE)
  3725. {
  3726. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b70100, RESPONSE_R1, response, 0, 0, 1);
  3727. }
  3728. #endif
  3729. #ifdef SD_MMC_SW_CONTROL
  3730. if(SD_WORK_MODE == CARD_SW_MODE)
  3731. {
  3732. ret = sd_send_cmd_sw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b70100, RESPONSE_R1, response);
  3733. }
  3734. #endif
  3735. if(ret)
  3736. {
  3737. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3738. }
  3739. else
  3740. {
  3741. sd_mmc_info->bus_width = SD_BUS_WIDE;
  3742. #ifdef SD_MMC_HW_CONTROL
  3743. if(SD_WORK_MODE == CARD_HW_MODE)
  3744. {
  3745. if (using_sdxc_controller)
  3746. {
  3747. unsigned long sdxc_ctrl = 0;
  3748. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  3749. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  3750. sdxc_ctrl_reg->dat_width = 1;
  3751. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  3752. }
  3753. else
  3754. {
  3755. unsigned long sdio_config = 0;
  3756. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  3757. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  3758. config_reg->bus_width = 1;
  3759. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  3760. }
  3761. }
  3762. #endif
  3763. }
  3764. }
  3765. else
  3766. {
  3767. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3768. }
  3769. }
  3770. #ifdef SD_MMC_HW_CONTROL
  3771. if(SD_WORK_MODE == CARD_HW_MODE)
  3772. {
  3773. if (using_sdxc_controller)
  3774. {
  3775. unsigned long sdxc_clk = 0;
  3776. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  3777. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  3778. sdxc_clk_reg->clk_ctl_en = 0;
  3779. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  3780. sdxc_clk_reg->clk_div = CLK_DIV_25M;
  3781. sdxc_clk_reg->clk_en = 1;
  3782. sdxc_clk_reg->clk_ctl_en = 1;
  3783. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  3784. }
  3785. else
  3786. {
  3787. unsigned long sdio_config = 0;
  3788. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  3789. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  3790. if(sd_mmc_info->disable_high_speed == 1)
  3791. {
  3792. config_reg->cmd_clk_divide = 4;
  3793. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_SLOWER_CLK;
  3794. }
  3795. else
  3796. {
  3797. //config_reg->cmd_clk_divide = 3;
  3798. config_reg->cmd_clk_divide = 4;
  3799. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_CLK;
  3800. }
  3801. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  3802. }
  3803. }
  3804. #endif
  3805. sd_mmc_info->operation_mode = DATA_TRANSFER_MODE;
  3806. sd_mmc_check_wp(sd_mmc_info);
  3807. return SD_MMC_NO_ERROR;
  3808. }
  3809. int sdxc_mmc_staff_init(SD_MMC_Card_Info_t *sd_mmc_info)
  3810. {
  3811. //SDXC_Send_Reg_t *sdxc_send_reg;
  3812. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg;
  3813. //SDXC_Status_Reg_t *sdxc_status_reg;
  3814. SDXC_Clk_Reg_t *sdxc_clk_reg;
  3815. SDXC_PDMA_Reg_t *sdxc_pdma_reg;
  3816. SDXC_Misc_Reg_t *sdxc_misc_reg;
  3817. unsigned int sdxc_ctrl, sdxc_clk, sdxc_misc, sdxc_pdma;
  3818. //unsigned int sdxc_send, sdxc_status;
  3819. unsigned int sdxc_srst;
  3820. sd_mmc_prepare_power(sd_mmc_info);
  3821. sd_mmc_power_on(sd_mmc_info);
  3822. sdxc_clk = 0;
  3823. sdxc_clk_reg = (void *)&sdxc_clk;
  3824. sdxc_clk_reg->clk_ctl_en = 0;
  3825. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  3826. sdxc_clk_reg->clk_in_sel = 1;
  3827. sdxc_clk_reg->clk_div = CLK_DIV_IDENTIFY; //sdxx
  3828. sdxc_clk_reg->clk_en = 1;
  3829. sdxc_clk_reg->clk_jic_control = 0;
  3830. sdxc_clk_reg->clk_ctl_en = 1;
  3831. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  3832. sdxc_misc = READ_CBUS_REG(SD_REG7_MISC);
  3833. sdxc_misc_reg = (void *)&sdxc_misc;
  3834. sdxc_misc_reg->manual_stop = 1;
  3835. WRITE_CBUS_REG(SD_REG7_MISC, sdxc_misc);
  3836. sdxc_ctrl = 0;
  3837. sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  3838. sdxc_ctrl_reg->dat_width = 0;
  3839. sdxc_ctrl_reg->rx_timeout = 0x40;
  3840. sdxc_ctrl_reg->rc_period = 0x08;
  3841. sdxc_ctrl_reg->endian = 0x03;
  3842. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  3843. sdxc_pdma = READ_CBUS_REG(SD_REG6_PDMA);
  3844. sdxc_pdma_reg = (void *)&sdxc_pdma;
  3845. sdxc_pdma_reg->dma_mode = 1;
  3846. WRITE_CBUS_REG(SD_REG6_PDMA, sdxc_pdma);
  3847. sdxc_srst = 0x27; //0x3F -- 0x27 : exclude rx_dphy_srst & tx_dphy_srst
  3848. WRITE_CBUS_REG(SD_REGB_SRST, sdxc_srst);
  3849. sd_delay_ms(1);
  3850. sd_sdio_enable(sd_mmc_info->io_pad_type);
  3851. /*
  3852. {
  3853. unsigned int pullup;
  3854. pullup = READ_CBUS_REG(PAD_PULL_UP_REG3);
  3855. pullup |= 0xFF;
  3856. WRITE_CBUS_REG(PAD_PULL_UP_REG3, pullup);
  3857. }
  3858. */
  3859. sd_mmc_info->card_type = CARD_TYPE_NONE;
  3860. sd_mmc_info->operation_mode = CARD_INDENTIFICATION_MODE;
  3861. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  3862. sd_mmc_info->spec_version = SPEC_VERSION_10_101;
  3863. sd_mmc_info->speed_class = NORMAL_SPEED;
  3864. sd_mmc_info->card_rca = 0;
  3865. sd_mmc_info->blk_len = 0;
  3866. sd_mmc_info->blk_nums = 0;
  3867. sd_mmc_info->clks_nac = SD_MMC_TIME_NAC_DEFAULT;
  3868. sd_mmc_info->inited_flag = 0;
  3869. sd_mmc_info->removed_flag = 0;
  3870. sd_mmc_info->write_protected_flag = 0;
  3871. sd_mmc_info->single_blk_failed = 1;
  3872. sd_mmc_info->support_uhs_mode = 0;
  3873. //sd_mmc_info->disable_wide_bus = 1; //sdxx
  3874. sd_mmc_info->read_multi_block_failed = 0;
  3875. sd_mmc_info->write_multi_block_failed = 0; //gg
  3876. return SD_MMC_NO_ERROR;
  3877. }
  3878. int sdxc_mmc_init(SD_MMC_Card_Info_t *sd_mmc_info)
  3879. {
  3880. int error;
  3881. sdio_close_host_interrupt(SDIO_IF_INT);
  3882. if(++sd_mmc_info->init_retry > SD_MMC_INIT_RETRY)
  3883. return SD_MMC_ERROR_DRIVER_FAILURE;
  3884. #ifdef SD_MMC_DEBUG
  3885. Debug_Printf("\nSDXC initialization started......\n");
  3886. #endif
  3887. error = sdxc_mmc_staff_init(sd_mmc_info);
  3888. if(error)
  3889. {
  3890. #ifdef SD_MMC_DEBUG
  3891. Debug_Printf("#%s error occured in sdxc_mmc_staff_init()()\n", sd_error_to_string(error));
  3892. #endif
  3893. goto error;
  3894. }
  3895. sd_mmc_set_input(sd_mmc_info);
  3896. error = sd_hw_reset(sd_mmc_info);
  3897. if(error)
  3898. {
  3899. #ifdef SD_MMC_DEBUG
  3900. Debug_Printf("#%s error occured in sd_hw_reset()\n", sd_error_to_string(error));
  3901. #endif
  3902. goto error;
  3903. }
  3904. sd_delay_ms(200);
  3905. error = sd_voltage_validation(sd_mmc_info);
  3906. if(error)
  3907. {
  3908. #ifdef SD_MMC_DEBUG
  3909. Debug_Printf("#%s error occured in sd_voltage_validation()\n", sd_error_to_string(error));
  3910. #endif
  3911. goto error;
  3912. }
  3913. error = sd_identify_process(sd_mmc_info);
  3914. if(error)
  3915. {
  3916. #ifdef SD_MMC_DEBUG
  3917. Debug_Printf("#%s error occured in sd_identify_process()\n", sd_error_to_string(error));
  3918. #endif
  3919. goto error;
  3920. }
  3921. #ifdef SD_MMC_HW_CONTROL
  3922. if(SD_WORK_MODE == CARD_HW_MODE)
  3923. {
  3924. if(!sd_mmc_info->disable_high_speed)
  3925. {
  3926. error = sd_mmc_switch_function(sd_mmc_info);
  3927. if(error)
  3928. {
  3929. #ifdef SD_MMC_DEBUG
  3930. Debug_Printf("#%s error occured in sd_switch_funtion()\n", sd_error_to_string(error));
  3931. #endif
  3932. //return error;
  3933. }
  3934. }
  3935. }
  3936. #endif
  3937. if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  3938. {
  3939. error = sd_check_sdio_card_type(sd_mmc_info);
  3940. if(error)
  3941. {
  3942. #ifdef SD_MMC_DEBUG
  3943. Debug_Printf("#%s error occured in sd_check_sdio_card_type()\n", sd_error_to_string(error));
  3944. #endif
  3945. goto error;
  3946. }
  3947. }
  3948. #ifdef SD_MMC_DEBUG
  3949. {
  3950. char *card_types[] = {
  3951. "Unknown",
  3952. "SD",
  3953. "SDHC",
  3954. "MMC",
  3955. "EMMC",
  3956. "SDIO"
  3957. };
  3958. char *card_str = card_types[sd_mmc_info->card_type];
  3959. char *bus_str = sd_mmc_info->bus_width == SD_BUS_WIDE ? "Wide Bus" : "Single Bus";
  3960. char *speed_str = sd_mmc_info->speed_class == HIGH_SPEED ? "High Speed" : "Normal Speed";
  3961. Debug_Printf("sdxc_mmc_init() is completed successfully!\n");
  3962. Debug_Printf("This %s card is working in %s and %s mode!\n\n", card_str, bus_str, speed_str);
  3963. }
  3964. #endif
  3965. sd_mmc_info->inited_flag = 1;
  3966. sd_mmc_info->init_retry = 0;
  3967. sd_mmc_info->sdxc_save_hw_io_flag = 1;
  3968. sd_mmc_info->sdxc_save_hw_io_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  3969. sd_mmc_info->sdxc_save_hw_io_clk = READ_CBUS_REG(SD_REG4_CLKC);
  3970. sd_gpio_enable(sd_mmc_info->io_pad_type);
  3971. return SD_MMC_NO_ERROR;
  3972. error:
  3973. sd_gpio_enable(sd_mmc_info->io_pad_type);
  3974. return error;
  3975. }
  3976. int sd_mmc_init(SD_MMC_Card_Info_t *sd_mmc_info)
  3977. {
  3978. int error;
  3979. /*
  3980. { //lin : clear pin mux
  3981. WRITE_CBUS_REG(PERIPHS_PIN_MUX_2, 0);
  3982. WRITE_CBUS_REG(PERIPHS_PIN_MUX_3, 0);
  3983. }
  3984. */
  3985. if ((sd_mmc_info->io_pad_type == SDXC_CARD_0_5) ||
  3986. (sd_mmc_info->io_pad_type == SDXC_BOOT_0_11) ||
  3987. (sd_mmc_info->io_pad_type == SDXC_GPIOX_0_9))
  3988. return sdxc_mmc_init(sd_mmc_info);
  3989. /*close IF INT before change to sd to avoid error IF INT*/
  3990. sdio_close_host_interrupt(SDIO_IF_INT);
  3991. WRITE_CBUS_REG(SDIO_CONFIG, 0);
  3992. WRITE_CBUS_REG(SDIO_MULT_CONFIG, 0);
  3993. if(sd_mmc_info->inited_flag && !sd_mmc_info->removed_flag)
  3994. {
  3995. #ifdef SD_MMC_HW_CONTROL
  3996. if(SD_WORK_MODE == CARD_HW_MODE)
  3997. sd_sdio_enable(sd_mmc_info->io_pad_type);
  3998. #endif
  3999. #ifdef SD_MMC_SW_CONTROL
  4000. if(SD_WORK_MODE == CARD_SW_MODE)
  4001. {
  4002. sd_gpio_enable(sd_mmc_info->io_pad_type);
  4003. }
  4004. #endif
  4005. error = sd_mmc_cmd_test(sd_mmc_info);
  4006. if(!error)
  4007. goto error;
  4008. }
  4009. if(++sd_mmc_info->init_retry > SD_MMC_INIT_RETRY)
  4010. return SD_MMC_ERROR_DRIVER_FAILURE;
  4011. #ifdef SD_MMC_DEBUG
  4012. Debug_Printf("\nSD/MMC initialization started......\n");
  4013. #endif
  4014. error = sd_mmc_staff_init(sd_mmc_info);
  4015. if(error)
  4016. {
  4017. #ifdef SD_MMC_DEBUG
  4018. Debug_Printf("#%s error occured in sd_mmc_staff_init()()\n", sd_error_to_string(error));
  4019. #endif
  4020. goto error;
  4021. }
  4022. sd_mmc_set_input(sd_mmc_info);
  4023. error = sd_hw_reset(sd_mmc_info);
  4024. if(error)
  4025. {
  4026. #ifdef SD_MMC_DEBUG
  4027. Debug_Printf("#%s error occured in sd_hw_reset()\n", sd_error_to_string(error));
  4028. #endif
  4029. goto error;
  4030. }
  4031. error = sd_voltage_validation(sd_mmc_info);
  4032. if(error)
  4033. {
  4034. #ifdef SD_MMC_DEBUG
  4035. Debug_Printf("#%s error occured in sd_voltage_validation()\n", sd_error_to_string(error));
  4036. #endif
  4037. goto error;
  4038. }
  4039. error = sd_identify_process(sd_mmc_info);
  4040. if(error)
  4041. {
  4042. #ifdef SD_MMC_DEBUG
  4043. Debug_Printf("#%s error occured in sd_identify_process()\n", sd_error_to_string(error));
  4044. #endif
  4045. goto error;
  4046. }
  4047. #ifdef SD_MMC_HW_CONTROL
  4048. if(SD_WORK_MODE == CARD_HW_MODE)
  4049. {
  4050. if(!sd_mmc_info->disable_high_speed)
  4051. {
  4052. error = sd_mmc_switch_function(sd_mmc_info);
  4053. if(error)
  4054. {
  4055. #ifdef SD_MMC_DEBUG
  4056. Debug_Printf("#%s error occured in sd_switch_funtion()\n", sd_error_to_string(error));
  4057. #endif
  4058. //return error;
  4059. }
  4060. }
  4061. }
  4062. #endif
  4063. if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  4064. {
  4065. error = sd_check_sdio_card_type(sd_mmc_info);
  4066. if(error)
  4067. {
  4068. #ifdef SD_MMC_DEBUG
  4069. Debug_Printf("#%s error occured in sd_check_sdio_card_type()\n", sd_error_to_string(error));
  4070. #endif
  4071. goto error;
  4072. }
  4073. }
  4074. #ifdef SD_MMC_DEBUG
  4075. {
  4076. char *card_types[] = {
  4077. "Unknown",
  4078. "SD",
  4079. "SDHC",
  4080. "MMC",
  4081. "EMMC",
  4082. "SDIO"
  4083. };
  4084. char *card_str = card_types[sd_mmc_info->card_type];
  4085. char *bus_str = sd_mmc_info->bus_width == SD_BUS_WIDE ? "Wide Bus" : "Single Bus";
  4086. char *speed_str = sd_mmc_info->speed_class == HIGH_SPEED ? "High Speed" : "Normal Speed";
  4087. if(!sd_mmc_info->sdio_clk && sd_mmc_info->sdio_clk_unit)
  4088. sd_mmc_info->sdio_clk = 1000/sd_mmc_info->sdio_clk_unit;
  4089. Debug_Printf("sd_mmc_init() is completed successfully!\n");
  4090. Debug_Printf("This %s card is working in %s and at %dMHz %s mode!\n\n", card_str, bus_str, sd_mmc_info->sdio_clk,speed_str);
  4091. }
  4092. #endif
  4093. sd_mmc_info->inited_flag = 1;
  4094. sd_mmc_info->init_retry = 0;
  4095. sd_mmc_info->sd_save_hw_io_flag = 1;
  4096. sd_mmc_info->sd_save_hw_io_config = READ_CBUS_REG(SDIO_CONFIG);
  4097. sd_mmc_info->sd_save_hw_io_mult_config = READ_CBUS_REG(SDIO_MULT_CONFIG);
  4098. sd_gpio_enable(sd_mmc_info->io_pad_type);
  4099. return SD_MMC_NO_ERROR;
  4100. error:
  4101. sd_gpio_enable(sd_mmc_info->io_pad_type);
  4102. return error;
  4103. }
  4104. void sd_mmc_io_config(SD_MMC_Card_Info_t *sd_mmc_info)
  4105. {
  4106. sd_gpio_enable(sd_mmc_info->io_pad_type);
  4107. sd_set_cmd_output();
  4108. sd_set_cmd_value(1);
  4109. sd_set_clk_output();
  4110. sd_set_clk_high();
  4111. sd_set_dat0_3_input();
  4112. }
  4113. int sd_mmc_staff_init(SD_MMC_Card_Info_t *sd_mmc_info)
  4114. {
  4115. unsigned int sdio_config, sdio_multi_config;
  4116. SDIO_Config_Reg_t *config_reg;
  4117. sd_mmc_prepare_power(sd_mmc_info);
  4118. sd_mmc_power_on(sd_mmc_info);
  4119. #ifdef SD_MMC_HW_CONTROL
  4120. if(SD_WORK_MODE == CARD_HW_MODE)
  4121. {
  4122. sdio_multi_config = (READ_CBUS_REG(SDIO_MULT_CONFIG) & 0x00000003);
  4123. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sdio_multi_config);
  4124. sdio_config = 0;
  4125. config_reg = (void *)&sdio_config;
  4126. config_reg->cmd_clk_divide = 375;
  4127. config_reg->cmd_argument_bits = 39;
  4128. config_reg->m_endian = 3;
  4129. config_reg->write_Nwr = 2;
  4130. config_reg->write_crc_ok_status = 2;
  4131. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  4132. sd_mmc_info->sdio_clk_unit = (1000/SD_MMC_IDENTIFY_CLK)*1000;
  4133. sd_sdio_enable(sd_mmc_info->io_pad_type);
  4134. }
  4135. #endif
  4136. #ifdef SD_MMC_SW_CONTROL
  4137. if(SD_WORK_MODE == CARD_SW_MODE)
  4138. sd_mmc_io_config(sd_mmc_info);
  4139. #endif
  4140. sd_mmc_info->card_type = CARD_TYPE_NONE;
  4141. sd_mmc_info->operation_mode = CARD_INDENTIFICATION_MODE;
  4142. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  4143. sd_mmc_info->spec_version = SPEC_VERSION_10_101;
  4144. sd_mmc_info->speed_class = NORMAL_SPEED;
  4145. sd_mmc_info->card_rca = 0;
  4146. sd_mmc_info->blk_len = 0;
  4147. sd_mmc_info->blk_nums = 0;
  4148. sd_mmc_info->clks_nac = SD_MMC_TIME_NAC_DEFAULT;
  4149. sd_mmc_info->inited_flag = 0;
  4150. sd_mmc_info->removed_flag = 0;
  4151. sd_mmc_info->write_protected_flag = 0;
  4152. sd_mmc_info->single_blk_failed = 0;
  4153. sd_mmc_info->support_uhs_mode = 0;
  4154. return SD_MMC_NO_ERROR;
  4155. }
  4156. #pragma pack(1)
  4157. typedef struct _MySCR {
  4158. unsigned SD_SPEC:4; //SD Card spec. Version
  4159. unsigned SCR_STRUCTURE:4; //SCR Structure
  4160. unsigned SD_BUS_WIDTHS:4; //DAT Bus widths supported
  4161. unsigned SD_SECURITY:3; //SD Security Support
  4162. unsigned DATA_STAT_AFTER_ERASE:1; //data_status_after erases
  4163. unsigned Rsv1 : 7;
  4164. unsigned SD_SPEC3 : 1;
  4165. unsigned CMD_SUPPORT : 2;
  4166. unsigned Rsv2 : 6;
  4167. ////unsigned Reserved1:16; //for alignment
  4168. unsigned long Reserved2;
  4169. } MySCR;
  4170. typedef struct _MyCID {
  4171. unsigned char MID; //Manufacturer ID
  4172. char OID[2]; //OEM/Application ID
  4173. char PNM[5]; //Product Name
  4174. unsigned char PRV; //Product Revision
  4175. unsigned long PSN; //Serial Number
  4176. unsigned MDT_high:4; //Manufacture Date Code
  4177. unsigned Reserved:4;
  4178. unsigned MDT_low:8; // MDT = (MDT_high << 8) | MDT_low
  4179. unsigned NotUsed:1;
  4180. unsigned CRC:7; //CRC7 checksum
  4181. } MyCID;
  4182. #pragma pack()
  4183. static void my_disp_cid(MyCID *cid)
  4184. {
  4185. int size;
  4186. int i;
  4187. unsigned char *pcid;
  4188. unsigned long mdt;
  4189. printk("\n***********CID*************\n");
  4190. pcid = (unsigned char*)cid;
  4191. size = sizeof (MyCID);
  4192. for (i = 0 ; i < size; i++)
  4193. {
  4194. printk("%02x:", pcid[i]);
  4195. }
  4196. printk("\nMID[8]=%d\n", cid->MID);
  4197. printk("OID[16]=%c%c\n", cid->OID[0], cid->OID[1]);
  4198. printk("PNM[40]=%c%c%c%c%c\n", cid->PNM[0], cid->PNM[1], cid->PNM[2], cid->PNM[3], cid->PNM[4]);
  4199. printk("PRV[8]=%d\n", cid->PRV);
  4200. printk("PSN[32]=0x%x\n", (unsigned int)cid->PSN);
  4201. printk("Reserved[4]=%d\n", cid->Reserved);
  4202. mdt = (cid->MDT_high << 8) | cid->MDT_low;
  4203. printk("year[8].month[4]=%ld.%ld\n", (mdt >> 4) + 2000, mdt & 0xF);
  4204. printk("NotUsed[1]=%d\n", cid->NotUsed);
  4205. printk("CRC[7]=%d\n\n", cid->CRC);
  4206. //printk("*************** from mmc *************\n");
  4207. //mmc_decode_cid(cid);
  4208. }
  4209. static void my_disp_scr(MySCR *scr)
  4210. {
  4211. int size;
  4212. int i;
  4213. unsigned char *pscr;
  4214. printk("\n***********SCR*************\n");
  4215. pscr = (unsigned char*)scr;
  4216. size = sizeof (MySCR);
  4217. for (i = 0 ; i < size; i++)
  4218. {
  4219. printk("%02x:", pscr[i]);
  4220. }
  4221. printk("\nSD_SPEC[4]=%d\n", scr->SD_SPEC);
  4222. printk("SCR_STRUCTURE[4]=%d\n", scr->SCR_STRUCTURE);
  4223. printk("SD_BUS_WIDTHS[4]=%d\n", scr->SD_BUS_WIDTHS);
  4224. printk("SD_SECURITY[3]=%d\n", scr->SD_SECURITY);
  4225. printk("DATA_STAT_AFTER_ERASE[1]=%d\n", scr->DATA_STAT_AFTER_ERASE);
  4226. printk("Rsv1[7]=%d\n", scr->Rsv1);
  4227. printk("SD_SPEC3[1]=%d\n", scr->SD_SPEC3);
  4228. printk("CMD_SUPPORT[2]=%d\n", scr->CMD_SUPPORT);
  4229. printk("Rsv2[6]=%d\n", scr->Rsv2);
  4230. printk("Reserved2[32]=%ld\n\n", scr->Reserved2);
  4231. }
  4232. //Read Operation Conditions Register
  4233. int sd_read_reg_ocr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_OCR_t * ocr);
  4234. //Read Card_Identification Register
  4235. int sd_read_reg_cid(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_CID_t * cid)
  4236. {
  4237. int ret;
  4238. unsigned char response[MAX_RESPONSE_BYTES];
  4239. SD_Response_R2_CID_t *res_cid;
  4240. res_cid = (SD_Response_R2_CID_t *)response;
  4241. sd_clear_response(response);
  4242. #ifdef SD_MMC_HW_CONTROL
  4243. if(SD_WORK_MODE == CARD_HW_MODE)
  4244. {
  4245. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_CID, sd_mmc_info->card_rca<<16, RESPONSE_R2_CID, response, NULL, 0, 1);
  4246. if(ret)
  4247. return ret;
  4248. memcpy(cid, (unsigned char*)&res_cid->cid, sizeof(SD_REG_CID_t));
  4249. my_disp_cid((MyCID *)cid);
  4250. }
  4251. #endif
  4252. #ifdef SD_MMC_SW_CONTROL
  4253. if(SD_WORK_MODE == CARD_SW_MODE)
  4254. {
  4255. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SEND_CID,sd_mmc_info->card_rca<<16, RESPONSE_R2_CID, response);
  4256. if(ret)
  4257. return ret;
  4258. memcpy(cid, (unsigned char*)&res_cid->cid, sizeof(SD_REG_CID_t));
  4259. }
  4260. #endif
  4261. return SD_MMC_NO_ERROR;
  4262. }
  4263. //Read Card-Specific Data Register
  4264. int sd_read_reg_csd(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_CSD_t * csd);
  4265. //Read Relative Card Address Register
  4266. int sd_read_reg_rca(SD_MMC_Card_Info_t *sd_mmc_info, unsigned short * rca);
  4267. //Read Driver Stage Register
  4268. int sd_read_reg_dsr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_DSR_t * dsr);
  4269. //Read SD CARD Configuration Register
  4270. int sd_read_reg_scr(SD_MMC_Card_Info_t *sd_mmc_info, SD_REG_SCR_t * scr)
  4271. {
  4272. int ret;
  4273. unsigned char response[MAX_RESPONSE_BYTES];
  4274. #ifdef SD_MMC_SW_CONTROL
  4275. unsigned short crc16;
  4276. #endif
  4277. sd_clear_response(response);
  4278. #ifdef SD_MMC_HW_CONTROL
  4279. if(SD_WORK_MODE == CARD_HW_MODE)
  4280. {
  4281. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  4282. if(ret)
  4283. return ret;
  4284. ret = sd_send_cmd_hw(sd_mmc_info, SD_SEND_SCR, 0, RESPONSE_R1, response, sd_mmc_info->sd_mmc_buf, sizeof(SD_REG_SCR_t), 1);
  4285. if(ret)
  4286. return ret;
  4287. memcpy(scr, sd_mmc_info->sd_mmc_buf, sizeof(SD_REG_SCR_t));
  4288. }
  4289. #endif
  4290. #ifdef SD_MMC_SW_CONTROL
  4291. if(SD_WORK_MODE == CARD_SW_MODE)
  4292. {
  4293. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  4294. if(ret)
  4295. return ret;
  4296. ret = sd_send_cmd_sw(sd_mmc_info, SD_SEND_SCR, 0, RESPONSE_NONE, response);
  4297. if(ret)
  4298. return ret;
  4299. ret = sd_get_dat0_data(sd_mmc_info, sizeof(SD_REG_SCR_t), (unsigned char *)scr, &crc16);
  4300. if(ret)
  4301. return ret;
  4302. }
  4303. #endif
  4304. my_disp_scr((MySCR*)scr);
  4305. return SD_MMC_NO_ERROR;
  4306. }
  4307. //Check if any card is connected to adapter
  4308. #ifdef SD_MMC_SW_CONTROL
  4309. SD_Card_Type_t sd_mmc_check_present(SD_MMC_Card_Info_t *sd_mmc_info)
  4310. {
  4311. int retry, ret;
  4312. unsigned char response[MAX_RESPONSE_BYTES];
  4313. SD_Response_R3_t * r3;
  4314. //Detect if SD card is inserted first
  4315. for(retry = 0; retry < MAX_CHECK_INSERT_RETRY; retry++)
  4316. {
  4317. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response);
  4318. if(ret)
  4319. continue;
  4320. ret = sd_send_cmd_sw(sd_mmc_info, SD_APP_OP_COND, 0x00200000, RESPONSE_R3, response); // 0x00200000: 3.3v~3.4v
  4321. r3 = (SD_Response_R3_t *)response;
  4322. if((ret == SD_MMC_NO_ERROR) && r3->ocr.Card_Busy)
  4323. return CARD_TYPE_SD;
  4324. }
  4325. sd_sw_reset(sd_mmc_info);
  4326. //No SD card, detect if MMC card is inserted then
  4327. for(retry = 0; retry < MAX_CHECK_INSERT_RETRY; retry++)
  4328. {
  4329. ret = sd_send_cmd_sw(sd_mmc_info, MMC_SEND_OP_COND, 0x00200000, RESPONSE_R3, response); // 0x00200000: 3.3v~3.4v
  4330. r3 = (SD_Response_R3_t *)response;
  4331. if((ret == SD_MMC_NO_ERROR) && r3->ocr.Card_Busy)
  4332. return CARD_TYPE_MMC;
  4333. }
  4334. return CARD_TYPE_NONE;
  4335. }
  4336. #endif
  4337. //Check if any card is inserted according to pull up resistor
  4338. int sd_mmc_check_insert(SD_MMC_Card_Info_t *sd_mmc_info)
  4339. {
  4340. int level, level_tmp;
  4341. int init_flag = sd_mmc_info->init_retry | sd_mmc_info->inited_flag;
  4342. if(sd_mmc_info->sd_mmc_get_ins)
  4343. {
  4344. level = sd_mmc_info->sd_mmc_get_ins();
  4345. }
  4346. else
  4347. {
  4348. sd_set_ins_input();
  4349. level = sd_get_ins_value();
  4350. }
  4351. if(init_flag){
  4352. if(level){
  4353. udelay(20);
  4354. level = sd_get_ins_value();
  4355. if(level){
  4356. udelay(20);
  4357. level = sd_get_ins_value();
  4358. }
  4359. }
  4360. }
  4361. if (level)
  4362. {
  4363. if(sd_mmc_info->init_retry)
  4364. {
  4365. sd_mmc_power_off(sd_mmc_info);
  4366. sd_mmc_info->init_retry = 0;
  4367. }
  4368. if(sd_mmc_info->inited_flag)
  4369. {
  4370. sd_mmc_power_off(sd_mmc_info);
  4371. sd_mmc_info->removed_flag = 1;
  4372. sd_mmc_info->inited_flag = 0;
  4373. }
  4374. return 0; //No card is inserted
  4375. }
  4376. else
  4377. {
  4378. return 1; //A card is inserted
  4379. }
  4380. }
  4381. //Read data from SD/MMC card
  4382. int sd_mmc_read_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long byte_cnt, unsigned char * data_buf)
  4383. {
  4384. int error = 0;
  4385. unsigned long lba_nums;
  4386. #ifdef SD_MMC_HW_CONTROL
  4387. if(SD_WORK_MODE == CARD_HW_MODE)
  4388. {
  4389. if (sd_mmc_info->sd_save_hw_io_flag) {
  4390. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  4391. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  4392. }
  4393. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  4394. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  4395. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  4396. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  4397. }
  4398. }
  4399. #endif
  4400. #ifdef SD_MMC_SW_CONTROL
  4401. if(SD_WORK_MODE == CARD_SW_MODE)
  4402. sd_mmc_io_config(sd_mmc_info);
  4403. #endif
  4404. lba_nums = sd_mmc_info->blk_len;
  4405. lba_nums = (byte_cnt + sd_mmc_info->blk_len - 1) / lba_nums;
  4406. if(lba_nums == 0)
  4407. {
  4408. error = SD_MMC_ERROR_BLOCK_LEN;
  4409. #ifdef SD_MMC_DEBUG
  4410. Debug_Printf("#%s error occured in sd_mmc_read_data()\n", sd_error_to_string(error));
  4411. #endif
  4412. return error;
  4413. }
  4414. else if ((lba_nums == 1) && !sd_mmc_info->single_blk_failed)
  4415. {
  4416. #ifdef SD_MMC_HW_CONTROL
  4417. if(SD_WORK_MODE == CARD_HW_MODE)
  4418. error = sd_read_single_block_hw(sd_mmc_info, lba, data_buf);
  4419. #endif
  4420. #ifdef SD_MMC_SW_CONTROL
  4421. if(SD_WORK_MODE == CARD_SW_MODE)
  4422. error = sd_read_single_block_sw(sd_mmc_info, lba, data_buf);
  4423. #endif
  4424. if(error)
  4425. {
  4426. #ifdef SD_MMC_DEBUG
  4427. Debug_Printf("#%s error occured in sd_read_single_block()\n", sd_error_to_string(error));
  4428. #endif
  4429. return error;
  4430. }
  4431. }
  4432. else
  4433. {
  4434. #ifdef SD_MMC_HW_CONTROL
  4435. if(SD_WORK_MODE == CARD_HW_MODE)
  4436. {
  4437. error = sd_read_multi_block_hw(sd_mmc_info, lba, lba_nums, data_buf);
  4438. if(error)
  4439. error = sd_read_multi_block_hw(sd_mmc_info, lba, lba_nums, data_buf);
  4440. }
  4441. #endif
  4442. #ifdef SD_MMC_SW_CONTROL
  4443. if(SD_WORK_MODE == CARD_SW_MODE)
  4444. error = sd_read_multi_block_sw(sd_mmc_info, lba, lba_nums, data_buf);
  4445. #endif
  4446. if(error)
  4447. {
  4448. #ifdef SD_MMC_DEBUG
  4449. Debug_Printf("#%s error occured in sd_read_multi_block()\n", sd_error_to_string(error));
  4450. #endif
  4451. return error;
  4452. }
  4453. }
  4454. return SD_MMC_NO_ERROR;
  4455. }
  4456. //Write data to SD/MMC card
  4457. int sd_mmc_write_data(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long lba, unsigned long byte_cnt, unsigned char * data_buf)
  4458. {
  4459. int error = 0;
  4460. unsigned long lba_nums;
  4461. if(sd_mmc_info->write_protected_flag)
  4462. {
  4463. error = SD_MMC_ERROR_WRITE_PROTECTED;
  4464. #ifdef SD_MMC_DEBUG
  4465. Debug_Printf("#%s error occured in sd_mmc_write_data()\n", sd_error_to_string(error));
  4466. #endif
  4467. return error;
  4468. }
  4469. #ifdef SD_MMC_HW_CONTROL
  4470. if(SD_WORK_MODE == CARD_HW_MODE)
  4471. {
  4472. if (sd_mmc_info->sd_save_hw_io_flag) {
  4473. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  4474. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  4475. }
  4476. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  4477. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  4478. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  4479. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  4480. }
  4481. }
  4482. #endif
  4483. #ifdef SD_MMC_SW_CONTROL
  4484. if(SD_WORK_MODE == CARD_SW_MODE)
  4485. sd_mmc_io_config(sd_mmc_info);
  4486. #endif
  4487. //memcpy(sd_write_buf, data_buf, byte_cnt);
  4488. lba_nums = sd_mmc_info->blk_len;
  4489. lba_nums = (byte_cnt + sd_mmc_info->blk_len - 1) / lba_nums;
  4490. if(lba_nums == 0)
  4491. {
  4492. error = SD_MMC_ERROR_BLOCK_LEN;
  4493. #ifdef SD_MMC_DEBUG
  4494. Debug_Printf("#%s error occured in sd_mmc_write_data()\n", sd_error_to_string(error));
  4495. #endif
  4496. return error;
  4497. }
  4498. else if ((lba_nums == 1) && !sd_mmc_info->single_blk_failed)
  4499. {
  4500. #ifdef SD_MMC_HW_CONTROL
  4501. if(SD_WORK_MODE == CARD_HW_MODE)
  4502. error = sd_write_single_block_hw(sd_mmc_info, lba, data_buf);
  4503. #endif
  4504. #ifdef SD_MMC_SW_CONTROL
  4505. if(SD_WORK_MODE == CARD_SW_MODE)
  4506. error = sd_write_single_block_sw(sd_mmc_info, lba, data_buf);
  4507. #endif
  4508. if(error)
  4509. {
  4510. #ifdef SD_MMC_DEBUG
  4511. Debug_Printf("#%s error occured in sd_write_single_block()\n", sd_error_to_string(error));
  4512. #endif
  4513. return error;
  4514. }
  4515. }
  4516. else
  4517. {
  4518. #ifdef SD_MMC_HW_CONTROL
  4519. if(SD_WORK_MODE == CARD_HW_MODE)
  4520. error = sd_write_multi_block_hw(sd_mmc_info, lba, lba_nums, data_buf);
  4521. #endif
  4522. #ifdef SD_MMC_SW_CONTROL
  4523. if(SD_WORK_MODE == CARD_SW_MODE)
  4524. error = sd_write_multi_block_sw(sd_mmc_info, lba, lba_nums, data_buf);
  4525. #endif
  4526. if(error)
  4527. {
  4528. #ifdef SD_MMC_DEBUG
  4529. Debug_Printf("#%s error occured in sd_write_multi_block()\n", sd_error_to_string(error));
  4530. #endif
  4531. return error;
  4532. }
  4533. }
  4534. return SD_MMC_NO_ERROR;
  4535. }
  4536. #ifdef SD_MMC_SW_CONTROL
  4537. int sd_mmc_cmd_test(SD_MMC_Card_Info_t *sd_mmc_info)
  4538. {
  4539. int ret;
  4540. unsigned char response[MAX_RESPONSE_BYTES];
  4541. sd_clear_response(response);
  4542. sd_mmc_io_config(sd_mmc_info);
  4543. ret = sd_send_cmd_sw(sd_mmc_info, SD_MMC_SEND_STATUS, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  4544. return ret;
  4545. }
  4546. #endif
  4547. void sd_mmc_power_on(SD_MMC_Card_Info_t *sd_mmc_info)
  4548. {
  4549. sd_delay_ms(sd_mmc_info->sd_mmc_power_delay+1);
  4550. #ifdef SD_MMC_POWER_CONTROL
  4551. if(sd_mmc_info->sd_mmc_power)
  4552. {
  4553. sd_mmc_info->sd_mmc_power(0);
  4554. }
  4555. else
  4556. {
  4557. sd_set_disable();
  4558. }
  4559. sd_delay_ms(200);
  4560. if(sd_mmc_info->sd_mmc_power)
  4561. {
  4562. if(sd_mmc_check_insert(sd_mmc_info)) //ensure card wasn't removed at this time
  4563. {
  4564. sd_mmc_info->sd_mmc_power(1);
  4565. }
  4566. }
  4567. else
  4568. {
  4569. if(sd_mmc_check_insert(sd_mmc_info)) //ensure card wasn't removed at this time
  4570. {
  4571. sd_set_enable();
  4572. }
  4573. }
  4574. sd_delay_ms(200);
  4575. #else
  4576. sd_delay_ms(10);
  4577. #endif
  4578. }
  4579. void sd_mmc_power_off(SD_MMC_Card_Info_t *sd_mmc_info)
  4580. {
  4581. #ifdef SD_MMC_POWER_CONTROL
  4582. if(sd_mmc_info->sd_mmc_power)
  4583. {
  4584. sd_mmc_info->sd_mmc_power(0);
  4585. }
  4586. else
  4587. {
  4588. sd_set_disable();
  4589. sd_set_pwr_input();
  4590. }
  4591. #endif
  4592. }
  4593. //Check if Write-Protected switch is on
  4594. int sd_mmc_check_wp(SD_MMC_Card_Info_t *sd_mmc_info)
  4595. {
  4596. #ifdef SD_MMC_WP_CHECK
  4597. int ret = 0;
  4598. if(sd_mmc_info->sd_get_wp)
  4599. {
  4600. ret = sd_mmc_info->sd_get_wp();
  4601. }
  4602. else
  4603. {
  4604. sd_set_wp_input();
  4605. ret = sd_get_wp_value();
  4606. }
  4607. if (ret)
  4608. {
  4609. sd_mmc_info->write_protected_flag = 1;
  4610. return 1; //switch is on
  4611. }
  4612. else
  4613. {
  4614. return 0; //switch is off
  4615. }
  4616. #else
  4617. return 0;
  4618. #endif
  4619. }
  4620. //check data lines consistency
  4621. int sd_check_data_consistency(SD_MMC_Card_Info_t *sd_mmc_info)
  4622. {
  4623. int error, func_num=0;
  4624. unsigned char read_reg_data;
  4625. unsigned read_addr, sdio_cis_addr;
  4626. #ifdef SD_MMC_SW_CONTROL
  4627. unsigned char response[MAX_RESPONSE_BYTES];
  4628. #endif
  4629. unsigned char *mbr_buf = sd_mmc_info->sd_mmc_buf;
  4630. //This card is working in wide bus mode!
  4631. memset(mbr_buf, 0, sd_mmc_info->blk_len);
  4632. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  4633. {
  4634. if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  4635. {
  4636. for (func_num=0; func_num<sd_mmc_info->sdio_function_nums; func_num++) {
  4637. read_addr = ((func_num << 8) | Common_CIS_Pointer3_REG);
  4638. error = sdio_read_reg(sd_mmc_info, 0, read_addr, &read_reg_data);
  4639. if(error)
  4640. return error;
  4641. sdio_cis_addr = read_reg_data;
  4642. read_addr = ((func_num << 8) | Common_CIS_Pointer2_REG);
  4643. error = sdio_read_reg(sd_mmc_info, 0, read_addr, &read_reg_data);
  4644. if(error)
  4645. return error;
  4646. sdio_cis_addr = ((sdio_cis_addr << 8) | read_reg_data);
  4647. read_addr = ((func_num << 8) | Common_CIS_Pointer1_REG);
  4648. error = sdio_read_reg(sd_mmc_info, 0, read_addr, &read_reg_data);
  4649. if (error)
  4650. return error;
  4651. sdio_cis_addr = ((sdio_cis_addr << 8) | read_reg_data);
  4652. sd_mmc_info->sdio_cis_addr[func_num] = sdio_cis_addr;
  4653. //printk("sdio cis addr is %x \n", sdio_cis_addr);
  4654. }
  4655. return SD_MMC_NO_ERROR;
  4656. }
  4657. //read MBR information
  4658. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len, mbr_buf);
  4659. if(error)
  4660. {
  4661. //error! retry again!
  4662. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len, mbr_buf);
  4663. if(error)
  4664. return error;
  4665. }
  4666. //check MBR data consistency
  4667. if((mbr_buf[510] != 0x55) || (mbr_buf[511] != 0xAA))
  4668. {
  4669. //data consistency error! retry again!
  4670. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len*2, mbr_buf);
  4671. if(error)
  4672. return error;
  4673. //check MBR data consistency
  4674. if((mbr_buf[510] != 0x55) || (mbr_buf[511] != 0xAA))
  4675. {
  4676. #ifdef SD_MMC_DEBUG
  4677. Debug_Printf("SD/MMC data consistency error in Wide Bus mode! Try Single Bus mode...\n");
  4678. #endif
  4679. //error again! retry single bus mode!
  4680. #ifdef SD_MMC_SW_CONTROL
  4681. if(SD_WORK_MODE == CARD_SW_MODE)
  4682. {
  4683. error = sd_send_cmd_sw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response);
  4684. if(error)
  4685. return error;
  4686. error = sd_send_cmd_sw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x00, RESPONSE_R1, response); //0 1bit, 10=4bits
  4687. if(error)
  4688. return error;
  4689. }
  4690. #endif
  4691. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  4692. #ifdef SD_MMC_HW_CONTROL
  4693. if(SD_WORK_MODE == CARD_HW_MODE)
  4694. {
  4695. unsigned long sdio_config = 0;
  4696. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  4697. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  4698. config_reg->bus_width = 0;
  4699. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  4700. }
  4701. #endif
  4702. }
  4703. else
  4704. {
  4705. sd_mmc_info->single_blk_failed = 1;
  4706. return SD_MMC_NO_ERROR;
  4707. }
  4708. }
  4709. else
  4710. {
  4711. return SD_MMC_NO_ERROR;
  4712. }
  4713. }
  4714. //This card is working in single bus mode!
  4715. memset(mbr_buf, 0, sd_mmc_info->blk_len);
  4716. //read MBR information
  4717. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len, mbr_buf);
  4718. //For Kingston MMC mobile card
  4719. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len, mbr_buf);
  4720. if(error)
  4721. {
  4722. //error! retry again!
  4723. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len, mbr_buf);
  4724. if(error)
  4725. return error;
  4726. }
  4727. //check MBR data consistency
  4728. if((mbr_buf[510] != 0x55) || (mbr_buf[511] != 0xAA))
  4729. {
  4730. //data consistency error! retry again!
  4731. error = sd_mmc_read_data(sd_mmc_info, 0, sd_mmc_info->blk_len*2, mbr_buf);
  4732. if(error)
  4733. return error;
  4734. //check MBR data consistency
  4735. if((mbr_buf[510] != 0x55) || (mbr_buf[511] != 0xAA))
  4736. {
  4737. return SD_MMC_ERROR_DATA_CRC;
  4738. }
  4739. else
  4740. {
  4741. sd_mmc_info->single_blk_failed = 1;
  4742. }
  4743. }
  4744. return SD_MMC_NO_ERROR;
  4745. }
  4746. void sd_mmc_exit(SD_MMC_Card_Info_t *sd_mmc_info)
  4747. {
  4748. if(sd_mmc_info->sd_mmc_io_release != NULL)
  4749. sd_mmc_info->sd_mmc_io_release();
  4750. if(sd_mmc_info->card_type == CARD_TYPE_SD)
  4751. Debug_Printf("SD card unpluged!\n\n");
  4752. else if(sd_mmc_info->card_type == CARD_TYPE_SDHC)
  4753. Debug_Printf("SDHC card unpluged!\n\n");
  4754. else if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  4755. Debug_Printf("SDIO card unpluged!\n\n");
  4756. else
  4757. Debug_Printf("MMC card unpluged!\n\n");
  4758. return;
  4759. }
  4760. void sd_mmc_prepare_init(SD_MMC_Card_Info_t *sd_mmc_info)
  4761. {
  4762. if(sd_mmc_power_register != NULL)
  4763. sd_mmc_info->sd_mmc_power = sd_mmc_power_register;
  4764. if(sd_mmc_ins_register != NULL)
  4765. sd_mmc_info->sd_mmc_get_ins = sd_mmc_ins_register;
  4766. if(sd_mmc_wp_register != NULL)
  4767. sd_mmc_info->sd_get_wp = sd_mmc_wp_register;
  4768. if(sd_mmc_io_release_register != NULL)
  4769. sd_mmc_info->sd_mmc_io_release = sd_mmc_io_release_register;
  4770. }
  4771. void sd_mmc_prepare_power(SD_MMC_Card_Info_t *sd_mmc_info)
  4772. {
  4773. sd_gpio_enable(sd_mmc_info->io_pad_type);
  4774. sd_set_cmd_output();
  4775. sd_set_cmd_value(0);
  4776. sd_set_clk_output();
  4777. sd_set_clk_low();
  4778. sd_set_dat0_3_output();
  4779. sd_set_dat0_3_value(0);
  4780. }
  4781. void sd_mmc_set_input(SD_MMC_Card_Info_t *sd_mmc_info)
  4782. {
  4783. sd_set_cmd_input();
  4784. sd_set_clk_input();
  4785. sd_set_dat0_3_input();
  4786. }
  4787. #define SWAP_SHORT(value) (((value) >> 8) | (((value) & 0xFF) << 8))
  4788. static int try_uhs_mode(SD_MMC_Card_Info_t *sd_mmc_info, unsigned long arg, SD_UHS_I_MODE_t mode)
  4789. {
  4790. int ret;
  4791. unsigned char response[MAX_RESPONSE_BYTES];
  4792. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  4793. SD_Switch_Function_Status_t *switch_funtion_status;
  4794. unsigned short max_current_comsumption;
  4795. unsigned short max_output_current = 400;
  4796. SDXC_Clk_Reg_t *sdxc_clk_reg;
  4797. unsigned long sdxc_clk;
  4798. //sdxx //reset to default mode
  4799. sdxc_clk = 0;
  4800. sdxc_clk_reg = (void *)&sdxc_clk;
  4801. sdxc_clk_reg->clk_ctl_en = 0;
  4802. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  4803. sdxc_clk_reg->clk_in_sel = 1;
  4804. sdxc_clk_reg->clk_div = CLK_DIV_IDENTIFY; //sdxx
  4805. sdxc_clk_reg->clk_en = 1;
  4806. sdxc_clk_reg->clk_ctl_en = 1;
  4807. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  4808. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  4809. memset(status_data_buf, 0, 64);
  4810. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, arg, RESPONSE_R1, response, status_data_buf, 64, 1);
  4811. if (ret)
  4812. return ret;
  4813. max_current_comsumption = SWAP_SHORT(switch_funtion_status->Max_Current_Consumption);
  4814. if ((max_current_comsumption == 0) || (max_current_comsumption > max_output_current) || (switch_funtion_status->Function_Group_Status1 != (arg & 0x0F)))
  4815. return SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  4816. memset(status_data_buf, 0, 64);
  4817. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, arg | 0x80000000, RESPONSE_R1, response, status_data_buf, 64, 1);
  4818. if (ret)
  4819. return ret;
  4820. max_current_comsumption = SWAP_SHORT(switch_funtion_status->Max_Current_Consumption);
  4821. if ((max_current_comsumption == 0) || (max_current_comsumption > max_output_current) || (switch_funtion_status->Function_Group_Status1 != (arg & 0x0F)))
  4822. return SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  4823. sdxc_clk = 0;
  4824. sdxc_clk_reg = (void *)&sdxc_clk;
  4825. sdxc_clk_reg->clk_ctl_en = 0;
  4826. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  4827. sdxc_clk_reg->clk_in_sel = 1;
  4828. switch (mode)
  4829. {
  4830. case SDR12 :
  4831. sdxc_clk_reg->clk_div = CLK_DIV_25M;
  4832. break;
  4833. case SDR25 :
  4834. sdxc_clk_reg->clk_div = CLK_DIV_50M;
  4835. break;
  4836. case SDR50 :
  4837. sdxc_clk_reg->clk_div = CLK_DIV_100M;
  4838. break;
  4839. case SDR104 :
  4840. sdxc_clk_reg->clk_div = CLK_DIV_208M;
  4841. break;
  4842. case DDR50 : //same as SDR25
  4843. sdxc_clk_reg->clk_div = CLK_DIV_50M;
  4844. break;
  4845. default :
  4846. sdxc_clk_reg->clk_div = CLK_DIV_IDENTIFY;
  4847. break;
  4848. }
  4849. sdxc_clk_reg->clk_en = 1;
  4850. sdxc_clk_reg->clk_ctl_en = 1;
  4851. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  4852. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_HIGHSPEED_CLK;
  4853. sd_mmc_info->speed_class = HIGH_SPEED;
  4854. sd_mmc_info->uhs_mode = mode;
  4855. return SD_MMC_NO_ERROR;
  4856. }
  4857. //total 64 bytes
  4858. static unsigned char sd_tuning_pattern[] = {
  4859. 0xFF, 0x0F, 0xFF, 0x00, 0xFF, 0xCC, 0xC3, 0xCC,
  4860. 0xC3, 0x3C, 0xCC, 0xFF, 0xFE, 0xFF, 0xFE, 0xEF,
  4861. 0xFF, 0xDF, 0xFF, 0xDD, 0xFF, 0xFB, 0xFF, 0xFB,
  4862. 0xBF, 0xFF, 0x7F, 0xFF, 0x77, 0xF7, 0xBD, 0xEF,
  4863. 0xFF, 0xF0, 0xFF, 0xF0, 0x0F, 0xFC, 0xCC, 0x3C,
  4864. 0xCC, 0x33, 0xCC, 0xCF, 0xFF, 0xEF, 0xFF, 0xEE,
  4865. 0xFF, 0xFD, 0xFF, 0xFD, 0xDF, 0xFF, 0xBF, 0xFF,
  4866. 0xBB, 0xFF, 0xF7, 0xFF, 0xF7, 0x7F, 0x7B, 0xDE
  4867. };
  4868. static int sd_check_tuning_pattern(unsigned char *pattern)
  4869. {
  4870. int i;
  4871. for (i = 0; i < 64; i++)
  4872. {
  4873. if (pattern[i] != sd_tuning_pattern[i])
  4874. return -1;
  4875. }
  4876. return SD_MMC_NO_ERROR;
  4877. }
  4878. #define MAX_TUNING_TIMES 40
  4879. static int sd_tune_sample_clock(SD_MMC_Card_Info_t *sd_mmc_info)
  4880. {
  4881. int ret;
  4882. int i;
  4883. int start, end;
  4884. int idx;
  4885. unsigned char response[MAX_RESPONSE_BYTES];
  4886. unsigned char *tunning_pattern_buf = sd_mmc_info->sd_mmc_buf;
  4887. unsigned char tuning_flag[MAX_TUNING_TIMES];
  4888. for (i = 0; i < MAX_TUNING_TIMES; i++)
  4889. {
  4890. //set SDXC_Misc_Reg_t->dat_line_delay & SDXC_Misc_Reg_t->cmd_line_delay according to i
  4891. ret = sd_send_cmd_hw(sd_mmc_info, SD_SEND_TUNNING_PATTERN, 0, RESPONSE_R1, response, tunning_pattern_buf, 64, 1);
  4892. if (ret)
  4893. return ret;
  4894. if (sd_check_tuning_pattern(response) == 0)
  4895. tuning_flag[i] = 1;
  4896. else
  4897. tuning_flag[i] = 0;
  4898. }
  4899. start = -1;
  4900. end = -1;
  4901. for (i = 0; i < MAX_TUNING_TIMES; i++)
  4902. {
  4903. if (tuning_flag[i] == 1)
  4904. {
  4905. start = i;
  4906. break;
  4907. }
  4908. }
  4909. if (start == -1)
  4910. return -1;
  4911. for (i = start + 1; i < MAX_TUNING_TIMES; i++)
  4912. {
  4913. if (tuning_flag[i] == 0)
  4914. {
  4915. end = i - 1;
  4916. }
  4917. }
  4918. if (end == -1)
  4919. end = MAX_TUNING_TIMES -1;
  4920. idx = (start + end) / 2;
  4921. //set SDXC_Misc_Reg_t->dat_line_delay & SDXC_Misc_Reg_t->cmd_line_delay according to idx
  4922. return SD_MMC_NO_ERROR;
  4923. }
  4924. int sd_switch_to_uhs_mode(SD_MMC_Card_Info_t *sd_mmc_info)
  4925. {
  4926. int ret;
  4927. unsigned char response[MAX_RESPONSE_BYTES];
  4928. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  4929. SD_Switch_Function_Status_t *switch_funtion_status;
  4930. unsigned short max_current_comsumption;
  4931. unsigned short support_current_limit; //function group 4
  4932. unsigned short support_driver_strength; //funciton group 3
  4933. unsigned short support_access_mode; //function group 1
  4934. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  4935. memset(status_data_buf, 0, 64);
  4936. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFFFF, RESPONSE_R1, response, status_data_buf, 64, 1);
  4937. if (ret)
  4938. return ret;
  4939. max_current_comsumption = SWAP_SHORT(switch_funtion_status->Max_Current_Consumption);
  4940. support_current_limit = SWAP_SHORT(switch_funtion_status->Function_Group[2]);
  4941. support_driver_strength = SWAP_SHORT(switch_funtion_status->Function_Group[3]);
  4942. support_access_mode = SWAP_SHORT(switch_funtion_status->Function_Group[5]);
  4943. printk("max_current_comsumption : %dmA\n", max_current_comsumption);
  4944. printk("support_current_limit : 0x%x\n", (unsigned int)support_current_limit);
  4945. printk("support_driver_strength : 0x%x\n", (unsigned int)support_driver_strength);
  4946. printk("support_access_mode : 0x%x\n", (unsigned int)support_access_mode);
  4947. if (support_access_mode & DDR50)
  4948. {
  4949. if (try_uhs_mode(sd_mmc_info, 0x00FFFFF4, DDR50) == 0)
  4950. return SD_MMC_NO_ERROR;
  4951. }
  4952. if (support_access_mode & SDR104)
  4953. {
  4954. if ((try_uhs_mode(sd_mmc_info, 0x00FFFFF3, SDR104) == 0) && (sd_tune_sample_clock(sd_mmc_info) == 0))
  4955. return SD_MMC_NO_ERROR;
  4956. }
  4957. if (support_access_mode & SDR50)
  4958. {
  4959. if ((try_uhs_mode(sd_mmc_info, 0x00FFFFF2, SDR50) == 0) && (sd_tune_sample_clock(sd_mmc_info) == 0))
  4960. return SD_MMC_NO_ERROR;
  4961. }
  4962. if (support_access_mode & SDR25)
  4963. {
  4964. if (try_uhs_mode(sd_mmc_info, 0x00FFFFF1, SDR25) == 0)
  4965. return SD_MMC_NO_ERROR;
  4966. }
  4967. if (support_access_mode & SDR12)
  4968. {
  4969. if (try_uhs_mode(sd_mmc_info, 0x00FFFFF0, SDR12) == 0)
  4970. return SD_MMC_NO_ERROR;
  4971. }
  4972. return SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  4973. }
  4974. static void my_disp_switch_status(SD_Switch_Function_Status_t *status)
  4975. {
  4976. int i;
  4977. printk("\n****************switch status****************\n");
  4978. printk("Data_Struction_Verion : %d\n", status->Data_Struction_Verion);
  4979. printk("Max_Current_Consumption : %d\n", SWAP_SHORT(status->Max_Current_Consumption));
  4980. for (i = 0; i < 6; i++)
  4981. {
  4982. printk("Support[%d] : 0x%x ", i, SWAP_SHORT(status->Function_Group[i]));
  4983. printk("Busy[%d] : 0x%x\n", i, SWAP_SHORT(status->Function_Status_In_Group[i]));
  4984. }
  4985. printk("Function_Group_Status6 : %d\n", status->Function_Group_Status6);
  4986. printk("Function_Group_Status5 : %d\n", status->Function_Group_Status5);
  4987. printk("Function_Group_Status4 : %d\n", status->Function_Group_Status4);
  4988. printk("Function_Group_Status3 : %d\n", status->Function_Group_Status3);
  4989. printk("Function_Group_Status2 : %d\n", status->Function_Group_Status2);
  4990. printk("Function_Group_Status1 : %d\n\n", status->Function_Group_Status1);
  4991. /*
  4992. unsigned short max_current_comsumption;
  4993. unsigned short support_current_limit;
  4994. unsigned short support_driver_strength;
  4995. unsigned short support_access_mode;
  4996. max_current_comsumption = SWAP_SHORT(status->Max_Current_Consumption);
  4997. support_current_limit = SWAP_SHORT(status->Function_Group[2]);
  4998. support_driver_strength = SWAP_SHORT(status->Function_Group[3]);
  4999. support_access_mode = SWAP_SHORT(status->Function_Group[5]);
  5000. printk("max_current_comsumption : %dmA\n", max_current_comsumption);
  5001. printk("support_current_limit : 0x%x\n", (unsigned int)support_current_limit);
  5002. printk("support_driver_strength : 0x%x\n", (unsigned int)support_driver_strength);
  5003. printk("support_access_mode : 0x%x\n", (unsigned int)support_access_mode);
  5004. */
  5005. }
  5006. static void my_disp_ss(unsigned char *pss, int size)
  5007. {
  5008. int i;
  5009. for (i = 0 ; i < size; i++)
  5010. {
  5011. printk("%02x", pss[i]);
  5012. if ((i % 4) == 3)
  5013. printk(" ");
  5014. if ((i % 16) == 15)
  5015. printk("\n");
  5016. }
  5017. }
  5018. int sd_mmc_switch_function(SD_MMC_Card_Info_t *sd_mmc_info)
  5019. {
  5020. int ret;
  5021. unsigned char response[MAX_RESPONSE_BYTES];
  5022. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  5023. unsigned char *mmc_ext_csd_buf = sd_mmc_info->sd_mmc_buf;
  5024. SD_Switch_Function_Status_t *switch_funtion_status;
  5025. MMC_REG_EXT_CSD_t *mmc_ext_csd_reg;
  5026. unsigned char read_reg_data;
  5027. unsigned char write_reg_data;
  5028. unsigned long sdio_config = 0;
  5029. SDIO_Config_Reg_t *config_reg = NULL;
  5030. if (sd_mmc_info->support_uhs_mode && using_sdxc_controller)
  5031. {
  5032. ret = sd_switch_to_uhs_mode(sd_mmc_info);
  5033. if (ret)
  5034. return ret;
  5035. }
  5036. else if(sd_mmc_info->spec_version || sd_mmc_info->card_type == CARD_TYPE_SDHC)
  5037. {
  5038. memset(status_data_buf, 0, 64);
  5039. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  5040. if(ret)
  5041. return ret;
  5042. my_disp_ss(status_data_buf, 64);
  5043. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  5044. if(switch_funtion_status->Max_Current_Consumption == 0)
  5045. return SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  5046. if(!((switch_funtion_status->Function_Group[5]>>8) & 0x02))
  5047. {
  5048. return SD_ERROR_NO_FUNCTION_SWITCH;
  5049. }
  5050. else
  5051. {
  5052. my_disp_switch_status(switch_funtion_status); //check disp
  5053. memset(status_data_buf, 0, 64);
  5054. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x80FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  5055. if(ret)
  5056. return ret;
  5057. my_disp_ss(status_data_buf, 64);
  5058. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  5059. if(switch_funtion_status->Max_Current_Consumption == 0 || switch_funtion_status->Function_Group_Status1 != 0x01)
  5060. return SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  5061. my_disp_switch_status(switch_funtion_status); //switch disp
  5062. if (using_sdxc_controller)
  5063. {
  5064. unsigned long sdxc_clk = 0;
  5065. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  5066. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  5067. sdxc_clk_reg->clk_ctl_en = 0;
  5068. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5069. sdxc_clk_reg->clk_div = CLK_DIV_50M; //sdxx
  5070. sdxc_clk_reg->clk_en = 1;
  5071. sdxc_clk_reg->clk_ctl_en = 1;
  5072. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5073. }
  5074. else
  5075. {
  5076. sdio_config = 0;
  5077. config_reg = (void *)&sdio_config;
  5078. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  5079. config_reg->cmd_clk_divide = 2;//aml_system_clk / (2*SD_MMC_TRANSFER_HIGHSPEED_CLK) -1;
  5080. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  5081. sd_mmc_info->sdio_clk = clk_get_rate(clk_get_sys("clk81", NULL))/2000000/(config_reg->cmd_clk_divide + 1);
  5082. sd_mmc_info->sdio_clk_unit = 1000/sd_mmc_info->sdio_clk;
  5083. }
  5084. sd_mmc_info->speed_class = HIGH_SPEED;
  5085. }
  5086. }
  5087. else if(sd_mmc_info->mmc_spec_version == SPEC_VERSION_40_41)
  5088. {
  5089. sd_delay_ms(2);
  5090. ret = sd_send_cmd_hw(sd_mmc_info,MMC_SEND_EXT_CSD, 0, RESPONSE_R1, response, mmc_ext_csd_buf, sizeof(MMC_REG_EXT_CSD_t), 1);
  5091. if(ret)
  5092. return ret;
  5093. mmc_ext_csd_reg = (MMC_REG_EXT_CSD_t *)mmc_ext_csd_buf;
  5094. if (mmc_ext_csd_reg->PARTITIONING_SUPPORT)
  5095. {
  5096. sd_mmc_info->emmc_boot_support = 1;
  5097. sd_mmc_info->emmc_boot_partition_size[0] = sd_mmc_info->emmc_boot_partition_size[1] = mmc_ext_csd_reg->BOOT_SIZE_MULTI * EMMC_BOOT_SIZE_UNIT;
  5098. }
  5099. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90100, RESPONSE_R1, response, 0, 0, 1);
  5100. if(ret)
  5101. return ret;
  5102. if (using_sdxc_controller)
  5103. {
  5104. unsigned long sdxc_clk = 0;
  5105. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  5106. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  5107. sdxc_clk_reg->clk_ctl_en = 0;
  5108. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5109. sdxc_clk_reg->clk_div = CLK_DIV_HS_MMC; //sdxx
  5110. sdxc_clk_reg->clk_en = 1;
  5111. sdxc_clk_reg->clk_ctl_en = 1;
  5112. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5113. }
  5114. else
  5115. {
  5116. sdio_config = 0;
  5117. config_reg = (void *)&sdio_config;
  5118. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  5119. config_reg->cmd_clk_divide = 1;
  5120. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  5121. sd_mmc_info->sdio_clk = clk_get_rate(clk_get_sys("clk81", NULL))/2000000/(config_reg->cmd_clk_divide + 1);
  5122. sd_mmc_info->sdio_clk_unit = 1000/sd_mmc_info->sdio_clk;
  5123. }
  5124. sd_mmc_info->speed_class = HIGH_SPEED;
  5125. }
  5126. else if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  5127. {
  5128. ret = sdio_read_reg(sd_mmc_info, 0, High_Speed_REG, &read_reg_data);
  5129. if(read_reg_data & SDIO_Support_High_Speed & (!ret))
  5130. {
  5131. write_reg_data = ((read_reg_data & 0xfd) | SDIO_Enable_High_Speed);
  5132. ret = sdio_write_reg(sd_mmc_info, 0, High_Speed_REG, &write_reg_data, SDIO_Read_After_Write);
  5133. if(!ret)
  5134. {
  5135. if (using_sdxc_controller)
  5136. {
  5137. unsigned long sdxc_clk = 0;
  5138. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  5139. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  5140. sdxc_clk_reg->clk_ctl_en = 0;
  5141. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5142. sdxc_clk_reg->clk_div = CLK_DIV_HS_SDIO; //sdxx
  5143. sdxc_clk_reg->clk_en = 1;
  5144. sdxc_clk_reg->clk_ctl_en = 1;
  5145. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5146. }
  5147. else
  5148. {
  5149. sdio_config = 0;
  5150. config_reg = (void *)&sdio_config;
  5151. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  5152. config_reg->cmd_clk_divide = 3;
  5153. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  5154. sd_mmc_info->sdio_clk = clk_get_rate(clk_get_sys("clk81", NULL))/2000000/(config_reg->cmd_clk_divide + 1);
  5155. sd_mmc_info->sdio_clk_unit = 1000/sd_mmc_info->sdio_clk;
  5156. }
  5157. sd_mmc_info->speed_class = HIGH_SPEED;
  5158. }
  5159. }
  5160. else //??? what about read High_Speed_REG error ??? //sdxx
  5161. {
  5162. if (using_sdxc_controller)
  5163. {
  5164. unsigned long sdxc_clk = 0;
  5165. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  5166. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  5167. sdxc_clk_reg->clk_ctl_en = 0;
  5168. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5169. sdxc_clk_reg->clk_div = CLK_DIV_IDENTIFY; //sdxx
  5170. sdxc_clk_reg->clk_en = 1;
  5171. sdxc_clk_reg->clk_ctl_en = 1;
  5172. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  5173. }
  5174. else
  5175. {
  5176. sdio_config = 0;
  5177. config_reg = (void *)&sdio_config;
  5178. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  5179. config_reg->cmd_clk_divide = 5;
  5180. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  5181. sd_mmc_info->sdio_clk = clk_get_rate(clk_get_sys("clk81", NULL))/2000000/(config_reg->cmd_clk_divide + 1);
  5182. sd_mmc_info->sdio_clk_unit = 1000/sd_mmc_info->sdio_clk;
  5183. }
  5184. }
  5185. }
  5186. if(!config_reg){
  5187. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  5188. config_reg = (void *)&sdio_config;
  5189. }
  5190. return SD_MMC_NO_ERROR;
  5191. }
  5192. int sd_check_sdio_card_type(SD_MMC_Card_Info_t *sd_mmc_info)
  5193. {
  5194. int error, function_no, timeout_count = SDIO_FUNCTION_TIMEOUT;
  5195. unsigned char read_reg_data;
  5196. unsigned char write_reg_data;
  5197. unsigned write_addr;
  5198. for(function_no=1; function_no<sd_mmc_info->sdio_function_nums; function_no++)
  5199. {
  5200. sd_mmc_info->sdio_blk_len[function_no] = 1;
  5201. read_reg_data = 0;
  5202. error = sdio_read_reg(sd_mmc_info, 0, function_no<<8, &read_reg_data);
  5203. if(error)
  5204. return error;
  5205. switch(read_reg_data) {
  5206. case 0:
  5207. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_NONE_SDIO;
  5208. break;
  5209. case 1:
  5210. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_STD_UART;
  5211. break;
  5212. case 2:
  5213. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_BT_TYPEA;
  5214. break;
  5215. case 3:
  5216. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_BT_TYPEB;
  5217. break;
  5218. case 4:
  5219. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_GPS;
  5220. break;
  5221. case 5:
  5222. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_CAMERA;
  5223. break;
  5224. case 6:
  5225. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_PHS;
  5226. break;
  5227. case 7:
  5228. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_WLAN;
  5229. break;
  5230. case 8:
  5231. case 9:
  5232. case 10:
  5233. case 11:
  5234. case 12:
  5235. case 13:
  5236. case 14:
  5237. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_NONE;
  5238. break;
  5239. case 15:
  5240. sd_mmc_info->sdio_card_type[function_no] = CARD_TYPE_SDIO_OTHER_IF;
  5241. break;
  5242. default:
  5243. break;
  5244. }
  5245. }
  5246. error = sdio_read_reg(sd_mmc_info, 0, IO_READY_REG, &write_reg_data);
  5247. if(error)
  5248. return error;
  5249. //function enable would do at up layer
  5250. /*write_reg_data |= 2;//((1<<sd_mmc_info->sdio_function_nums)-2);
  5251. error = sdio_write_reg(sd_mmc_info, 0, IO_ENABLE_REG, &write_reg_data, SDIO_Read_After_Write);
  5252. if(error)
  5253. return error;
  5254. while(timeout_count--)
  5255. {
  5256. error = sdio_read_reg(sd_mmc_info, 0, IO_READY_REG, &read_reg_data);
  5257. if(error)
  5258. return error;
  5259. if(read_reg_data == write_reg_data)
  5260. break;
  5261. else
  5262. sd_delay_ms(1);
  5263. }
  5264. #ifdef SD_MMC_DEBUG
  5265. Debug_Printf("#read_reg_data %x timeout_count %d \n", read_reg_data, timeout_count);
  5266. #endif*/
  5267. if(timeout_count > 0)
  5268. {
  5269. error = sdio_read_reg(sd_mmc_info, 0, Card_Capability_REG, &read_reg_data);
  5270. if(error)
  5271. return error;
  5272. if((read_reg_data) & SDIO_Support_Multi_Block)
  5273. {
  5274. if(SDIO_BLOCK_SIZE&0xFF)
  5275. {
  5276. write_reg_data = (SDIO_BLOCK_SIZE & 0xFF);
  5277. error = sdio_write_reg(sd_mmc_info, 0, FN0_Block_Size_Low_REG, &write_reg_data, SDIO_Read_After_Write);
  5278. if(error)
  5279. {
  5280. sd_mmc_info->sdio_blk_len[0] = 1;
  5281. return SD_MMC_NO_ERROR;
  5282. }
  5283. write_addr = ((2 << 8) | 0x10);
  5284. error = sdio_write_reg(sd_mmc_info, 0, write_addr, &write_reg_data, SDIO_Read_After_Write);
  5285. if(error)
  5286. {
  5287. sd_mmc_info->sdio_blk_len[2] = 1;
  5288. return SD_MMC_NO_ERROR;
  5289. }
  5290. }
  5291. write_reg_data = (SDIO_BLOCK_SIZE>>8);
  5292. error = sdio_write_reg(sd_mmc_info, 0, FN0_Block_Size_High_REG, &write_reg_data, SDIO_Read_After_Write);
  5293. if(error)
  5294. {
  5295. sd_mmc_info->sdio_blk_len[0] = 1;
  5296. }
  5297. else
  5298. {
  5299. sd_mmc_info->sdio_blk_len[0] = SDIO_BLOCK_SIZE;
  5300. }
  5301. write_addr = ((2 << 8) | 0x11);
  5302. error = sdio_write_reg(sd_mmc_info, 0, write_addr, &write_reg_data, SDIO_Read_After_Write);
  5303. if(error)
  5304. {
  5305. sd_mmc_info->sdio_blk_len[1] = 1;
  5306. }
  5307. else
  5308. {
  5309. sd_mmc_info->sdio_blk_len[2] = SDIO_BLOCK_SIZE;
  5310. }
  5311. }
  5312. else
  5313. {
  5314. return SD_SDIO_ERROR_NO_FUNCTION;
  5315. }
  5316. }
  5317. else
  5318. {
  5319. return SD_SDIO_ERROR_NO_FUNCTION;
  5320. }
  5321. if(error)
  5322. {
  5323. #ifdef SD_MMC_DEBUG
  5324. Debug_Printf("#%s error occured in sdio_open_interrupt()()\n", sd_error_to_string(error));
  5325. #endif
  5326. //return error;
  5327. }
  5328. return SD_MMC_NO_ERROR;
  5329. }
  5330. int sdio_read_reg(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, unsigned long sdio_register, unsigned char *reg_data)
  5331. {
  5332. int ret = 0;
  5333. unsigned long sdio_direct_rw = 0;
  5334. unsigned char response[MAX_RESPONSE_BYTES];
  5335. SDIO_IO_RW_CMD_ARG_t *sdio_io_direct_rw;
  5336. SDIO_RW_CMD_Response_R5_t * sdio_rw_response = (SDIO_RW_CMD_Response_R5_t *)response;
  5337. #ifdef SD_MMC_HW_CONTROL
  5338. if(SD_WORK_MODE == CARD_HW_MODE)
  5339. {
  5340. if (sd_mmc_info->sd_save_hw_io_flag) {
  5341. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  5342. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  5343. }
  5344. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  5345. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  5346. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  5347. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  5348. }
  5349. }
  5350. #endif
  5351. #ifdef SD_MMC_SW_CONTROL
  5352. if(SD_WORK_MODE == CARD_SW_MODE)
  5353. sd_mmc_io_config(sd_mmc_info);
  5354. #endif
  5355. sdio_io_direct_rw = (void *)&sdio_direct_rw;
  5356. sdio_io_direct_rw->Function_No = function_no;
  5357. sdio_io_direct_rw->Register_Address = (sdio_register & 0x1FFFF);
  5358. #ifdef SD_MMC_HW_CONTROL
  5359. if(SD_WORK_MODE == CARD_HW_MODE)
  5360. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_DIRECT, sdio_direct_rw, RESPONSE_R5, response, 0, 0, 1);
  5361. #endif
  5362. #ifdef SD_MMC_SW_CONTROL
  5363. if(SD_WORK_MODE == CARD_SW_MODE)
  5364. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_DIRECT, sdio_direct_rw, RESPONSE_R5, response);
  5365. #endif
  5366. if(ret)
  5367. return ret;
  5368. *reg_data = sdio_rw_response->read_or_write_data;
  5369. return SD_MMC_NO_ERROR;
  5370. }
  5371. int sdio_write_reg(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, unsigned int sdio_register, unsigned char *reg_data, unsigned read_after_write_flag)
  5372. {
  5373. int ret = 0;
  5374. unsigned long sdio_direct_rw = 0;
  5375. SDIO_IO_RW_CMD_ARG_t *sdio_io_direct_rw;
  5376. unsigned char response[MAX_RESPONSE_BYTES];
  5377. SDIO_RW_CMD_Response_R5_t * sdio_rw_response = (SDIO_RW_CMD_Response_R5_t *)response;
  5378. #ifdef SD_MMC_HW_CONTROL
  5379. if(SD_WORK_MODE == CARD_HW_MODE)
  5380. {
  5381. if (sd_mmc_info->sd_save_hw_io_flag) {
  5382. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  5383. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  5384. }
  5385. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  5386. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  5387. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  5388. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  5389. }
  5390. }
  5391. #endif
  5392. #ifdef SD_MMC_SW_CONTROL
  5393. if(SD_WORK_MODE == CARD_SW_MODE)
  5394. sd_mmc_io_config(sd_mmc_info);
  5395. #endif
  5396. sdio_io_direct_rw = (void *)&sdio_direct_rw;
  5397. sdio_io_direct_rw->R_W_Flag = SDIO_Write_Data;
  5398. sdio_io_direct_rw->RAW_Flag = read_after_write_flag;
  5399. sdio_io_direct_rw->Function_No = function_no;
  5400. sdio_io_direct_rw->write_data_bytes = (*reg_data);
  5401. sdio_io_direct_rw->Register_Address = (sdio_register & 0x1FFFF);
  5402. #ifdef SD_MMC_HW_CONTROL
  5403. if(SD_WORK_MODE == CARD_HW_MODE)
  5404. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_DIRECT, sdio_direct_rw, RESPONSE_R5, response, 0, 0, 0);
  5405. #endif
  5406. #ifdef SD_MMC_SW_CONTROL
  5407. if(SD_WORK_MODE == CARD_SW_MODE)
  5408. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_DIRECT, sdio_direct_rw, RESPONSE_R5, response);
  5409. #endif
  5410. #ifdef SD_MMC_DEBUG
  5411. //Debug_Printf("#sdio_write_reg write: %x addr: %x read: %x function_no %d\n", (*reg_data), sdio_register, sdio_rw_response->read_or_write_data, function_no);
  5412. #endif
  5413. if(ret)
  5414. return ret;
  5415. if(read_after_write_flag && (sdio_rw_response->read_or_write_data != (*reg_data))) {
  5416. #ifdef SD_MMC_DEBUG
  5417. Debug_Printf("#this sdio card could not support read after write\n");
  5418. #endif
  5419. return SD_MMC_NO_ERROR;
  5420. }
  5421. return SD_MMC_NO_ERROR;
  5422. }
  5423. int sdio_card_reset(SD_MMC_Card_Info_t *sd_mmc_info)
  5424. {
  5425. int ret;
  5426. unsigned char write_reg_data;
  5427. write_reg_data = SDIO_RES_bit;
  5428. ret = sdio_write_reg(sd_mmc_info, 0, IO_ABORT_REG, &write_reg_data, SDIO_DONT_Read_After_Write);
  5429. if(ret)
  5430. return ret;
  5431. return SD_MMC_NO_ERROR;
  5432. }
  5433. int sdio_data_transfer_abort(SD_MMC_Card_Info_t *sd_mmc_info, int function_no)
  5434. {
  5435. int ret;
  5436. unsigned char write_reg_data;
  5437. write_reg_data = function_no;
  5438. ret = sdio_write_reg(sd_mmc_info, 0, IO_ABORT_REG, &write_reg_data, SDIO_DONT_Read_After_Write);
  5439. if(ret)
  5440. return ret;
  5441. return SD_MMC_NO_ERROR;
  5442. }
  5443. int sdio_read_data_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long block_count, unsigned char *data_buf)
  5444. {
  5445. int ret;
  5446. unsigned char response[MAX_RESPONSE_BYTES];
  5447. unsigned long read_block_count, data_offset = 0;
  5448. unsigned long sdio_extend_rw = 0;
  5449. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  5450. while(block_count)
  5451. {
  5452. if(block_count > sd_mmc_info->max_blk_count)
  5453. read_block_count = sd_mmc_info->max_blk_count;
  5454. else
  5455. read_block_count = block_count;
  5456. sdio_io_extend_rw->R_W_Flag = SDIO_Read_Data;
  5457. sdio_io_extend_rw->Block_Mode = SDIO_Block_MODE;
  5458. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  5459. sdio_io_extend_rw->Function_No = function_no;
  5460. sdio_io_extend_rw->Byte_Block_Count = read_block_count;
  5461. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  5462. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response, data_buf+data_offset, read_block_count*sd_mmc_info->blk_len, 0);
  5463. if(ret)
  5464. return ret;
  5465. data_offset += read_block_count*sd_mmc_info->blk_len;
  5466. block_count -= read_block_count;
  5467. }
  5468. return SD_MMC_NO_ERROR;
  5469. }
  5470. int sdio_read_data_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long block_count, unsigned char *data_buf)
  5471. {
  5472. unsigned long data = 0, res = 0, temp = 0;
  5473. int ret, data_busy = 1, res_busy = 1;
  5474. unsigned long res_cnt = 0, data_cnt = 0, num_nac = 0, num_ncr = 0;
  5475. unsigned short crc16_array[4] = {0, 0, 0, 0};
  5476. unsigned short crc16 = 0;
  5477. unsigned long loop_num,blk_cnt;
  5478. int i,j;
  5479. #ifdef SD_MMC_CRC_CHECK
  5480. unsigned short crc_check = 0, crc_check_array[4]={0,0,0,0};
  5481. int error=0;
  5482. unsigned char *org_buf=data_buf;
  5483. #endif
  5484. unsigned char response[MAX_RESPONSE_BYTES];
  5485. unsigned long read_block_count, data_offset = 0;
  5486. unsigned long sdio_extend_rw = 0;
  5487. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  5488. while(block_count)
  5489. {
  5490. if(block_count > sd_mmc_info->max_blk_count)
  5491. read_block_count = sd_mmc_info->max_blk_count;
  5492. else
  5493. read_block_count = block_count;
  5494. sdio_io_extend_rw->R_W_Flag = SDIO_Read_Data;
  5495. sdio_io_extend_rw->Block_Mode = SDIO_Block_MODE;
  5496. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  5497. sdio_io_extend_rw->Function_No = function_no;
  5498. sdio_io_extend_rw->Byte_Block_Count = read_block_count;
  5499. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  5500. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_NONE, NULL);
  5501. if(ret)
  5502. return ret;
  5503. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  5504. {
  5505. sd_set_dat0_3_input();
  5506. }
  5507. else
  5508. {
  5509. sd_set_dat0_input();
  5510. }
  5511. sd_clear_response(response);
  5512. sd_delay_clocks_z(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  5513. sd_set_cmd_input();
  5514. //wait until both response and data is valid
  5515. do
  5516. {
  5517. sd_clk_transfer_low();
  5518. res = sd_get_cmd_value();
  5519. data = sd_get_dat0_value();
  5520. if (res_busy)
  5521. {
  5522. if (res)
  5523. num_ncr++;
  5524. else
  5525. res_busy = 0;
  5526. }
  5527. else
  5528. {
  5529. if (res_cnt < (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8))
  5530. {
  5531. response[res_cnt>>3] <<= 1;
  5532. response[res_cnt>>3] |= res;
  5533. res_cnt++;
  5534. }
  5535. }
  5536. if (data_busy)
  5537. {
  5538. if (data)
  5539. num_nac++;
  5540. else
  5541. data_busy = 0;
  5542. }
  5543. else
  5544. {
  5545. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  5546. {
  5547. data = sd_get_dat0_3_value();
  5548. temp <<= 4;
  5549. temp |= data;
  5550. #ifdef SD_MMC_CRC_CHECK
  5551. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  5552. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  5553. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  5554. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  5555. #endif
  5556. if((data_cnt & 0x01) == 1)
  5557. {
  5558. #ifdef AMLOGIC_CHIP_SUPPORT
  5559. if((unsigned long)data_buf == 0x3400000)
  5560. {
  5561. WRITE_BYTE_TO_FIFO(temp);
  5562. }
  5563. else
  5564. #endif
  5565. {
  5566. *data_buf = temp;
  5567. data_buf++;
  5568. }
  5569. temp = 0; //one byte received, clear temp varialbe
  5570. }
  5571. }
  5572. else //only data0 lines
  5573. {
  5574. data = sd_get_dat0_value();
  5575. temp <<= 1;
  5576. temp |= data;
  5577. if((data_cnt & 0x07) == 7)
  5578. {
  5579. #ifdef AMLOGIC_CHIP_SUPPORT
  5580. if((unsigned)data_buf == 0x3400000)
  5581. {
  5582. WRITE_BYTE_TO_FIFO(temp);
  5583. }
  5584. else
  5585. #endif
  5586. {
  5587. *data_buf = temp;
  5588. data_buf++;
  5589. }
  5590. #ifdef SD_MMC_CRC_CHECK
  5591. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  5592. #endif
  5593. temp = 0; //one byte received, clear temp varialbe
  5594. }
  5595. }
  5596. data_cnt++;
  5597. }
  5598. sd_clk_transfer_high();
  5599. if(!res_busy && !data_busy)
  5600. {
  5601. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  5602. {
  5603. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x01) == 0))
  5604. {
  5605. data_cnt >>= 1;
  5606. break;
  5607. }
  5608. }
  5609. else
  5610. {
  5611. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x07) == 0))
  5612. {
  5613. data_cnt >>= 3;
  5614. break;
  5615. }
  5616. }
  5617. }
  5618. }while((num_ncr < SD_MMC_TIME_NCR_MAX) && (num_nac < sd_mmc_info->clks_nac));
  5619. if((num_ncr >= SD_MMC_TIME_NCR_MAX) || (num_nac >= sd_mmc_info->clks_nac))
  5620. return SD_MMC_ERROR_TIMEOUT;
  5621. //Read all data blocks
  5622. loop_num = sd_mmc_info->blk_len;
  5623. for (blk_cnt = 0; blk_cnt < block_count; blk_cnt++)
  5624. {
  5625. //wait until data is valid
  5626. num_nac = 0;
  5627. do
  5628. {
  5629. if(!data_busy)
  5630. break;
  5631. sd_clk_transfer_low();
  5632. data = sd_get_dat0_value();
  5633. if(data)
  5634. {
  5635. num_nac++;
  5636. }
  5637. else
  5638. {
  5639. data_busy = 0;
  5640. }
  5641. sd_clk_transfer_high();
  5642. }while(data_busy && (num_nac < sd_mmc_info->clks_nac));
  5643. if(num_nac >= sd_mmc_info->clks_nac)
  5644. return SD_MMC_ERROR_TIMEOUT;
  5645. //Read data
  5646. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  5647. {
  5648. #ifdef AMLOGIC_CHIP_SUPPORT
  5649. if((unsigned long)data_buf == 0x3400000)
  5650. {
  5651. for(; data_cnt < loop_num; data_cnt++)
  5652. {
  5653. temp = 0; //clear temp varialbe
  5654. for(i = 0; i < 2; i++)
  5655. {
  5656. sd_clk_transfer_low();
  5657. data = sd_get_dat0_3_value();
  5658. temp <<= 4;
  5659. temp |= data;
  5660. sd_clk_transfer_high();
  5661. #ifdef SD_MMC_CRC_CHECK
  5662. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  5663. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  5664. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  5665. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  5666. #endif
  5667. }
  5668. WRITE_BYTE_TO_FIFO(temp);
  5669. }
  5670. }
  5671. else
  5672. #endif
  5673. {
  5674. for(; data_cnt < loop_num; data_cnt++)
  5675. {
  5676. temp = 0; //clear temp varialbe
  5677. for(i = 0; i < 2; i++)
  5678. {
  5679. sd_clk_transfer_low();
  5680. data = sd_get_dat0_3_value();
  5681. temp <<= 4;
  5682. temp |= data;
  5683. sd_clk_transfer_high();
  5684. #ifdef SD_MMC_CRC_CHECK
  5685. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  5686. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  5687. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  5688. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  5689. #endif
  5690. }
  5691. *data_buf = temp;
  5692. data_buf++;
  5693. }
  5694. }
  5695. //Read CRC16 data
  5696. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  5697. {
  5698. sd_clk_transfer_low();
  5699. crc16_array[0] <<= 1;
  5700. crc16_array[1] <<= 1;
  5701. crc16_array[2] <<= 1;
  5702. crc16_array[3] <<= 1;
  5703. data = sd_get_dat0_3_value();
  5704. crc16_array[0] |= (data & 0x01);
  5705. crc16_array[1] |= ((data >> 1) & 0x01);
  5706. crc16_array[2] |= ((data >> 2) & 0x01);
  5707. crc16_array[3] |= ((data >> 3) & 0x01);
  5708. sd_clk_transfer_high();
  5709. }
  5710. #ifdef SD_MMC_CRC_CHECK
  5711. for(i=0; i<4; i++)
  5712. {
  5713. //crc_check_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  5714. if(crc16_array[i] != crc_check_array[i])
  5715. {
  5716. error = SD_MMC_ERROR_DATA_CRC;
  5717. break;
  5718. }
  5719. }
  5720. #endif
  5721. }
  5722. else //only data0 lines
  5723. {
  5724. #ifdef AMLOGIC_CHIP_SUPPORT
  5725. if((unsigned long)data_buf == 0x3400000)
  5726. {
  5727. for(; data_cnt < loop_num; data_cnt++)
  5728. {
  5729. temp = 0; //clear temp varialbe
  5730. for(j = 0; j < 8; j++)
  5731. {
  5732. sd_clk_transfer_low();
  5733. data = sd_get_dat0_value();
  5734. temp <<= 1;
  5735. temp |= data;
  5736. sd_clk_transfer_high();
  5737. }
  5738. WRITE_BYTE_TO_FIFO(temp);
  5739. #ifdef SD_MMC_CRC_CHECK
  5740. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  5741. #endif
  5742. }
  5743. }
  5744. else
  5745. #endif
  5746. {
  5747. for(; data_cnt < loop_num; data_cnt++)
  5748. {
  5749. temp = 0; //clear temp varialbe
  5750. for(j = 0; j < 8; j++)
  5751. {
  5752. sd_clk_transfer_low();
  5753. data = sd_get_dat0_value();
  5754. temp <<= 1;
  5755. temp |= data;
  5756. sd_clk_transfer_high();
  5757. }
  5758. *data_buf = temp;
  5759. data_buf++;
  5760. #ifdef SD_MMC_CRC_CHECK
  5761. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  5762. #endif
  5763. }
  5764. }
  5765. //Read CRC16 data
  5766. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  5767. {
  5768. sd_clk_transfer_low();
  5769. data = sd_get_dat0_value();
  5770. crc16 <<= 1;
  5771. crc16 |= data;
  5772. sd_clk_transfer_high();
  5773. }
  5774. #ifdef SD_MMC_CRC_CHECK
  5775. if(crc16 != crc_check)
  5776. error = SD_MMC_ERROR_DATA_CRC;
  5777. #endif
  5778. }
  5779. sd_clk_transfer_low(); //for end bit
  5780. sd_clk_transfer_high();
  5781. data_busy = 1;
  5782. data_cnt = 0;
  5783. #ifdef SD_MMC_CRC_CHECK
  5784. org_buf = data_buf;
  5785. crc_check = 0;
  5786. crc_check_array[0] = crc_check_array[1] = crc_check_array[2] = crc_check_array[3] = 0;
  5787. #endif
  5788. }
  5789. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC); //Clock delay, Z type
  5790. data_offset += read_block_count*sd_mmc_info->blk_len;
  5791. block_count -= read_block_count;
  5792. }
  5793. return SD_MMC_NO_ERROR;
  5794. }
  5795. unsigned char sdio_4bytes_buf[PAGE_SIZE];
  5796. int sdio_read_data_byte_hw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  5797. {
  5798. int ret;
  5799. unsigned char response[MAX_RESPONSE_BYTES];
  5800. unsigned long read_byte_count, four_byte_count, data_offset = 0;
  5801. unsigned long sdio_extend_rw = 0;
  5802. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  5803. while(byte_count)
  5804. {
  5805. if(byte_count > 512)
  5806. read_byte_count = 512;
  5807. else
  5808. read_byte_count = byte_count;
  5809. sdio_io_extend_rw->R_W_Flag = SDIO_Read_Data;
  5810. sdio_io_extend_rw->Block_Mode = SDIO_Byte_MODE;
  5811. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  5812. sdio_io_extend_rw->Function_No = function_no;
  5813. sdio_io_extend_rw->Byte_Block_Count = read_byte_count;
  5814. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  5815. if(read_byte_count%4)
  5816. sd_mmc_info->sdio_read_crc_close = 1;
  5817. else
  5818. sd_mmc_info->sdio_read_crc_close = 0;
  5819. four_byte_count = (read_byte_count + 3) / 4;
  5820. four_byte_count *= 4;
  5821. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response, sdio_4bytes_buf, four_byte_count, 0);
  5822. if(ret)
  5823. return ret;
  5824. memcpy(data_buf + data_offset, sdio_4bytes_buf, read_byte_count);
  5825. data_offset += read_byte_count;
  5826. byte_count -= read_byte_count;
  5827. }
  5828. sd_mmc_info->sdio_read_crc_close = 0;
  5829. return SD_MMC_NO_ERROR;
  5830. }
  5831. int sdio_read_data_byte_sw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  5832. {
  5833. unsigned long data = 0, res = 0, temp = 0;
  5834. int ret, data_busy = 1, res_busy = 1;
  5835. unsigned long res_cnt = 0, data_cnt = 0, num_nac = 0, num_ncr = 0, crc_data_cnt = 0;
  5836. unsigned short crc16_array[4] = {0, 0, 0, 0};
  5837. unsigned short crc16 = 0;
  5838. unsigned long loop_num;
  5839. int i,j;
  5840. #ifdef SD_MMC_CRC_CHECK
  5841. unsigned short crc_check = 0, crc_check_array[4]={0,0,0,0};
  5842. int error=0;
  5843. //unsigned char *org_buf=data_buf;
  5844. #endif
  5845. unsigned char response[MAX_RESPONSE_BYTES];
  5846. unsigned long read_byte_count, data_offset = 0;
  5847. unsigned long sdio_extend_rw = 0;
  5848. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  5849. while(byte_count)
  5850. {
  5851. if(byte_count > 512)
  5852. read_byte_count = 512;
  5853. else
  5854. read_byte_count = byte_count;
  5855. sdio_io_extend_rw->R_W_Flag = SDIO_Read_Data;
  5856. sdio_io_extend_rw->Block_Mode = SDIO_Byte_MODE;
  5857. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  5858. sdio_io_extend_rw->Function_No = function_no;
  5859. sdio_io_extend_rw->Byte_Block_Count = read_byte_count;
  5860. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  5861. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_NONE, NULL);
  5862. if(ret)
  5863. return ret;
  5864. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  5865. {
  5866. sd_set_dat0_3_input();
  5867. }
  5868. else
  5869. {
  5870. sd_set_dat0_input();
  5871. }
  5872. sd_clear_response(response);
  5873. sd_delay_clocks_z(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  5874. sd_set_cmd_input();
  5875. //wait until both response and data is valid
  5876. do
  5877. {
  5878. sd_clk_transfer_low();
  5879. res = sd_get_cmd_value();
  5880. data = sd_get_dat0_value();
  5881. if(res_busy)
  5882. {
  5883. if (res)
  5884. num_ncr++;
  5885. else
  5886. res_busy = 0;
  5887. }
  5888. else
  5889. {
  5890. if (res_cnt < (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8))
  5891. {
  5892. response[res_cnt>>3] <<= 1;
  5893. response[res_cnt>>3] |= res;
  5894. res_cnt++;
  5895. }
  5896. }
  5897. if (data_busy)
  5898. {
  5899. if (data)
  5900. num_nac++;
  5901. else
  5902. data_busy = 0;
  5903. }
  5904. else
  5905. {
  5906. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  5907. {
  5908. if(data_cnt < read_byte_count*2)
  5909. {
  5910. data = sd_get_dat0_3_value();
  5911. temp <<= 4;
  5912. temp |= data;
  5913. #ifdef SD_MMC_CRC_CHECK
  5914. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  5915. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  5916. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  5917. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  5918. #endif
  5919. if((data_cnt & 0x01) == 1)
  5920. {
  5921. #ifdef AMLOGIC_CHIP_SUPPORT
  5922. if((unsigned long)data_buf == 0x3400000)
  5923. {
  5924. WRITE_BYTE_TO_FIFO(temp);
  5925. }
  5926. else
  5927. #endif
  5928. {
  5929. *data_buf = temp;
  5930. data_buf++;
  5931. }
  5932. temp = 0; //one byte received, clear temp varialbe
  5933. }
  5934. data_cnt++;
  5935. }
  5936. else if(crc_data_cnt < 16)
  5937. {
  5938. //Read CRC16 data
  5939. crc16_array[0] <<= 1;
  5940. crc16_array[1] <<= 1;
  5941. crc16_array[2] <<= 1;
  5942. crc16_array[3] <<= 1;
  5943. data = sd_get_dat0_3_value();
  5944. crc16_array[0] |= (data & 0x01);
  5945. crc16_array[1] |= ((data >> 1) & 0x01);
  5946. crc16_array[2] |= ((data >> 2) & 0x01);
  5947. crc16_array[3] |= ((data >> 3) & 0x01);
  5948. crc_data_cnt++;
  5949. }
  5950. }
  5951. else //only data0 lines
  5952. {
  5953. if(data_cnt < read_byte_count*8)
  5954. {
  5955. data = sd_get_dat0_value();
  5956. temp <<= 1;
  5957. temp |= data;
  5958. if((data_cnt & 0x07) == 7)
  5959. {
  5960. #ifdef AMLOGIC_CHIP_SUPPORT
  5961. if((unsigned)data_buf == 0x3400000)
  5962. {
  5963. WRITE_BYTE_TO_FIFO(temp);
  5964. }
  5965. else
  5966. #endif
  5967. {
  5968. *data_buf = temp;
  5969. data_buf++;
  5970. }
  5971. #ifdef SD_MMC_CRC_CHECK
  5972. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  5973. #endif
  5974. temp = 0; //one byte received, clear temp varialbe
  5975. }
  5976. }
  5977. data_cnt++;
  5978. }
  5979. }
  5980. sd_clk_transfer_high();
  5981. if(!res_busy && !data_busy)
  5982. {
  5983. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  5984. {
  5985. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x01) == 0))
  5986. {
  5987. data_cnt >>= 1;
  5988. break;
  5989. }
  5990. }
  5991. else
  5992. {
  5993. if((res_cnt >= (RESPONSE_R1_R3_R4_R5_R6_R7_LENGTH*8)) && ((data_cnt&0x07) == 0))
  5994. {
  5995. data_cnt >>= 3;
  5996. break;
  5997. }
  5998. }
  5999. }
  6000. }while((num_ncr < SD_MMC_TIME_NCR_MAX) && (num_nac < sd_mmc_info->clks_nac));
  6001. if((num_ncr >= SD_MMC_TIME_NCR_MAX) || (num_nac >= sd_mmc_info->clks_nac))
  6002. return SD_MMC_ERROR_TIMEOUT;
  6003. //Read data and response
  6004. loop_num = read_byte_count;
  6005. if(sd_mmc_info->bus_width == SD_BUS_WIDE) //4 data lines
  6006. {
  6007. #ifdef AMLOGIC_CHIP_SUPPORT
  6008. if((unsigned long)data_buf == 0x3400000)
  6009. {
  6010. for(; data_cnt < loop_num; data_cnt++)
  6011. {
  6012. temp = 0; //clear temp varialbe
  6013. for(i = 0; i < 2; i++)
  6014. {
  6015. sd_clk_transfer_low();
  6016. data = sd_get_dat0_3_value();
  6017. temp <<= 4;
  6018. temp |= data;
  6019. sd_clk_transfer_high();
  6020. #ifdef SD_MMC_CRC_CHECK
  6021. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  6022. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  6023. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  6024. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  6025. #endif
  6026. }
  6027. WRITE_BYTE_TO_FIFO(temp);
  6028. }
  6029. }
  6030. else
  6031. #endif
  6032. {
  6033. for(; data_cnt < loop_num; data_cnt++)
  6034. {
  6035. temp = 0; //clear temp varialbe
  6036. for(i = 0; i < 2; i++)
  6037. {
  6038. sd_clk_transfer_low();
  6039. data = sd_get_dat0_3_value();
  6040. temp <<= 4;
  6041. temp |= data;
  6042. sd_clk_transfer_high();
  6043. #ifdef SD_MMC_CRC_CHECK
  6044. SD_CAL_BIT_CRC(crc_check_array[0],data&0x01);
  6045. SD_CAL_BIT_CRC(crc_check_array[1],data&0x02);
  6046. SD_CAL_BIT_CRC(crc_check_array[2],data&0x04);
  6047. SD_CAL_BIT_CRC(crc_check_array[3],data&0x08);
  6048. #endif
  6049. }
  6050. *data_buf = temp;
  6051. data_buf++;
  6052. }
  6053. }
  6054. //Read CRC16 data
  6055. for(; crc_data_cnt < 16; crc_data_cnt++) // 16 bits CRC
  6056. {
  6057. sd_clk_transfer_low();
  6058. crc16_array[0] <<= 1;
  6059. crc16_array[1] <<= 1;
  6060. crc16_array[2] <<= 1;
  6061. crc16_array[3] <<= 1;
  6062. data = sd_get_dat0_3_value();
  6063. crc16_array[0] |= (data & 0x01);
  6064. crc16_array[1] |= ((data >> 1) & 0x01);
  6065. crc16_array[2] |= ((data >> 2) & 0x01);
  6066. crc16_array[3] |= ((data >> 3) & 0x01);
  6067. sd_clk_transfer_high();
  6068. }
  6069. #ifdef SD_MMC_CRC_CHECK
  6070. for(i=0; i<4; i++)
  6071. {
  6072. //crc_check_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  6073. if(crc16_array[i] != crc_check_array[i])
  6074. {
  6075. error = SD_MMC_ERROR_DATA_CRC;
  6076. break;
  6077. }
  6078. }
  6079. #endif
  6080. }
  6081. else //only data0 lines
  6082. {
  6083. #ifdef AMLOGIC_CHIP_SUPPORT
  6084. if((unsigned)data_buf == 0x3400000)
  6085. {
  6086. for(; data_cnt < loop_num; data_cnt++)
  6087. {
  6088. temp = 0; //clear temp varialbe
  6089. for(j = 0; j < 8; j++)
  6090. {
  6091. sd_clk_transfer_low();
  6092. data = sd_get_dat0_value();
  6093. temp <<= 1;
  6094. temp |= data;
  6095. sd_clk_transfer_high();
  6096. }
  6097. WRITE_BYTE_TO_FIFO(temp);
  6098. #ifdef SD_MMC_CRC_CHECK
  6099. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  6100. #endif
  6101. }
  6102. }
  6103. else
  6104. #endif
  6105. {
  6106. for(; data_cnt < loop_num; data_cnt++)
  6107. {
  6108. temp = 0; //clear temp varialbe
  6109. for(j = 0; j < 8; j++)
  6110. {
  6111. sd_clk_transfer_low();
  6112. data = sd_get_dat0_value();
  6113. temp <<= 1;
  6114. temp |= data;
  6115. sd_clk_transfer_high();
  6116. }
  6117. *data_buf = temp;
  6118. data_buf++;
  6119. #ifdef SD_MMC_CRC_CHECK
  6120. crc_check = (crc_check << 8) ^ sd_crc_table[((crc_check >> 8) ^ temp) & 0xff];
  6121. #endif
  6122. }
  6123. }
  6124. //Read CRC16 data
  6125. for(data_cnt = 0; data_cnt < 16; data_cnt++) // 16 bits CRC
  6126. {
  6127. sd_clk_transfer_low();
  6128. data = sd_get_dat0_value();
  6129. crc16 <<= 1;
  6130. crc16 |= data;
  6131. sd_clk_transfer_high();
  6132. }
  6133. #ifdef SD_MMC_CRC_CHECK
  6134. if(crc16 != crc_check)
  6135. error = SD_MMC_ERROR_DATA_CRC;
  6136. #endif
  6137. }
  6138. sd_clk_transfer_low(); //for end bit
  6139. sd_clk_transfer_high();
  6140. sd_delay_clocks_z(sd_mmc_info, SD_MMC_TIME_NRC_NCC); //Clock delay, Z type
  6141. data_offset += read_byte_count;
  6142. byte_count -= read_byte_count;
  6143. }
  6144. return SD_MMC_NO_ERROR;
  6145. }
  6146. int sdio_read_data(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  6147. {
  6148. int error = 0, ret;
  6149. unsigned long block_nums, byte_nums;
  6150. BUG_ON(sd_mmc_info->sdio_blk_len[function_no] == 0);
  6151. #ifdef SD_MMC_HW_CONTROL
  6152. if(SD_WORK_MODE == CARD_HW_MODE)
  6153. {
  6154. if (sd_mmc_info->sd_save_hw_io_flag) {
  6155. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  6156. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  6157. }
  6158. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  6159. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  6160. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  6161. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  6162. }
  6163. }
  6164. #endif
  6165. #ifdef SD_MMC_SW_CONTROL
  6166. if(SD_WORK_MODE == CARD_SW_MODE)
  6167. sd_mmc_io_config(sd_mmc_info);
  6168. #endif
  6169. sd_mmc_info->blk_len = sd_mmc_info->sdio_blk_len[function_no];
  6170. byte_nums = byte_count % sd_mmc_info->blk_len;
  6171. block_nums = byte_count / sd_mmc_info->blk_len;
  6172. if(block_nums == 0)
  6173. {
  6174. if(byte_nums)
  6175. {
  6176. #ifdef SD_MMC_HW_CONTROL
  6177. if(SD_WORK_MODE == CARD_HW_MODE)
  6178. error = sdio_read_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6179. #endif
  6180. #ifdef SD_MMC_SW_CONTROL
  6181. if(SD_WORK_MODE == CARD_SW_MODE)
  6182. error = sdio_read_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6183. #endif
  6184. if(error == SD_MMC_ERROR_TIMEOUT)
  6185. {
  6186. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6187. if(ret)
  6188. return ret;
  6189. #ifdef SD_MMC_HW_CONTROL
  6190. if(SD_WORK_MODE == CARD_HW_MODE)
  6191. error = sdio_read_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6192. #endif
  6193. #ifdef SD_MMC_SW_CONTROL
  6194. if(SD_WORK_MODE == CARD_SW_MODE)
  6195. error = sdio_read_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6196. #endif
  6197. if(error == SD_MMC_ERROR_TIMEOUT)
  6198. return error;
  6199. }
  6200. }
  6201. else
  6202. {
  6203. error = SD_MMC_ERROR_BLOCK_LEN;
  6204. #ifdef SD_MMC_DEBUG
  6205. Debug_Printf("#%s error occured in sdio_read_data()\n", sd_error_to_string(error));
  6206. #endif
  6207. return error;
  6208. }
  6209. if(error)
  6210. {
  6211. #ifdef SD_MMC_DEBUG
  6212. Debug_Printf("#%s error occured in sdio_read_byte()\n", sd_error_to_string(error));
  6213. #endif
  6214. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6215. if(ret)
  6216. return ret;
  6217. return error;
  6218. }
  6219. }
  6220. else
  6221. {
  6222. if(sd_mmc_info->blk_len == sd_mmc_info->sdio_blk_len[function_no])
  6223. {
  6224. #ifdef SD_MMC_HW_CONTROL
  6225. if(SD_WORK_MODE == CARD_HW_MODE)
  6226. {
  6227. error = sdio_read_data_block_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6228. if(error == SD_MMC_ERROR_TIMEOUT)
  6229. {
  6230. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6231. if(ret)
  6232. return ret;
  6233. error = sdio_read_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums*sd_mmc_info->blk_len, data_buf);
  6234. }
  6235. if(byte_nums)
  6236. {
  6237. error = sdio_read_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr + block_nums*sd_mmc_info->blk_len, byte_nums, data_buf + block_nums*sd_mmc_info->blk_len);
  6238. }
  6239. }
  6240. #endif
  6241. #ifdef SD_MMC_SW_CONTROL
  6242. if(SD_WORK_MODE == CARD_SW_MODE)
  6243. {
  6244. error = sdio_read_data_block_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6245. if(error == SD_MMC_ERROR_TIMEOUT)
  6246. {
  6247. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6248. if(ret)
  6249. return ret;
  6250. error = sdio_read_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums*sd_mmc_info->blk_len, data_buf);
  6251. }
  6252. if(byte_nums)
  6253. {
  6254. error = sdio_read_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr + block_nums*sd_mmc_info->blk_len, byte_nums, data_buf + block_nums*sd_mmc_info->blk_len);
  6255. }
  6256. }
  6257. #endif
  6258. }
  6259. else
  6260. {
  6261. #ifdef SD_MMC_HW_CONTROL
  6262. if(SD_WORK_MODE == CARD_HW_MODE)
  6263. error = sdio_read_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_count, data_buf);
  6264. #endif
  6265. #ifdef SD_MMC_SW_CONTROL
  6266. if(SD_WORK_MODE == CARD_SW_MODE)
  6267. error = sdio_read_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_count, data_buf);
  6268. #endif
  6269. }
  6270. if(error)
  6271. {
  6272. #ifdef SD_MMC_DEBUG
  6273. Debug_Printf("#%s error occured in sdio_read_block()\n", sd_error_to_string(error));
  6274. #endif
  6275. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6276. if(ret)
  6277. return ret;
  6278. return error;
  6279. }
  6280. }
  6281. return SD_MMC_NO_ERROR;
  6282. }
  6283. int sdio_write_data_block_hw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long block_count, unsigned char *data_buf)
  6284. {
  6285. int ret;
  6286. unsigned char response[MAX_RESPONSE_BYTES];
  6287. unsigned long write_block_count, data_offset = 0;
  6288. unsigned long sdio_extend_rw = 0;
  6289. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  6290. while(block_count)
  6291. {
  6292. if(block_count > sd_mmc_info->max_blk_count)
  6293. write_block_count = sd_mmc_info->max_blk_count;
  6294. else
  6295. write_block_count = block_count;
  6296. sdio_io_extend_rw->R_W_Flag = SDIO_Write_Data;
  6297. sdio_io_extend_rw->Block_Mode = SDIO_Block_MODE;
  6298. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  6299. sdio_io_extend_rw->Function_No = function_no;
  6300. sdio_io_extend_rw->Byte_Block_Count = write_block_count;
  6301. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  6302. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response, data_buf+data_offset, write_block_count*sd_mmc_info->blk_len, 0);
  6303. if(ret)
  6304. return ret;
  6305. data_offset += write_block_count*sd_mmc_info->blk_len;
  6306. block_count -= write_block_count;
  6307. }
  6308. return SD_MMC_NO_ERROR;
  6309. }
  6310. int sdio_write_data_block_sw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long block_count, unsigned char *data_buf)
  6311. {
  6312. unsigned long write_block_count, data_offset = 0;
  6313. int ret,i,j;
  6314. unsigned long crc_status, data;
  6315. unsigned long data_cnt = 0;
  6316. unsigned timeout;
  6317. unsigned char * org_buf = data_buf;
  6318. unsigned short crc16_array[4] = {0, 0, 0, 0};
  6319. unsigned short crc16;
  6320. unsigned char char_mode[4][3] = {{0x10, 0x01, 0},
  6321. {0x20, 0x02, 0},
  6322. {0x40, 0x04, 0},
  6323. {0x80, 0x08, 0}};
  6324. unsigned char response[MAX_RESPONSE_BYTES];
  6325. unsigned long loop_num,blk_cnt;
  6326. unsigned long sdio_extend_rw = 0;
  6327. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  6328. while(block_count)
  6329. {
  6330. if(block_count > sd_mmc_info->max_blk_count)
  6331. write_block_count = sd_mmc_info->max_blk_count;
  6332. else
  6333. write_block_count = block_count;
  6334. sdio_io_extend_rw->R_W_Flag = SDIO_Write_Data;
  6335. sdio_io_extend_rw->Block_Mode = SDIO_Block_MODE;
  6336. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  6337. sdio_io_extend_rw->Function_No = function_no;
  6338. sdio_io_extend_rw->Byte_Block_Count = write_block_count;
  6339. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  6340. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response);
  6341. if(ret)
  6342. return ret;
  6343. loop_num = sd_mmc_info->blk_len;
  6344. for(blk_cnt = 0; blk_cnt < write_block_count; blk_cnt++)
  6345. {
  6346. org_buf = data_buf;
  6347. //Nwr cycles delay
  6348. sd_delay_clocks_h(sd_mmc_info, SD_MMC_TIME_NWR);
  6349. //Start bit
  6350. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6351. {
  6352. sd_set_dat0_3_output();
  6353. sd_clk_transfer_low();
  6354. sd_set_dat0_3_value(0x00);
  6355. sd_clk_transfer_high();
  6356. }
  6357. else
  6358. {
  6359. sd_set_dat0_output();
  6360. sd_clk_transfer_low();
  6361. sd_set_dat0_value(0x00);
  6362. sd_clk_transfer_high();
  6363. }
  6364. //Write data
  6365. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6366. {
  6367. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  6368. {
  6369. for(i=1; i>=0; i--)
  6370. {
  6371. sd_clk_transfer_low();
  6372. data = (*data_buf >> (i<<2)) & 0x0F;
  6373. sd_set_dat0_3_value(data);
  6374. sd_clk_transfer_high();
  6375. }
  6376. data_buf++;
  6377. }
  6378. //Caculate CRC16 value and write to line
  6379. for(i=0; i<4; i++)
  6380. {
  6381. crc16_array[i] = sd_cal_crc_mode(org_buf, sd_mmc_info->blk_len, char_mode[i]);
  6382. }
  6383. //Write CRC16
  6384. for(i=15; i>=0; i--)
  6385. {
  6386. sd_clk_transfer_low();
  6387. data = 0;
  6388. for(j=3; j>=0; j--)
  6389. {
  6390. data <<= 1;
  6391. data |= (crc16_array[j] >> i) & 0x0001;
  6392. }
  6393. sd_set_dat0_3_value(data);
  6394. sd_clk_transfer_high();
  6395. }
  6396. }
  6397. else // only dat0 line
  6398. {
  6399. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  6400. {
  6401. for(i=7; i>=0; i--)
  6402. {
  6403. sd_clk_transfer_low();
  6404. data = (*data_buf >> i) & 0x01;
  6405. sd_set_dat0_value(data);
  6406. sd_clk_transfer_high();
  6407. }
  6408. data_buf++;
  6409. }
  6410. //Caculate CRC16 value and write to line
  6411. crc16 = sd_cal_crc16(org_buf, sd_mmc_info->blk_len);
  6412. //Write CRC16
  6413. for(i=15; i>=0; i--)
  6414. {
  6415. sd_clk_transfer_low();
  6416. data = (crc16 >> i) & 0x0001;
  6417. sd_set_dat0_value(data);
  6418. sd_clk_transfer_high();
  6419. }
  6420. }
  6421. //End bit
  6422. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6423. {
  6424. sd_clk_transfer_low();
  6425. sd_set_dat0_3_value(0x0F);
  6426. sd_clk_transfer_high();
  6427. sd_set_dat0_3_input();
  6428. }
  6429. else
  6430. {
  6431. sd_clk_transfer_low();
  6432. sd_set_dat0_value(0x01);
  6433. sd_clk_transfer_high();
  6434. sd_set_dat0_input();
  6435. }
  6436. sd_delay_clocks_h(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  6437. crc_status = 0;
  6438. //Check CRC status
  6439. sd_set_dat0_input();
  6440. for(i = 0; i < 5; i++)
  6441. {
  6442. sd_clk_transfer_low();
  6443. data = sd_get_dat0_value();
  6444. crc_status <<= 1;
  6445. crc_status |= data;
  6446. sd_clk_transfer_high();
  6447. }
  6448. if (crc_status == 0x0A) //1010, CRC error
  6449. return SD_MMC_ERROR_DATA_CRC;
  6450. else if (crc_status == 0x0F) //1111, Programming error
  6451. return SD_MMC_ERROR_DRIVER_FAILURE;
  6452. //0101, CRC ok
  6453. //Check busy
  6454. timeout = 0;
  6455. do
  6456. {
  6457. sd_clk_transfer_low();
  6458. data = sd_get_dat0_value();
  6459. sd_clk_transfer_high();
  6460. if(data)
  6461. break;
  6462. sd_delay_ms(1);
  6463. }while(timeout < SD_PROGRAMMING_TIMEOUT/TIMER_1MS);
  6464. if(timeout >= SD_PROGRAMMING_TIMEOUT/TIMER_1MS)
  6465. return SD_MMC_ERROR_TIMEOUT;
  6466. }
  6467. data_offset += write_block_count*sd_mmc_info->blk_len;
  6468. block_count -= write_block_count;
  6469. }
  6470. return SD_MMC_NO_ERROR;
  6471. }
  6472. int sdio_write_data_byte_hw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  6473. {
  6474. int ret;
  6475. unsigned char response[MAX_RESPONSE_BYTES];
  6476. unsigned long write_byte_count, data_offset = 0;
  6477. unsigned long sdio_extend_rw = 0;
  6478. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  6479. while(byte_count)
  6480. {
  6481. if(byte_count > 512)
  6482. write_byte_count = 512;
  6483. else
  6484. write_byte_count = byte_count;
  6485. sdio_io_extend_rw->R_W_Flag = SDIO_Write_Data;
  6486. sdio_io_extend_rw->Block_Mode = SDIO_Byte_MODE;
  6487. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  6488. sdio_io_extend_rw->Function_No = function_no;
  6489. sdio_io_extend_rw->Byte_Block_Count = write_byte_count;
  6490. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  6491. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response, data_buf+data_offset, write_byte_count, 0);
  6492. if(ret)
  6493. return ret;
  6494. data_offset += write_byte_count;
  6495. byte_count -= write_byte_count;
  6496. }
  6497. return SD_MMC_NO_ERROR;
  6498. }
  6499. int sdio_write_data_byte_sw(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  6500. {
  6501. int ret,i,j;
  6502. unsigned long crc_status, data;
  6503. unsigned long data_cnt = 0;
  6504. unsigned timeout;
  6505. unsigned char * org_buf = data_buf;
  6506. unsigned short crc16_array[4] = {0, 0, 0, 0};
  6507. unsigned short crc16;
  6508. unsigned char char_mode[4][3] = {{0x10, 0x01, 0},
  6509. {0x20, 0x02, 0},
  6510. {0x40, 0x04, 0},
  6511. {0x80, 0x08, 0}};
  6512. unsigned long loop_num;
  6513. unsigned char response[MAX_RESPONSE_BYTES];
  6514. unsigned long write_byte_count, data_offset = 0;
  6515. unsigned long sdio_extend_rw = 0;
  6516. SDIO_IO_RW_EXTENDED_ARG *sdio_io_extend_rw = (void *)&sdio_extend_rw;
  6517. while(byte_count)
  6518. {
  6519. if(byte_count > 512)
  6520. write_byte_count = 512;
  6521. else
  6522. write_byte_count = byte_count;
  6523. sdio_io_extend_rw->R_W_Flag = SDIO_Write_Data;
  6524. sdio_io_extend_rw->Block_Mode = SDIO_Byte_MODE;
  6525. sdio_io_extend_rw->OP_Code = buf_or_fifo;
  6526. sdio_io_extend_rw->Function_No = function_no;
  6527. sdio_io_extend_rw->Byte_Block_Count = write_byte_count;
  6528. sdio_io_extend_rw->Register_Address = ((sdio_addr+data_offset) & 0x1FFFF);
  6529. ret = sd_send_cmd_sw(sd_mmc_info, IO_RW_EXTENDED, sdio_extend_rw, RESPONSE_R5, response);
  6530. if(ret)
  6531. return ret;
  6532. loop_num = write_byte_count;
  6533. org_buf = data_buf;
  6534. //Nwr cycles delay
  6535. sd_delay_clocks_h(sd_mmc_info, SD_MMC_TIME_NWR);
  6536. //Start bit
  6537. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6538. {
  6539. sd_set_dat0_3_output();
  6540. sd_clk_transfer_low();
  6541. sd_set_dat0_3_value(0x00);
  6542. sd_clk_transfer_high();
  6543. }
  6544. else
  6545. {
  6546. sd_set_dat0_output();
  6547. sd_clk_transfer_low();
  6548. sd_set_dat0_value(0x00);
  6549. sd_clk_transfer_high();
  6550. }
  6551. //Write data
  6552. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6553. {
  6554. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  6555. {
  6556. for(i=1; i>=0; i--)
  6557. {
  6558. sd_clk_transfer_low();
  6559. data = (*data_buf >> (i<<2)) & 0x0F;
  6560. sd_set_dat0_3_value(data);
  6561. sd_clk_transfer_high();
  6562. }
  6563. data_buf++;
  6564. }
  6565. //Caculate CRC16 value and write to line
  6566. for(i=0; i<4; i++)
  6567. {
  6568. crc16_array[i] = sd_cal_crc_mode(org_buf, write_byte_count, char_mode[i]);
  6569. }
  6570. //Write CRC16
  6571. for(i=15; i>=0; i--)
  6572. {
  6573. sd_clk_transfer_low();
  6574. data = 0;
  6575. for(j=3; j>=0; j--)
  6576. {
  6577. data <<= 1;
  6578. data |= (crc16_array[j] >> i) & 0x0001;
  6579. }
  6580. sd_set_dat0_3_value(data);
  6581. sd_clk_transfer_high();
  6582. }
  6583. }
  6584. else // only dat0 line
  6585. {
  6586. for(data_cnt = 0; data_cnt < loop_num; data_cnt++)
  6587. {
  6588. for(i=7; i>=0; i--)
  6589. {
  6590. sd_clk_transfer_low();
  6591. data = (*data_buf >> i) & 0x01;
  6592. sd_set_dat0_value(data);
  6593. sd_clk_transfer_high();
  6594. }
  6595. data_buf++;
  6596. }
  6597. //Caculate CRC16 value and write to line
  6598. crc16 = sd_cal_crc16(org_buf, write_byte_count);
  6599. //Write CRC16
  6600. for(i=15; i>=0; i--)
  6601. {
  6602. sd_clk_transfer_low();
  6603. data = (crc16 >> i) & 0x0001;
  6604. sd_set_dat0_value(data);
  6605. sd_clk_transfer_high();
  6606. }
  6607. }
  6608. //End bit
  6609. if(sd_mmc_info->bus_width == SD_BUS_WIDE)
  6610. {
  6611. sd_clk_transfer_low();
  6612. sd_set_dat0_3_value(0x0F);
  6613. sd_clk_transfer_high();
  6614. sd_set_dat0_3_input();
  6615. }
  6616. else
  6617. {
  6618. sd_clk_transfer_low();
  6619. sd_set_dat0_value(0x01);
  6620. sd_clk_transfer_high();
  6621. sd_set_dat0_input();
  6622. }
  6623. sd_delay_clocks_h(sd_mmc_info, SD_MMC_Z_CMD_TO_RES);
  6624. crc_status = 0;
  6625. //Check CRC status
  6626. sd_set_dat0_input();
  6627. for(i = 0; i < 5; i++)
  6628. {
  6629. sd_clk_transfer_low();
  6630. data = sd_get_dat0_value();
  6631. crc_status <<= 1;
  6632. crc_status |= data;
  6633. sd_clk_transfer_high();
  6634. }
  6635. if (crc_status == 0x0A) //1010, CRC error
  6636. return SD_MMC_ERROR_DATA_CRC;
  6637. else if (crc_status == 0x0F) //1111, Programming error
  6638. return SD_MMC_ERROR_DRIVER_FAILURE;
  6639. //0101, CRC ok
  6640. //Check busy
  6641. timeout = 0;
  6642. do
  6643. {
  6644. sd_clk_transfer_low();
  6645. data = sd_get_dat0_value();
  6646. sd_clk_transfer_high();
  6647. if(data)
  6648. break;
  6649. sd_delay_ms(1);
  6650. }while(timeout < SD_PROGRAMMING_TIMEOUT/TIMER_1MS);
  6651. if(timeout >= SD_PROGRAMMING_TIMEOUT/TIMER_1MS)
  6652. return SD_MMC_ERROR_TIMEOUT;
  6653. data_offset += write_byte_count;
  6654. byte_count -= write_byte_count;
  6655. }
  6656. return SD_MMC_NO_ERROR;
  6657. }
  6658. int sdio_write_data(SD_MMC_Card_Info_t *sd_mmc_info, int function_no, int buf_or_fifo, unsigned long sdio_addr, unsigned long byte_count, unsigned char *data_buf)
  6659. {
  6660. int error = 0,ret;
  6661. unsigned long block_nums, byte_nums;
  6662. BUG_ON(sd_mmc_info->sdio_blk_len[function_no] == 0);
  6663. #ifdef SD_MMC_HW_CONTROL
  6664. if(SD_WORK_MODE == CARD_HW_MODE)
  6665. {
  6666. if (sd_mmc_info->sd_save_hw_io_flag) {
  6667. WRITE_CBUS_REG(SDIO_CONFIG, sd_mmc_info->sd_save_hw_io_config);
  6668. WRITE_CBUS_REG(SDIO_MULT_CONFIG, sd_mmc_info->sd_save_hw_io_mult_config);
  6669. }
  6670. if (sd_mmc_info->sdxc_save_hw_io_flag) {
  6671. WRITE_CBUS_REG(SD_REG2_CNTL, sd_mmc_info->sdxc_save_hw_io_ctrl);
  6672. WRITE_CBUS_REG(SD_REG4_CLKC, 0);
  6673. WRITE_CBUS_REG(SD_REG4_CLKC, sd_mmc_info->sdxc_save_hw_io_clk);
  6674. }
  6675. }
  6676. #endif
  6677. #ifdef SD_MMC_SW_CONTROL
  6678. if(SD_WORK_MODE == CARD_SW_MODE)
  6679. sd_mmc_io_config(sd_mmc_info);
  6680. #endif
  6681. sd_mmc_info->blk_len = sd_mmc_info->sdio_blk_len[function_no];
  6682. block_nums = sd_mmc_info->blk_len;
  6683. block_nums = byte_count / block_nums;
  6684. byte_nums = byte_count % sd_mmc_info->blk_len;
  6685. //printk("sdio write data addr %x at fun %d cnt: %d blk len %d\n", sdio_addr, function_no, byte_count, sd_mmc_info->blk_len);
  6686. if(block_nums == 0)
  6687. {
  6688. if(byte_nums)
  6689. {
  6690. #ifdef SD_MMC_HW_CONTROL
  6691. if(SD_WORK_MODE == CARD_HW_MODE)
  6692. error = sdio_write_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6693. #endif
  6694. #ifdef SD_MMC_SW_CONTROL
  6695. if(SD_WORK_MODE == CARD_SW_MODE)
  6696. error = sdio_write_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6697. #endif
  6698. if(error)
  6699. {
  6700. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6701. if(ret)
  6702. return ret;
  6703. #ifdef SD_MMC_HW_CONTROL
  6704. if(SD_WORK_MODE == CARD_HW_MODE)
  6705. error = sdio_write_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6706. #endif
  6707. #ifdef SD_MMC_SW_CONTROL
  6708. if(SD_WORK_MODE == CARD_SW_MODE)
  6709. error = sdio_write_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_nums, data_buf);
  6710. #endif
  6711. if(error)
  6712. return error;
  6713. }
  6714. }
  6715. else
  6716. {
  6717. error = SD_MMC_ERROR_BLOCK_LEN;
  6718. #ifdef SD_MMC_DEBUG
  6719. Debug_Printf("#%s error occured in sdio_write_data() blklen %d fun no %d\n", sd_error_to_string(error), sd_mmc_info->blk_len, function_no);
  6720. #endif
  6721. return error;
  6722. }
  6723. if(error)
  6724. {
  6725. #ifdef SD_MMC_DEBUG
  6726. Debug_Printf("#%s error occured in sdio_write_byte()\n", sd_error_to_string(error));
  6727. #endif
  6728. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6729. if(ret)
  6730. return ret;
  6731. return error;
  6732. }
  6733. }
  6734. else
  6735. {
  6736. if(sd_mmc_info->blk_len == sd_mmc_info->sdio_blk_len[function_no])
  6737. {
  6738. #ifdef SD_MMC_HW_CONTROL
  6739. if(SD_WORK_MODE == CARD_HW_MODE)
  6740. {
  6741. error = sdio_write_data_block_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6742. if(error)
  6743. {
  6744. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6745. if(ret)
  6746. return ret;
  6747. error = sdio_write_data_block_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6748. if(error)
  6749. {
  6750. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6751. if(ret)
  6752. return ret;
  6753. error = sdio_write_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums*sd_mmc_info->blk_len, data_buf);
  6754. }
  6755. }
  6756. if(byte_nums)
  6757. {
  6758. error = sdio_write_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr+block_nums*sd_mmc_info->blk_len, byte_nums, data_buf+block_nums*sd_mmc_info->blk_len);
  6759. }
  6760. }
  6761. #endif
  6762. #ifdef SD_MMC_SW_CONTROL
  6763. if(SD_WORK_MODE == CARD_SW_MODE)
  6764. {
  6765. error = sdio_write_data_block_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6766. if(error)
  6767. {
  6768. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6769. if(ret)
  6770. return ret;
  6771. error = sdio_write_data_block_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums, data_buf);
  6772. if(error)
  6773. {
  6774. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6775. if(ret)
  6776. return ret;
  6777. error = sdio_write_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, block_nums*sd_mmc_info->blk_len, data_buf);
  6778. }
  6779. }
  6780. if(byte_nums)
  6781. {
  6782. error = sdio_write_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr+block_nums*sd_mmc_info->blk_len, byte_nums, data_buf+block_nums*sd_mmc_info->blk_len);
  6783. }
  6784. }
  6785. #endif
  6786. }
  6787. else
  6788. {
  6789. #ifdef SD_MMC_HW_CONTROL
  6790. if(SD_WORK_MODE == CARD_HW_MODE)
  6791. error = sdio_write_data_byte_hw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_count, data_buf);
  6792. #endif
  6793. #ifdef SD_MMC_SW_CONTROL
  6794. if(SD_WORK_MODE == CARD_SW_MODE)
  6795. error = sdio_write_data_byte_sw(sd_mmc_info, function_no, buf_or_fifo, sdio_addr, byte_count, data_buf);
  6796. #endif
  6797. }
  6798. if(error)
  6799. {
  6800. #ifdef SD_MMC_DEBUG
  6801. Debug_Printf("#%s error occured in sdio_write_block() blklen %d fun no %d\n", sd_error_to_string(error), sd_mmc_info->blk_len, function_no);
  6802. #endif
  6803. ret = sdio_data_transfer_abort(sd_mmc_info, function_no);
  6804. if(ret)
  6805. return ret;
  6806. return error;
  6807. }
  6808. }
  6809. return SD_MMC_NO_ERROR;
  6810. }
  6811. int sdio_open_target_interrupt(SD_MMC_Card_Info_t *sd_mmc_info, int function_no)
  6812. {
  6813. int error = 0;
  6814. unsigned char read_reg_data, write_reg_data;
  6815. error = sdio_read_reg(sd_mmc_info, 0, Card_Capability_REG, &read_reg_data);
  6816. if(error)
  6817. return error;
  6818. write_reg_data = ((1 << function_no) | SDIO_INT_EN_MASK);
  6819. error = sdio_write_reg(sd_mmc_info, 0, INT_ENABLE_REG, &write_reg_data, SDIO_Read_After_Write);
  6820. if(error)
  6821. return error;
  6822. return SD_MMC_NO_ERROR;
  6823. }
  6824. int sdio_close_target_interrupt(SD_MMC_Card_Info_t *sd_mmc_info, int function_no)
  6825. {
  6826. int error = 0;
  6827. unsigned char read_reg_data, write_reg_data;
  6828. error = sdio_read_reg(sd_mmc_info, 0, Card_Capability_REG, &read_reg_data);
  6829. if(error)
  6830. return error;
  6831. write_reg_data = 0;
  6832. error = sdio_write_reg(sd_mmc_info, 0, INT_ENABLE_REG, &write_reg_data, SDIO_Read_After_Write);
  6833. if(error)
  6834. return error;
  6835. return SD_MMC_NO_ERROR;
  6836. }
  6837. /*sdio_select_card & sdio_read_rca & sdio_rw_direct used by nrx600,
  6838. claim host in nano_download
  6839. */
  6840. int sdio_select_card(struct memory_card *card)
  6841. {
  6842. int ret;
  6843. SD_MMC_Card_Info_t *sd_mmc_info;
  6844. unsigned char response[MAX_RESPONSE_BYTES];
  6845. BUG_ON(!card);
  6846. sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  6847. card->host->card_busy = card;
  6848. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD,
  6849. sd_mmc_info->card_rca<<16, RESPONSE_R1B, response, 0,
  6850. 0, 1);
  6851. if(ret)
  6852. printk("[sdio_select_card] ret = %d\n", ret);
  6853. return ret;
  6854. }
  6855. EXPORT_SYMBOL(sdio_select_card);
  6856. int sdio_read_rca(struct memory_card *card, unsigned* rca)
  6857. {
  6858. int ret, slot_id;
  6859. unsigned char response[MAX_RESPONSE_BYTES];
  6860. SD_MMC_Card_Info_t *sd_mmc_info;
  6861. BUG_ON(!card);
  6862. sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  6863. card->host->card_busy = card;
  6864. slot_id = 1;
  6865. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, slot_id<<16,
  6866. RESPONSE_R6, response, 0, 0, 0); ///* Send out a byte to read RCA*/
  6867. if(ret)
  6868. printk("[sdio_read_rca] ret = %d\n", ret);
  6869. sd_mmc_info->card_rca = ((SD_Response_R6_t *)response)->rca_high << 8 |
  6870. ((SD_Response_R6_t *)response)->rca_low;
  6871. *rca = sd_mmc_info->card_rca;
  6872. printk("*rca = %x\n", *rca);
  6873. return ret;
  6874. }
  6875. EXPORT_SYMBOL(sdio_read_rca);
  6876. int sdio_rw_direct(struct memory_card *card, unsigned int arg)
  6877. {
  6878. int ret;
  6879. unsigned char response[MAX_RESPONSE_BYTES];
  6880. SD_MMC_Card_Info_t *sd_mmc_info;
  6881. BUG_ON(!card);
  6882. sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  6883. card->host->card_busy = card;
  6884. ret = sd_send_cmd_hw(sd_mmc_info, IO_RW_DIRECT, arg, RESPONSE_R5,
  6885. response, 0, 0, 1);
  6886. if(ret)
  6887. printk("[sdio_rw_direct] ret = %d\n", ret);
  6888. return ret;
  6889. }
  6890. EXPORT_SYMBOL(sdio_rw_direct);
  6891. /*void sd_mmc_get_info(blkdev_stat_t *info)
  6892. {
  6893. if(info->magic != BLKDEV_STAT_MAGIC)
  6894. return;
  6895. info->valid = 1;
  6896. info->blk_size = sd_mmc_info->blk_len;
  6897. info->blk_num = sd_mmc_info->blk_nums;
  6898. info->serial_no = sd_mmc_info->card_psn;
  6899. info->st_write_protect = sd_mmc_info->write_protected_flag;
  6900. switch(sd_mmc_info->card_type)
  6901. {
  6902. case CARD_TYPE_SD:
  6903. info->blkdev_name = "SD card";
  6904. break;
  6905. case CARD_TYPE_SDHC:
  6906. info->blkdev_name = "SDHC card";
  6907. break;
  6908. case CARD_TYPE_MMC:
  6909. info->blkdev_name = "MMC card";
  6910. break;
  6911. default:
  6912. break;
  6913. }
  6914. }*/
  6915. //lin
  6916. #define SDXC_B_ENABLE CBUS_REG_ADDR(0x201b)
  6917. #define SDXC_B_OUTPUT CBUS_REG_ADDR(0x201c)
  6918. #define SDXC_B_INPUT CBUS_REG_ADDR(0x201d)
  6919. static struct aml_card_info my_card_info[] = {
  6920. [0] = {
  6921. .name = "inand_card_sdxc",
  6922. .work_mode = CARD_HW_MODE,
  6923. .io_pad_type = SDXC_BOOT_0_11,
  6924. .card_ins_en_reg = 0,
  6925. .card_ins_en_mask = 0,
  6926. .card_ins_input_reg = 0,
  6927. .card_ins_input_mask = 0,
  6928. .card_power_en_reg = BOOT_GPIO_ENABLE,
  6929. .card_power_en_mask = PREG_IO_9_MASK,
  6930. .card_power_output_reg = BOOT_GPIO_OUTPUT,
  6931. .card_power_output_mask = PREG_IO_9_MASK,
  6932. .card_power_en_lev = 1,
  6933. .card_wp_en_reg = 0,
  6934. .card_wp_en_mask = 0,
  6935. .card_wp_input_reg = 0,
  6936. .card_wp_input_mask = 0,
  6937. .card_extern_init = 0,
  6938. },
  6939. [1] = {
  6940. .name = "inand_card_sdhc",
  6941. .work_mode = CARD_HW_MODE,
  6942. .io_pad_type = SDHC_BOOT_0_11,
  6943. .card_ins_en_reg = 0,
  6944. .card_ins_en_mask = 0,
  6945. .card_ins_input_reg = 0,
  6946. .card_ins_input_mask = 0,
  6947. .card_power_en_reg = BOOT_GPIO_ENABLE,
  6948. .card_power_en_mask = PREG_IO_9_MASK,
  6949. .card_power_output_reg = BOOT_GPIO_OUTPUT,
  6950. .card_power_output_mask = PREG_IO_9_MASK,
  6951. .card_power_en_lev = 1,
  6952. .card_wp_en_reg = 0,
  6953. .card_wp_en_mask = 0,
  6954. .card_wp_input_reg = 0,
  6955. .card_wp_input_mask = 0,
  6956. .card_extern_init = 0,
  6957. },
  6958. [3] = { //m3 sdhc
  6959. .name = "sd_card_sdxc",
  6960. .work_mode = CARD_HW_MODE,
  6961. .io_pad_type = SDXC_CARD_0_5, //SDXC-B
  6962. .card_ins_en_reg = SDXC_B_ENABLE,
  6963. .card_ins_en_mask = PREG_IO_29_MASK,
  6964. .card_ins_input_reg = SDXC_B_INPUT,
  6965. .card_ins_input_mask = PREG_IO_29_MASK,
  6966. .card_power_en_reg = SDXC_B_ENABLE,
  6967. .card_power_en_mask = PREG_IO_31_MASK,
  6968. .card_power_output_reg = SDXC_B_OUTPUT,
  6969. .card_power_output_mask = PREG_IO_31_MASK,
  6970. .card_power_en_lev = 0,
  6971. .card_wp_en_reg = 0,
  6972. .card_wp_en_mask = 0,
  6973. .card_wp_input_reg = 0,
  6974. .card_wp_input_mask = 0,
  6975. .card_extern_init = 0,
  6976. },
  6977. [4] = {
  6978. .name = "sd_card_sdhc",
  6979. .work_mode = CARD_HW_MODE,
  6980. .io_pad_type = SDHC_CARD_0_5, //SDHC-B
  6981. .card_ins_en_reg = CARD_GPIO_ENABLE,
  6982. .card_ins_en_mask = PREG_IO_29_MASK,
  6983. .card_ins_input_reg = CARD_GPIO_INPUT,
  6984. .card_ins_input_mask = PREG_IO_29_MASK,
  6985. .card_power_en_reg = CARD_GPIO_ENABLE,
  6986. .card_power_en_mask = PREG_IO_31_MASK,
  6987. .card_power_output_reg = CARD_GPIO_OUTPUT,
  6988. .card_power_output_mask = PREG_IO_31_MASK,
  6989. .card_power_en_lev = 0,
  6990. .card_wp_en_reg = 0,
  6991. .card_wp_en_mask = 0,
  6992. .card_wp_input_reg = 0,
  6993. .card_wp_input_mask = 0,
  6994. .card_extern_init = 0,
  6995. },
  6996. [2] = { //m1 sdio
  6997. .name = "sd_card",
  6998. .work_mode = CARD_HW_MODE,
  6999. .io_pad_type = SDHC_CARD_0_5,
  7000. .card_ins_en_reg = CARD_GPIO_ENABLE,
  7001. .card_ins_en_mask = PREG_IO_29_MASK,
  7002. .card_ins_input_reg = CARD_GPIO_INPUT,
  7003. .card_ins_input_mask = PREG_IO_29_MASK,
  7004. .card_power_en_reg = CARD_GPIO_ENABLE,
  7005. .card_power_en_mask = PREG_IO_31_MASK,
  7006. .card_power_output_reg = CARD_GPIO_OUTPUT,
  7007. .card_power_output_mask = PREG_IO_31_MASK,
  7008. .card_power_en_lev = 0,
  7009. .card_wp_en_reg = 0,
  7010. .card_wp_en_mask = 0,
  7011. .card_wp_input_reg = 0,
  7012. .card_wp_input_mask = 0,
  7013. .card_extern_init = 0,
  7014. },
  7015. };
  7016. static int myidx = 0;
  7017. static struct memory_card *sdxc_card = NULL;
  7018. static unsigned int my_parse_num(char *buf, char **res_buf)
  7019. {
  7020. unsigned int value;
  7021. unsigned int c;
  7022. value = 0;
  7023. while(1)
  7024. {
  7025. c = *buf++;
  7026. if (c >= '0' && c <= '9')
  7027. {
  7028. value = value * 10 + c - '0';
  7029. }
  7030. else
  7031. {
  7032. break;
  7033. }
  7034. }
  7035. if (res_buf != NULL)
  7036. *res_buf = buf;
  7037. return value;
  7038. }
  7039. static void my_test(char *buf)
  7040. {
  7041. char *pcur;
  7042. int t1 = my_parse_num(buf, &pcur);
  7043. int t2 = my_parse_num(pcur, &pcur);
  7044. int t3 = my_parse_num(pcur, &pcur);
  7045. int i;
  7046. struct card_host *host = sdxc_card->host;
  7047. __card_claim_host(host, sdxc_card);
  7048. ///sd_io_init(sdxc_card);
  7049. using_sdxc_controller = 0; //reset for sd_io_init()
  7050. switch (t1) {
  7051. case 1 :
  7052. {
  7053. printk("test gpio\n");
  7054. sd_set_cmd_output();
  7055. sd_set_cmd_value(t2);
  7056. sd_set_clk_output();
  7057. sd_set_clk_low();
  7058. sd_set_dat0_3_output();
  7059. sd_set_dat0_3_value(t3);
  7060. msleep(10);
  7061. i = 10;
  7062. while (i--) {
  7063. sd_set_dat0_3_value(--t3);
  7064. msleep(2);
  7065. }
  7066. }
  7067. break;
  7068. case 2 :
  7069. {
  7070. unsigned int value, value2, value3;
  7071. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7072. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  7073. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_5);
  7074. printk("MUX2-sdxc:[0x%08x]/[0x%02x], MUX4:[0x%08x]/[0x%02x], MUX5:[0x%08x]/[0x%02x]\n",
  7075. value, (value >> 4) & 0x1F, value2, (value2 >> 26) & 0x1F, value3, (value3 >> 10) & 0x1F);
  7076. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7077. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  7078. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_8);
  7079. printk("MUX2-sdhc:[0x%08x]/[0x%02x], MUX6:[0x%08x]/[0x%02x], MUX8:[0x%08x]/[0x%02x]\n",
  7080. value, (value >> 10) & 0x3F, value2, (value2 >> 24) & 0x3F, value3, (value3 >> 0) & 0x3F);
  7081. }
  7082. break;
  7083. case 3 :
  7084. {
  7085. unsigned int value, value2, value3;
  7086. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7087. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  7088. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_5);
  7089. printk("MUX2-sdxc:[0x%08x]/[0x%02x], MUX4:[0x%08x]/[0x%02x], MUX5:[0x%08x]/[0x%02x]\n",
  7090. value, (value >> 4) & 0x1F, value2, (value2 >> 26) & 0x1F, value3, (value3 >> 10) & 0x1F);
  7091. value &= ~0x0FFF0000;
  7092. WRITE_CBUS_REG(PERIPHS_PIN_MUX_2, value);
  7093. value2 &= ~0x7FFFFFFF;
  7094. WRITE_CBUS_REG(PERIPHS_PIN_MUX_3, value2);
  7095. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7096. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  7097. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_8);
  7098. printk("MUX2-sdhc:[0x%08x]/[0x%02x], MUX6:[0x%08x]/[0x%02x], MUX8:[0x%08x]/[0x%02x]\n",
  7099. value, (value >> 10) & 0x3F, value2, (value2 >> 24) & 0x3F, value3, (value3 >> 0) & 0x3F);
  7100. }
  7101. break;
  7102. case 4 :
  7103. {
  7104. unsigned int value4, value6, value2, value3;
  7105. value4 = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  7106. value6 = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  7107. value2 = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7108. value3 = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  7109. printk("MUX4:[0x%08x]/[0x%02x], MUX6:[0x%08x]/[0x%02x], MUX2:[0x%08x]/[0x%03x], MUX3:[0x%08x]/[0x%02x]\n",
  7110. value4, (value4 >> 26) & 0x1F, value6, (value6 >> 24) & 0x3F, value2, (value2 >> 16) & 0xFFF, value3, (value3 >> 31) & 0x01);
  7111. }
  7112. break;
  7113. case 5 :
  7114. {
  7115. printk("PINMUX :\n[0x%08x], [0x%08x], [0x%08x], [0x%08x]\n[0x%08x], [0x%08x], [0x%08x], [0x%08x]\n[0x%08x], [0x%08x], [0x%08x], [0x%08x], [0x%08x]\n",
  7116. READ_CBUS_REG(PERIPHS_PIN_MUX_0), READ_CBUS_REG(PERIPHS_PIN_MUX_1), READ_CBUS_REG(PERIPHS_PIN_MUX_2), READ_CBUS_REG(PERIPHS_PIN_MUX_3),
  7117. READ_CBUS_REG(PERIPHS_PIN_MUX_4), READ_CBUS_REG(PERIPHS_PIN_MUX_5), READ_CBUS_REG(PERIPHS_PIN_MUX_6), READ_CBUS_REG(PERIPHS_PIN_MUX_7),
  7118. READ_CBUS_REG(PERIPHS_PIN_MUX_8), READ_CBUS_REG(PERIPHS_PIN_MUX_9), READ_CBUS_REG(PERIPHS_PIN_MUX_10), READ_CBUS_REG(PERIPHS_PIN_MUX_11), READ_CBUS_REG(PERIPHS_PIN_MUX_12));
  7119. }
  7120. break;
  7121. case 6 : //clear t2[t3]
  7122. {
  7123. unsigned int value;
  7124. printk("clear PIN_MUX_%d\n", t2);
  7125. switch (t2) {
  7126. case 0 :
  7127. value = READ_CBUS_REG(PERIPHS_PIN_MUX_0);
  7128. value &= ~t3;
  7129. WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, value);
  7130. break;
  7131. case 1 :
  7132. value = READ_CBUS_REG(PERIPHS_PIN_MUX_1);
  7133. value &= ~t3;
  7134. WRITE_CBUS_REG(PERIPHS_PIN_MUX_1, value);
  7135. break;
  7136. case 2 :
  7137. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7138. value &= ~t3;
  7139. WRITE_CBUS_REG(PERIPHS_PIN_MUX_2, value);
  7140. break;
  7141. case 3 :
  7142. value = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  7143. value &= ~t3;
  7144. WRITE_CBUS_REG(PERIPHS_PIN_MUX_3, value);
  7145. break;
  7146. case 4 :
  7147. value = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  7148. value &= ~t3;
  7149. WRITE_CBUS_REG(PERIPHS_PIN_MUX_4, value);
  7150. break;
  7151. case 5 :
  7152. value = READ_CBUS_REG(PERIPHS_PIN_MUX_5);
  7153. value &= ~t3;
  7154. WRITE_CBUS_REG(PERIPHS_PIN_MUX_5, value);
  7155. break;
  7156. case 6 :
  7157. value = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  7158. value &= ~t3;
  7159. WRITE_CBUS_REG(PERIPHS_PIN_MUX_6, value);
  7160. break;
  7161. case 7 :
  7162. value = READ_CBUS_REG(PERIPHS_PIN_MUX_7);
  7163. value &= ~t3;
  7164. WRITE_CBUS_REG(PERIPHS_PIN_MUX_7, value);
  7165. break;
  7166. case 8 :
  7167. value = READ_CBUS_REG(PERIPHS_PIN_MUX_8);
  7168. value &= ~t3;
  7169. WRITE_CBUS_REG(PERIPHS_PIN_MUX_8, value);
  7170. break;
  7171. case 9 :
  7172. value = READ_CBUS_REG(PERIPHS_PIN_MUX_9);
  7173. value &= ~t3;
  7174. WRITE_CBUS_REG(PERIPHS_PIN_MUX_9, value);
  7175. break;
  7176. default :
  7177. break;
  7178. }
  7179. }
  7180. break;
  7181. case 7 : //set t2[t3]
  7182. {
  7183. unsigned int value;
  7184. printk("set PIN_MUX_%d\n", t2);
  7185. switch (t2) {
  7186. case 2 :
  7187. value = READ_CBUS_REG(PERIPHS_PIN_MUX_2);
  7188. value |= t3;
  7189. WRITE_CBUS_REG(PERIPHS_PIN_MUX_2, value);
  7190. break;
  7191. case 3 :
  7192. value = READ_CBUS_REG(PERIPHS_PIN_MUX_3);
  7193. value |= t3;
  7194. WRITE_CBUS_REG(PERIPHS_PIN_MUX_3, value);
  7195. break;
  7196. case 4 :
  7197. value = READ_CBUS_REG(PERIPHS_PIN_MUX_4);
  7198. value |= t3;
  7199. WRITE_CBUS_REG(PERIPHS_PIN_MUX_4, value);
  7200. break;
  7201. case 6 :
  7202. value = READ_CBUS_REG(PERIPHS_PIN_MUX_6);
  7203. value |= t3;
  7204. WRITE_CBUS_REG(PERIPHS_PIN_MUX_6, value);
  7205. break;
  7206. default :
  7207. break;
  7208. }
  7209. }
  7210. break;
  7211. case 8 :
  7212. printk("set myt1 from %d to %d\n", myt1, t2);
  7213. myt1 = t2;
  7214. break;
  7215. default :
  7216. break;
  7217. }
  7218. card_release_host(host);
  7219. }
  7220. static struct memory_card* sdxc_card_setup(struct card_host *host, int idx)
  7221. {
  7222. //int err = 0;
  7223. struct memory_card* card;
  7224. //SD_MMC_Card_Info_t *sd_mmc_info;
  7225. card = kzalloc(sizeof(struct memory_card), GFP_KERNEL);
  7226. if (!card)
  7227. return ERR_PTR(-ENOMEM);
  7228. card_init_card(card, host);
  7229. card->unit_state = CARD_UNIT_NOT_READY;
  7230. strcpy(card->name, "sdxc");
  7231. card->card_type = CARD_SECURE_DIGITAL;
  7232. card->card_plat_info = &my_card_info[idx];
  7233. printk("setup card %s\n", card->card_plat_info->name);
  7234. if ((card->card_plat_info->io_pad_type == SDXC_CARD_0_5) ||
  7235. (card->card_plat_info->io_pad_type == SDXC_BOOT_0_11) ||
  7236. (card->card_plat_info->io_pad_type == SDXC_GPIOX_0_9))
  7237. myidx = 0;
  7238. else
  7239. myidx = 1;
  7240. /*
  7241. __card_claim_host(host, card);
  7242. err = sd_mmc_probe(card);
  7243. using_sdxc_controller = 0; //reset for sd_io_init()
  7244. if (err)
  7245. {
  7246. card_release_host(host);
  7247. kfree(card);
  7248. return NULL;
  7249. }
  7250. sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  7251. if (myidx == 0)
  7252. err = sdxc_mmc_staff_init(sd_mmc_info);
  7253. else
  7254. err = sd_mmc_staff_init(sd_mmc_info);
  7255. if (err)
  7256. {
  7257. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7258. card_release_host(host);
  7259. kfree(card);
  7260. return NULL;
  7261. }
  7262. sd_mmc_set_input(sd_mmc_info); //???
  7263. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7264. card_release_host(host);
  7265. */
  7266. return card;
  7267. }
  7268. static int sdxc_card_present(struct memory_card* card)
  7269. {
  7270. struct card_host *host = card->host;
  7271. __card_claim_host(host, card);
  7272. card->card_io_init(card); //sd_io_init()
  7273. card->card_detector(card); //sd_insert_detector()
  7274. using_sdxc_controller = 0; //reset for sd_io_init()
  7275. card_release_host(host);
  7276. if (card->card_status == CARD_INSERTED)
  7277. return 1;
  7278. else
  7279. return 0;
  7280. }
  7281. #define CHCEK_CONTINUE() \
  7282. { \
  7283. if (cursteps >= steps) \
  7284. goto error; \
  7285. printk("step %d\n", ++cursteps); \
  7286. }
  7287. static int sdxc_identify_verbose(SD_MMC_Card_Info_t *sd_mmc_info, int steps)
  7288. {
  7289. int error = 0;
  7290. int cursteps = 0;
  7291. sdio_close_host_interrupt(SDIO_IF_INT);
  7292. #ifdef SD_MMC_DEBUG
  7293. Debug_Printf("\nSDXC initialization started......\n");
  7294. #endif
  7295. sd_mmc_probe(sdxc_card);
  7296. sd_mmc_info = sdxc_card->card_info;
  7297. CHCEK_CONTINUE(); ////1
  7298. sdxc_mmc_staff_init(sd_mmc_info);
  7299. CHCEK_CONTINUE(); ////2
  7300. sd_mmc_set_input(sd_mmc_info);
  7301. error = sd_hw_reset(sd_mmc_info);
  7302. if(error)
  7303. {
  7304. #ifdef SD_MMC_DEBUG
  7305. Debug_Printf("#%s error occured in sd_hw_reset()\n", sd_error_to_string(error));
  7306. #endif
  7307. goto error;
  7308. }
  7309. sd_delay_ms(200);
  7310. CHCEK_CONTINUE(); ////3
  7311. error = sd_voltage_validation(sd_mmc_info);
  7312. if(error)
  7313. {
  7314. #ifdef SD_MMC_DEBUG
  7315. Debug_Printf("#%s error occured in sd_voltage_validation()\n", sd_error_to_string(error));
  7316. #endif
  7317. goto error;
  7318. }
  7319. CHCEK_CONTINUE(); ////4
  7320. error = sd_identify_process(sd_mmc_info);
  7321. if(error)
  7322. {
  7323. #ifdef SD_MMC_DEBUG
  7324. Debug_Printf("#%s error occured in sd_identify_process()\n", sd_error_to_string(error));
  7325. #endif
  7326. goto error;
  7327. }
  7328. #ifdef SD_MMC_HW_CONTROL
  7329. if(SD_WORK_MODE == CARD_HW_MODE)
  7330. {
  7331. if(!sd_mmc_info->disable_high_speed)
  7332. {
  7333. CHCEK_CONTINUE(); ////5
  7334. error = sd_mmc_switch_function(sd_mmc_info);
  7335. if(error)
  7336. {
  7337. #ifdef SD_MMC_DEBUG
  7338. Debug_Printf("#%s error occured in sd_switch_funtion()\n", sd_error_to_string(error));
  7339. #endif
  7340. //return error;
  7341. }
  7342. }
  7343. }
  7344. #endif
  7345. if(sd_mmc_info->card_type == CARD_TYPE_SDIO)
  7346. {
  7347. error = sd_check_sdio_card_type(sd_mmc_info);
  7348. if(error)
  7349. {
  7350. #ifdef SD_MMC_DEBUG
  7351. Debug_Printf("#%s error occured in sd_check_sdio_card_type()\n", sd_error_to_string(error));
  7352. #endif
  7353. goto error;
  7354. }
  7355. }
  7356. #ifdef SD_MMC_DEBUG
  7357. {
  7358. char *card_types[] = {
  7359. "Unknown",
  7360. "SD",
  7361. "SDHC",
  7362. "MMC",
  7363. "EMMC",
  7364. "SDIO"
  7365. };
  7366. char *card_str = card_types[sd_mmc_info->card_type];
  7367. char *bus_str = sd_mmc_info->bus_width == SD_BUS_WIDE ? "Wide Bus" : "Single Bus";
  7368. char *speed_str = sd_mmc_info->speed_class == HIGH_SPEED ? "High Speed" : "Normal Speed";
  7369. Debug_Printf("sd_mmc_init() is completed successfully!\n");
  7370. Debug_Printf("This %s card is working in %s and %s mode!\n\n", card_str, bus_str, speed_str);
  7371. }
  7372. #endif
  7373. CHCEK_CONTINUE(); ////6
  7374. sd_mmc_info->inited_flag = 1;
  7375. sd_mmc_info->init_retry = 0;
  7376. sd_mmc_info->sdxc_save_hw_io_flag = 1;
  7377. sd_mmc_info->sdxc_save_hw_io_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7378. sd_mmc_info->sdxc_save_hw_io_clk = READ_CBUS_REG(SD_REG4_CLKC);
  7379. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7380. return SD_MMC_NO_ERROR;
  7381. error:
  7382. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7383. return error;
  7384. }
  7385. static int sdxc_card_identify(struct memory_card* card, int steps)
  7386. {
  7387. int ret;
  7388. SD_MMC_Card_Info_t *sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  7389. struct card_host *host = card->host;
  7390. __card_claim_host(host, card);
  7391. if (myidx == 0)
  7392. {
  7393. using_sdxc_controller = 1;
  7394. ret = sdxc_identify_verbose(sd_mmc_info, steps);
  7395. using_sdxc_controller = 0;
  7396. }
  7397. else
  7398. {
  7399. sd_mmc_probe(sdxc_card);
  7400. sd_mmc_info = sdxc_card->card_info;
  7401. ret = sd_mmc_init(sd_mmc_info);
  7402. }
  7403. card_release_host(host);
  7404. return ret;
  7405. }
  7406. //for cmd "7"
  7407. static int sdxc_card_cmd(struct memory_card* card, unsigned int cmd)
  7408. {
  7409. int ret;
  7410. unsigned char response[MAX_RESPONSE_BYTES];
  7411. SD_MMC_Card_Info_t *sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  7412. struct card_host *host = card->host;
  7413. __card_claim_host(host, card);
  7414. sd_sdio_enable(sd_mmc_info->io_pad_type);
  7415. if (myidx == 0)
  7416. using_sdxc_controller = 1;
  7417. switch (cmd)
  7418. {
  7419. case 0 : //SD_MMC_GO_IDLE_STATE
  7420. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_GO_IDLE_STATE, 0, RESPONSE_NONE, 0, 0, 0, 1);
  7421. break;
  7422. //begin voltage validation
  7423. case 8: //SD_SEND_IF_COND
  7424. ret = sd_send_cmd_hw(sd_mmc_info, SD_SEND_IF_COND, 0x000001aa, RESPONSE_R7, response, 0, 0, 0);
  7425. break;
  7426. case 55: //SD_APP_CMD
  7427. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response, 0, 0, 0);
  7428. break;
  7429. case 41: //SD_APP_OP_COND //acmd
  7430. {
  7431. SD_Response_R3_t * r3;
  7432. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response, 0, 0, 0);
  7433. if (ret)
  7434. break;
  7435. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_OP_COND, 0x40200000, RESPONSE_R3, response, 0, 0, 0); //maybe check for ready
  7436. r3 = (SD_Response_R3_t *)response;
  7437. if(ret == SD_MMC_NO_ERROR && r3->ocr.Card_Busy)
  7438. {
  7439. printk("cmd41 : card ok\n");
  7440. }
  7441. else
  7442. {
  7443. printk("cmd41 : card still busy\n");
  7444. }
  7445. break;
  7446. }
  7447. case 42: //SD_APP_OP_COND : loop until ready //acmd
  7448. {
  7449. int loop = 0;
  7450. do
  7451. {
  7452. SD_Response_R3_t * r3;
  7453. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, 0, RESPONSE_R1, response, 0, 0, 0);
  7454. if (ret)
  7455. {
  7456. sd_delay_ms(10);
  7457. loop++;
  7458. continue;
  7459. }
  7460. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_OP_COND, 0x40200000, RESPONSE_R3, response, 0, 0, 0);
  7461. r3 = (SD_Response_R3_t *)response;
  7462. if(ret == SD_MMC_NO_ERROR && r3->ocr.Card_Busy)
  7463. {
  7464. printk("cmd41 : card ok -- loop%d\n", loop);
  7465. break;
  7466. }
  7467. else
  7468. {
  7469. printk("cmd 41 : loop%d with %s\n", loop, sd_error_to_string(ret));
  7470. }
  7471. sd_delay_ms(10);
  7472. loop++;
  7473. } while (loop < 10);
  7474. break;
  7475. }
  7476. case 43: //MMC_SEND_OP_COND : loop until ready //acmd
  7477. {
  7478. int loop = 0;
  7479. do
  7480. {
  7481. SD_Response_R3_t * r3;
  7482. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SEND_OP_COND, 0x40FF8000, RESPONSE_R3, response, 0, 0, 0); // 0x00200000: 3.3v~3.4v
  7483. r3 = (SD_Response_R3_t *)response;
  7484. if(ret == SD_MMC_NO_ERROR && r3->ocr.Card_Busy)
  7485. {
  7486. printk("cmd43 : card ok -- loop%d\n", loop);
  7487. if(!r3->ocr.Card_Capacity_Status)
  7488. sd_mmc_info->card_type = CARD_TYPE_MMC;
  7489. else
  7490. sd_mmc_info->card_type = CARD_TYPE_EMMC;
  7491. break;
  7492. }
  7493. else
  7494. {
  7495. printk("cmd 43 : loop%d with %s\n", loop, sd_error_to_string(ret));
  7496. }
  7497. sd_delay_ms(10);
  7498. loop++;
  7499. } while (loop < 10);
  7500. break;
  7501. }
  7502. //begin identify
  7503. case 2: //SD_MMC_ALL_SEND_CID
  7504. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID, response, 0, 0, 1);
  7505. break;
  7506. case 3: //SD_MMC_SEND_RELATIVE_ADDR
  7507. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_RELATIVE_ADDR, 0, RESPONSE_R6, response, 0, 0, 0); //maybe save the RCA value
  7508. sd_mmc_info->card_rca = ((SD_Response_R6_t *)response)->rca_high << 8 | ((SD_Response_R6_t *)response)->rca_low;
  7509. printk("Got RCA=0x%x (%d)\n", sd_mmc_info->card_rca, sd_mmc_info->card_rca);
  7510. break;
  7511. case 10: //SD_MMC_SEND_CID
  7512. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_CID, sd_mmc_info->card_rca<<16, RESPONSE_R2_CID, response, NULL, 0, 1);
  7513. if (ret == SD_MMC_NO_ERROR)
  7514. {
  7515. my_disp_cid((MyCID*)&(((SD_Response_R2_CID_t *)response)->cid));
  7516. }
  7517. break;
  7518. case 9: //SD_MMC_SEND_CSD
  7519. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SEND_CSD, sd_mmc_info->card_rca<<16, RESPONSE_R2_CSD, response, 0, 0, 1); //maybe parse the blk num & len
  7520. sd_mmc_info->blk_len = 512;
  7521. if (ret == SD_MMC_NO_ERROR)
  7522. {
  7523. my_disp_csdv2(&(((SDHC_Response_R2_CSD_t *)response)->csd));
  7524. }
  7525. break;
  7526. case 7: //SD_MMC_SELECT_DESELECT_CARD
  7527. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_SELECT_DESELECT_CARD, sd_mmc_info->card_rca<<16, RESPONSE_R1B, response, 0, 0, 1);
  7528. break;
  7529. case 51: //SD_SEND_SCR //acmd
  7530. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  7531. if (ret)
  7532. break;
  7533. ret = sd_send_cmd_hw(sd_mmc_info, SD_SEND_SCR, 0, RESPONSE_R1, response, sd_mmc_info->sd_mmc_buf, sizeof(SD_REG_SCR_t), 1); //may be parse spec_version & bus bit modes
  7534. my_disp_scr((MySCR*)sd_mmc_info->sd_mmc_buf);
  7535. break;
  7536. /*
  7537. case 6: //SD_SET_BUS_WIDTHS : 4 bits //acmd
  7538. sd_mmc_info->bus_width = SD_BUS_WIDE;
  7539. if (using_sdxc_controller)
  7540. {
  7541. unsigned long sdxc_ctrl = 0;
  7542. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7543. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7544. sdxc_ctrl_reg->dat_width = 1;
  7545. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7546. }
  7547. else
  7548. {
  7549. unsigned long sdio_config = 0;
  7550. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7551. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7552. config_reg->bus_width = 1;
  7553. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7554. }
  7555. sd_delay_ms(100);
  7556. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  7557. if (ret)
  7558. {
  7559. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7560. if (using_sdxc_controller)
  7561. {
  7562. unsigned long sdxc_ctrl = 0;
  7563. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7564. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7565. sdxc_ctrl_reg->dat_width = 0;
  7566. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7567. }
  7568. else
  7569. {
  7570. unsigned long sdio_config = 0;
  7571. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7572. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7573. config_reg->bus_width = 0;
  7574. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7575. }
  7576. break;
  7577. }
  7578. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x02, RESPONSE_R1, response, 0, 0, 1);
  7579. if (ret == SD_MMC_NO_ERROR)
  7580. {
  7581. }
  7582. else
  7583. {
  7584. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7585. if (using_sdxc_controller)
  7586. {
  7587. unsigned long sdxc_ctrl = 0;
  7588. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7589. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7590. sdxc_ctrl_reg->dat_width = 0;
  7591. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7592. }
  7593. else
  7594. {
  7595. unsigned long sdio_config = 0;
  7596. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7597. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7598. config_reg->bus_width = 0;
  7599. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7600. }
  7601. }
  7602. break;
  7603. case 46: //SD_SET_BUS_WIDTHS : 1 bit
  7604. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7605. if (using_sdxc_controller)
  7606. {
  7607. unsigned long sdxc_ctrl = 0;
  7608. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7609. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7610. sdxc_ctrl_reg->dat_width = 0;
  7611. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7612. }
  7613. else
  7614. {
  7615. unsigned long sdio_config = 0;
  7616. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7617. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7618. config_reg->bus_width = 0;
  7619. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7620. }
  7621. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  7622. if (ret)
  7623. break;
  7624. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x00, RESPONSE_R1, response, 0, 0, 1);
  7625. if (ret == SD_MMC_NO_ERROR)
  7626. {
  7627. }
  7628. else
  7629. {
  7630. }
  7631. break;
  7632. */
  7633. case 6: //SD_SET_BUS_WIDTHS : 4 bits //acmd
  7634. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  7635. if (ret)
  7636. break;
  7637. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x02, RESPONSE_R1, response, 0, 0, 1);
  7638. if (ret == SD_MMC_NO_ERROR)
  7639. {
  7640. sd_mmc_info->bus_width = SD_BUS_WIDE;
  7641. if (using_sdxc_controller)
  7642. {
  7643. unsigned long sdxc_ctrl = 0;
  7644. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7645. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7646. sdxc_ctrl_reg->dat_width = 1;
  7647. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7648. }
  7649. else
  7650. {
  7651. unsigned long sdio_config = 0;
  7652. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7653. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7654. config_reg->bus_width = 1;
  7655. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7656. }
  7657. }
  7658. break;
  7659. case 46: //SD_SET_BUS_WIDTHS : 1 bit //acmd
  7660. ret = sd_send_cmd_hw(sd_mmc_info, SD_APP_CMD, sd_mmc_info->card_rca<<16, RESPONSE_R1, response, 0, 0, 1);
  7661. if (ret)
  7662. break;
  7663. ret = sd_send_cmd_hw(sd_mmc_info, SD_SET_BUS_WIDTHS, 0x00, RESPONSE_R1, response, 0, 0, 1);
  7664. if (ret == SD_MMC_NO_ERROR)
  7665. {
  7666. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7667. if (using_sdxc_controller)
  7668. {
  7669. unsigned long sdxc_ctrl = 0;
  7670. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7671. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7672. sdxc_ctrl_reg->dat_width = 0;
  7673. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7674. }
  7675. else
  7676. {
  7677. unsigned long sdio_config = 0;
  7678. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7679. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7680. config_reg->bus_width = 0;
  7681. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7682. }
  7683. }
  7684. break;
  7685. case 56 : //SD_SWITCH_FUNCTION //HS
  7686. {
  7687. unsigned char response[MAX_RESPONSE_BYTES];
  7688. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  7689. SD_Switch_Function_Status_t *switch_funtion_status;
  7690. unsigned long sdio_config = 0;
  7691. SDIO_Config_Reg_t *config_reg = NULL;
  7692. memset(status_data_buf, 0, 64);
  7693. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  7694. if(ret)
  7695. break;
  7696. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  7697. if(switch_funtion_status->Max_Current_Consumption == 0)
  7698. {
  7699. ret = SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  7700. break;
  7701. }
  7702. my_disp_switch_status(switch_funtion_status); //check disp
  7703. memset(status_data_buf, 0, 64);
  7704. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x80FFFF01, RESPONSE_R1, response, status_data_buf, 64, 1);
  7705. if(ret)
  7706. break;
  7707. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  7708. if(switch_funtion_status->Max_Current_Consumption == 0 || switch_funtion_status->Function_Group_Status1 == 0xF)
  7709. {
  7710. ret = SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  7711. break;
  7712. }
  7713. my_disp_switch_status(switch_funtion_status); //switch disp
  7714. if (using_sdxc_controller)
  7715. {
  7716. unsigned long sdxc_clk = 0;
  7717. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  7718. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  7719. sdxc_clk_reg->clk_ctl_en = 0;
  7720. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  7721. sdxc_clk_reg->clk_div = CLK_DIV_50M; //sdxx
  7722. sdxc_clk_reg->clk_en = 1;
  7723. sdxc_clk_reg->clk_ctl_en = 1;
  7724. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  7725. }
  7726. else
  7727. {
  7728. sdio_config = 0;
  7729. config_reg = (void *)&sdio_config;
  7730. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7731. config_reg->cmd_clk_divide = 1;//aml_system_clk / (2*SD_MMC_TRANSFER_HIGHSPEED_CLK) -1;
  7732. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7733. }
  7734. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_HIGHSPEED_CLK;
  7735. sd_mmc_info->speed_class = HIGH_SPEED;
  7736. break;
  7737. }
  7738. case 66 : //SD_SWITCH_FUNCTION //DS
  7739. {
  7740. unsigned char response[MAX_RESPONSE_BYTES];
  7741. unsigned char *status_data_buf = sd_mmc_info->sd_mmc_buf;
  7742. SD_Switch_Function_Status_t *switch_funtion_status;
  7743. unsigned long sdio_config = 0;
  7744. SDIO_Config_Reg_t *config_reg = NULL;
  7745. memset(status_data_buf, 0, 64);
  7746. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x00FFFF00, RESPONSE_R1, response, status_data_buf, 64, 1);
  7747. if(ret)
  7748. break;
  7749. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  7750. if(switch_funtion_status->Max_Current_Consumption == 0)
  7751. {
  7752. ret = SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  7753. break;
  7754. }
  7755. my_disp_switch_status(switch_funtion_status); //check disp
  7756. memset(status_data_buf, 0, 64);
  7757. ret = sd_send_cmd_hw(sd_mmc_info, SD_SWITCH_FUNCTION, 0x80FFFF00, RESPONSE_R1, response, status_data_buf, 64, 1);
  7758. if(ret)
  7759. break;
  7760. switch_funtion_status = (SD_Switch_Function_Status_t *)status_data_buf;
  7761. if(switch_funtion_status->Max_Current_Consumption == 0 || switch_funtion_status->Function_Group_Status1 == 0xF)
  7762. {
  7763. ret = SD_ERROR_SWITCH_FUNCTION_COMUNICATION;
  7764. break;
  7765. }
  7766. my_disp_switch_status(switch_funtion_status); //switch disp
  7767. if (using_sdxc_controller)
  7768. {
  7769. unsigned long sdxc_clk = 0;
  7770. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  7771. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  7772. sdxc_clk_reg->clk_ctl_en = 0;
  7773. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  7774. sdxc_clk_reg->clk_div = CLK_DIV_25M; //sdxx
  7775. sdxc_clk_reg->clk_en = 1;
  7776. sdxc_clk_reg->clk_ctl_en = 1;
  7777. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  7778. }
  7779. else
  7780. {
  7781. sdio_config = 0;
  7782. config_reg = (void *)&sdio_config;
  7783. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7784. config_reg->cmd_clk_divide = 4;//aml_system_clk / (2*SD_MMC_TRANSFER_HIGHSPEED_CLK) -1;
  7785. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7786. }
  7787. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_HIGHSPEED_CLK;
  7788. sd_mmc_info->speed_class = NORMAL_SPEED;
  7789. break;
  7790. }
  7791. default :
  7792. printk("unknowd cmd %d\n", cmd);
  7793. ret = SD_MMC_ERROR_GENERAL;
  7794. break;
  7795. }
  7796. using_sdxc_controller = 0;
  7797. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7798. card_release_host(host);
  7799. return ret;
  7800. }
  7801. static int wr_cnt = 10;
  7802. //for cmd "9"
  7803. static int sdxc_card_rw(struct memory_card* card, unsigned int cmd, unsigned int lba, unsigned int cnt)
  7804. {
  7805. int ret = 0;
  7806. unsigned char response[MAX_RESPONSE_BYTES];
  7807. unsigned char* data_buf;
  7808. SD_MMC_Card_Info_t *sd_mmc_info = (SD_MMC_Card_Info_t *)card->card_info;
  7809. struct card_host *host = card->host;
  7810. static unsigned char start_num = 0x55;
  7811. __card_claim_host(host, card);
  7812. sd_sdio_enable(sd_mmc_info->io_pad_type);
  7813. if (myidx == 0)
  7814. using_sdxc_controller = 1;
  7815. data_buf = sd_mmc_info->sd_mmc_buf;
  7816. switch (cmd)
  7817. {
  7818. case 20 :
  7819. start_num = lba;
  7820. printk("new start num = 0x%x -- %u\n", start_num, start_num);
  7821. break;
  7822. case 21 :
  7823. sdxc_delay = lba;
  7824. printk("new rw delay = %dus\n", sdxc_delay);
  7825. break;
  7826. case 22 :
  7827. sd_mmc_info->max_blk_count = lba;
  7828. printk("new sd_mmc_info->max_blk_count = %d\n", sd_mmc_info->max_blk_count);
  7829. break;
  7830. case 23 :
  7831. my_check = lba;
  7832. printk("my_check=%d\n", my_check);
  7833. break;
  7834. case 3 :
  7835. printk("send stop\n");
  7836. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  7837. break;
  7838. case 31 :
  7839. {
  7840. printk("sd_mmc_prepare_power\n");
  7841. sd_mmc_prepare_power(sd_mmc_info);
  7842. msleep(5);
  7843. break;
  7844. }
  7845. case 32 :
  7846. {
  7847. printk("sd_mmc_set_input\n");
  7848. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7849. sd_mmc_set_input(sd_mmc_info);
  7850. msleep(5);
  7851. break;
  7852. }
  7853. case 33 :
  7854. {
  7855. printk("test STAT3\n");
  7856. sd_gpio_enable(sd_mmc_info->io_pad_type);
  7857. sd_set_cmd_output();
  7858. sd_set_cmd_value(lba);
  7859. sd_set_clk_output();
  7860. sd_set_clk_low();
  7861. sd_set_dat0_3_output();
  7862. sd_set_dat0_3_value(cnt);
  7863. msleep(5);
  7864. break;
  7865. }
  7866. /*
  7867. case 31 :
  7868. {
  7869. printk("\n");
  7870. break;
  7871. }
  7872. */
  7873. case 4 :
  7874. {
  7875. unsigned int pullup;
  7876. pullup = READ_CBUS_REG(PAD_PULL_UP_REG3);
  7877. printk("PAD_PULL_UP_REG3=0x%8x\n", pullup);
  7878. break;
  7879. }
  7880. case 5 :
  7881. {
  7882. unsigned int pullup;
  7883. pullup = READ_CBUS_REG(PAD_PULL_UP_REG3);
  7884. pullup |= 0xFF;
  7885. WRITE_CBUS_REG(PAD_PULL_UP_REG3, pullup);
  7886. printk("set PAD_PULL_UP_REG3 pullup\n");
  7887. break;
  7888. }
  7889. case 6 :
  7890. {
  7891. unsigned int pullup;
  7892. pullup = READ_CBUS_REG(PAD_PULL_UP_REG3);
  7893. pullup &= ~0xFF;
  7894. WRITE_CBUS_REG(PAD_PULL_UP_REG3, pullup);
  7895. printk("unset PAD_PULL_UP_REG3 pullup\n");
  7896. break;
  7897. }
  7898. case 10 :
  7899. printk("switch to 1 bits for emmc\n");
  7900. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b70000, RESPONSE_R1, response, 0, 0, 1);
  7901. if(ret)
  7902. {
  7903. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7904. }
  7905. else
  7906. {
  7907. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7908. if (using_sdxc_controller)
  7909. {
  7910. unsigned long sdxc_ctrl = 0;
  7911. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7912. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7913. sdxc_ctrl_reg->dat_width = 0;
  7914. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7915. }
  7916. else
  7917. {
  7918. unsigned long sdio_config = 0;
  7919. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7920. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7921. config_reg->bus_width = 0;
  7922. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7923. }
  7924. }
  7925. break;
  7926. case 11 :
  7927. printk("switch to 4 bits for emmc\n");
  7928. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b70100, RESPONSE_R1, response, 0, 0, 1);
  7929. if(ret)
  7930. {
  7931. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7932. }
  7933. else
  7934. {
  7935. sd_mmc_info->bus_width = SD_BUS_WIDE;
  7936. if (using_sdxc_controller)
  7937. {
  7938. unsigned long sdxc_ctrl = 0;
  7939. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7940. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7941. sdxc_ctrl_reg->dat_width = 1;
  7942. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7943. }
  7944. else
  7945. {
  7946. unsigned long sdio_config = 0;
  7947. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7948. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7949. config_reg->bus_width = 1;
  7950. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7951. }
  7952. }
  7953. break;
  7954. case 12 :
  7955. printk("switch to 8 bits for emmc\n");
  7956. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b70200, RESPONSE_R1, response, 0, 0, 1);
  7957. if(ret)
  7958. {
  7959. sd_mmc_info->bus_width = SD_BUS_SINGLE;
  7960. }
  7961. else
  7962. {
  7963. sd_mmc_info->bus_width = SD_BUS_WIDE;
  7964. if (using_sdxc_controller)
  7965. {
  7966. unsigned long sdxc_ctrl = 0;
  7967. SDXC_Ctrl_Reg_t *sdxc_ctrl_reg = (void *)&sdxc_ctrl;
  7968. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7969. sdxc_ctrl_reg->dat_width = 2;
  7970. printk("before set : %x\n", (unsigned int)sdxc_ctrl);
  7971. WRITE_CBUS_REG(SD_REG2_CNTL, sdxc_ctrl);
  7972. sdxc_ctrl = READ_CBUS_REG(SD_REG2_CNTL);
  7973. printk("after set : %x\n", (unsigned int)sdxc_ctrl);
  7974. }
  7975. else
  7976. {
  7977. unsigned long sdio_config = 0;
  7978. SDIO_Config_Reg_t *config_reg = (void *)&sdio_config;
  7979. sdio_config = READ_CBUS_REG(SDIO_CONFIG);
  7980. config_reg->bus_width = 1;
  7981. WRITE_CBUS_REG(SDIO_CONFIG, sdio_config);
  7982. }
  7983. }
  7984. break;
  7985. case 16 :
  7986. printk("switch to identify speed for emmc\n");
  7987. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90000, RESPONSE_R1, response, 0, 0, 1);
  7988. if(ret)
  7989. break;
  7990. if (using_sdxc_controller)
  7991. {
  7992. unsigned long sdxc_clk = 0;
  7993. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  7994. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  7995. sdxc_clk_reg->clk_ctl_en = 0;
  7996. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  7997. sdxc_clk_reg->clk_div = CLK_DIV_IDENTIFY; //sdxx
  7998. sdxc_clk_reg->clk_en = 1;
  7999. sdxc_clk_reg->clk_ctl_en = 1;
  8000. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8001. }
  8002. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_IDENTIFY_CLK;
  8003. sd_mmc_info->speed_class = NORMAL_SPEED;
  8004. break;
  8005. case 13 :
  8006. printk("switch to default speed for emmc : %d=%dK\n", lba, 500000/(lba+1));
  8007. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90000, RESPONSE_R1, response, 0, 0, 1);
  8008. if(ret)
  8009. break;
  8010. if (using_sdxc_controller)
  8011. {
  8012. unsigned long sdxc_clk = 0;
  8013. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  8014. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  8015. sdxc_clk_reg->clk_ctl_en = 0;
  8016. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8017. sdxc_clk_reg->clk_div = lba; //sdxx
  8018. sdxc_clk_reg->rx_clk_phase_sel = cnt;
  8019. sdxc_clk_reg->clk_en = 1;
  8020. sdxc_clk_reg->clk_ctl_en = 1;
  8021. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8022. }
  8023. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_CLK;
  8024. sd_mmc_info->speed_class = NORMAL_SPEED;
  8025. break;
  8026. case 14 :
  8027. printk("switch to high speed for emmc : %d=%dK\n", lba, 500000/(lba+1));
  8028. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90100, RESPONSE_R1, response, 0, 0, 1);
  8029. if(ret)
  8030. break;
  8031. if (using_sdxc_controller)
  8032. {
  8033. unsigned long sdxc_clk = 0;
  8034. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  8035. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  8036. sdxc_clk_reg->clk_ctl_en = 0;
  8037. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8038. sdxc_clk_reg->clk_div = lba; //sdxx
  8039. sdxc_clk_reg->rx_clk_phase_sel = cnt;
  8040. sdxc_clk_reg->clk_en = 1;
  8041. sdxc_clk_reg->clk_ctl_en = 1;
  8042. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8043. }
  8044. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_HIGHSPEED_CLK;
  8045. sd_mmc_info->speed_class = HIGH_SPEED;
  8046. break;
  8047. /*
  8048. case 13 :
  8049. printk("switch to default speed for emmc\n");
  8050. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90000, RESPONSE_R1, response, 0, 0, 1);
  8051. if(ret)
  8052. break;
  8053. if (using_sdxc_controller)
  8054. {
  8055. unsigned long sdxc_clk = 0;
  8056. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  8057. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  8058. sdxc_clk_reg->clk_ctl_en = 0;
  8059. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8060. sdxc_clk_reg->clk_div = CLK_DIV_25M; //sdxx
  8061. sdxc_clk_reg->clk_en = 1;
  8062. sdxc_clk_reg->clk_ctl_en = 1;
  8063. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8064. }
  8065. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_CLK;
  8066. sd_mmc_info->speed_class = NORMAL_SPEED;
  8067. break;
  8068. case 14 :
  8069. printk("switch to high speed for emmc\n");
  8070. ret = sd_send_cmd_hw(sd_mmc_info, MMC_SWITCH_FUNTION, 0x03b90100, RESPONSE_R1, response, 0, 0, 1);
  8071. if(ret)
  8072. break;
  8073. if (using_sdxc_controller)
  8074. {
  8075. unsigned long sdxc_clk = 0;
  8076. SDXC_Clk_Reg_t *sdxc_clk_reg = (void *)&sdxc_clk;
  8077. sdxc_clk = READ_CBUS_REG(SD_REG4_CLKC);
  8078. sdxc_clk_reg->clk_ctl_en = 0;
  8079. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8080. sdxc_clk_reg->clk_div = CLK_DIV_HS_MMC; //sdxx
  8081. sdxc_clk_reg->clk_en = 1;
  8082. sdxc_clk_reg->clk_ctl_en = 1;
  8083. WRITE_CBUS_REG(SD_REG4_CLKC, sdxc_clk);
  8084. }
  8085. sd_mmc_info->sdio_clk_unit = 1000/SD_MMC_TRANSFER_HIGHSPEED_CLK;
  8086. sd_mmc_info->speed_class = HIGH_SPEED;
  8087. break;
  8088. */
  8089. case 15 :
  8090. printk("send csd_ext\n");
  8091. {
  8092. unsigned char *mmc_ext_csd_buf = sd_mmc_info->sd_mmc_buf;
  8093. MMC_REG_EXT_CSD_t *mmc_ext_csd_reg;
  8094. ret = sd_send_cmd_hw(sd_mmc_info,MMC_SEND_EXT_CSD, 0, RESPONSE_R1, response, mmc_ext_csd_buf, sizeof(MMC_REG_EXT_CSD_t), 1);
  8095. mmc_ext_csd_reg = (MMC_REG_EXT_CSD_t *)mmc_ext_csd_buf;
  8096. my_disp_csd_ext(mmc_ext_csd_reg);
  8097. }
  8098. break;
  8099. case 17 : //SD_MMC_READ_SINGLE_BLOCK
  8100. {
  8101. int i;
  8102. for( i = 0; i < 512; i++)
  8103. data_buf[i] = 0xdd;
  8104. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_READ_SINGLE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512, 1);
  8105. if (ret == SD_MMC_NO_ERROR)
  8106. {
  8107. printk("read data from lba 0x%x -- %u\n", lba, lba);
  8108. for (i = 0; i < 512; i++)
  8109. {
  8110. printk("%02x", data_buf[i]);
  8111. if ((i % 4) == 3)
  8112. printk(" ");
  8113. if ((i % 32) == 31)
  8114. printk("\n");
  8115. }
  8116. printk("end of lba 0x%x -- %u\n", lba, lba);
  8117. }
  8118. break;
  8119. }
  8120. case 18 : //SD_MMC_READ_MULTIPLE_BLOCK
  8121. {
  8122. int i;
  8123. for( i = 0; i < 512 * cnt; i++)
  8124. data_buf[i] = 0xee;
  8125. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_READ_MULTIPLE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512 * cnt, 1);
  8126. if (ret == SD_MMC_NO_ERROR)
  8127. {
  8128. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8129. printk("read %d sectors data from lba 0x%x -- %u\n", cnt, lba, lba);
  8130. for (i = 0; i < 512 * cnt; i++)
  8131. {
  8132. printk("%02x", data_buf[i]);
  8133. if ((i % 4) == 3)
  8134. printk(" ");
  8135. if ((i % 32) == 31)
  8136. printk("\n");
  8137. if ((i % 512) == 511)
  8138. printk("\n");
  8139. }
  8140. printk("end of lba 0x%x -- %u\n", lba, lba);
  8141. }
  8142. /*
  8143. ret = sd_read_multi_block_hw(sd_mmc_info, lba, cnt, data_buf);
  8144. if (ret == SD_MMC_NO_ERROR)
  8145. {
  8146. printk("read %d sectors data from lba 0x%x -- %u\n", cnt, lba, lba);
  8147. for (i = 0; i < 512 * cnt; i++)
  8148. {
  8149. printk("%02x", data_buf[i]);
  8150. if ((i % 4) == 3)
  8151. printk(" ");
  8152. if ((i % 32) == 31)
  8153. printk("\n");
  8154. if ((i % 512) == 511)
  8155. printk("\n");
  8156. }
  8157. printk("end of lba 0x%x -- %u\n", lba, lba);
  8158. }
  8159. */
  8160. break;
  8161. }
  8162. case 19 : //SD_MMC_READ_MULTIPLE_BLOCK
  8163. {
  8164. int i;
  8165. int j = 0;
  8166. memset(data_buf, 0xee, 512 * cnt);
  8167. printk("read %d sectors data from lba 0x%x -- %u\n", cnt, lba, lba);
  8168. while (j++ < wr_cnt) {
  8169. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_READ_MULTIPLE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512 * cnt, 1);
  8170. if (ret == SD_MMC_NO_ERROR) {
  8171. i = 10;
  8172. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8173. while (ret != SD_MMC_NO_ERROR && i--) {
  8174. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8175. }
  8176. if (i != 10)
  8177. printk("send stop retry %d times\n", 10 - i);
  8178. if (ret)
  8179. break;
  8180. }
  8181. }
  8182. if (ret == SD_MMC_NO_ERROR) {
  8183. for (i = 0; i < cnt; i++)
  8184. {
  8185. printk("%02x", data_buf[i * 512]);
  8186. if ((i % 4) == 3)
  8187. printk(" ");
  8188. if ((i % 32) == 31)
  8189. printk("\n");
  8190. if ((i % 512) == 511)
  8191. printk("\n");
  8192. }
  8193. printk("\nend of lba 0x%x -- %u\n", lba, lba);
  8194. }
  8195. /*
  8196. ret = sd_read_multi_block_hw(sd_mmc_info, lba, cnt, data_buf);
  8197. if (ret == SD_MMC_NO_ERROR)
  8198. {
  8199. printk("read %d sectors data from lba 0x%x -- %u\n", cnt, lba, lba);
  8200. for (i = 0; i < 512 * cnt; i++)
  8201. {
  8202. printk("%02x", data_buf[i]);
  8203. if ((i % 4) == 3)
  8204. printk(" ");
  8205. if ((i % 32) == 31)
  8206. printk("\n");
  8207. if ((i % 512) == 511)
  8208. printk("\n");
  8209. }
  8210. printk("end of lba 0x%x -- %u\n", lba, lba);
  8211. }
  8212. */
  8213. break;
  8214. }
  8215. case 24 : //SD_MMC_WRITE_BLOCK
  8216. {
  8217. int i;
  8218. for( i = 0; i < 512; i++)
  8219. data_buf[i] = i + start_num;
  8220. printk("write data 0x%x to lba 0x%x -- %u\n", start_num, lba, lba);
  8221. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_WRITE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512, 1);
  8222. break;
  8223. }
  8224. case 25 : //SD_MMC_WRITE_MULTIPLE_BLOCK
  8225. {
  8226. int i;
  8227. for (i = 0; i < cnt; i++) {
  8228. memset(data_buf + i * 512, start_num + i, 512);
  8229. }
  8230. printk("write %d sectors data 0x%x to lba 0x%x -- %u\n", cnt, start_num, lba, lba);
  8231. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_WRITE_MULTIPLE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512 * cnt, 1);
  8232. i = 10;
  8233. if (ret == SD_MMC_NO_ERROR) {
  8234. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8235. while (ret != SD_MMC_NO_ERROR && i--) {
  8236. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8237. }
  8238. printk("send stop retry %d times\n", 10 - i);
  8239. }
  8240. break;
  8241. }
  8242. case 26 : //SD_MMC_WRITE_MULTIPLE_BLOCK
  8243. {
  8244. int i;
  8245. int j = 0;
  8246. for (i = 0; i < cnt; i++) {
  8247. memset(data_buf + i * 512, start_num + i, 512);
  8248. }
  8249. printk("write %d sectors data 0x%x to lba 0x%x -- %u\n", cnt, start_num, lba, lba);
  8250. while (j++ < wr_cnt) {
  8251. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_WRITE_MULTIPLE_BLOCK, lba, RESPONSE_R1, response, data_buf, 512 * cnt, 1);
  8252. i = 10;
  8253. if (ret == SD_MMC_NO_ERROR) {
  8254. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8255. while (ret != SD_MMC_NO_ERROR && i--) {
  8256. ret = sd_send_cmd_hw(sd_mmc_info, SD_MMC_STOP_TRANSMISSION, 0, RESPONSE_R1B, response, NULL, 0, 0);
  8257. }
  8258. if (i != 10)
  8259. printk("send stop retry %d times\n", 10 - i);
  8260. }
  8261. if (ret)
  8262. break;
  8263. }
  8264. break;
  8265. }
  8266. case 27 :
  8267. printk("change wr_cnt from %d to %d\n", wr_cnt, lba);
  8268. wr_cnt = lba;
  8269. break;
  8270. default :
  8271. printk("unknown cmd %d\n", cmd);
  8272. ret = SD_ERROR_Reserved1;
  8273. break;
  8274. }
  8275. using_sdxc_controller = 0;
  8276. sd_gpio_enable(sd_mmc_info->io_pad_type);
  8277. card_release_host(host);
  8278. return ret;
  8279. }
  8280. static void my_disp_sdhc_regs(void)
  8281. {
  8282. unsigned int value;
  8283. const char *ptr;
  8284. value = READ_CBUS_REG(SD_REG0_ARGU);
  8285. printk("\nSD_REG0_ARGU=0x%08x -- %u\n", value, value);
  8286. value = READ_CBUS_REG(SD_REG1_SEND);
  8287. printk("SD_REG1_SEND=0x%08x -- %u\n", value, value);
  8288. {
  8289. SDXC_Send_Reg_t *send_reg = (SDXC_Send_Reg_t *)&value;
  8290. printk("\t total_pack--%d \n", send_reg->total_pack);
  8291. printk("\t data_stop--%d \n", send_reg->data_stop);
  8292. printk("\t data_direction--%d(%s) \n", send_reg->data_direction, send_reg->data_direction ? "tx" : "rx");
  8293. printk("\t response_no_crc--%d \n", send_reg->response_no_crc);
  8294. printk("\t response_length--%d \n", send_reg->response_length);
  8295. printk("\t command_has_data--%d \n", send_reg->command_has_data);
  8296. printk("\t command_has_resp--%d \n", send_reg->command_has_resp);
  8297. printk("\t command_index--0x%02x \n", send_reg->command_index);
  8298. }
  8299. value = READ_CBUS_REG(SD_REG2_CNTL);
  8300. printk("SD_REG2_CNTL=0x%08x -- %u\n", value, value);
  8301. {
  8302. SDXC_Ctrl_Reg_t *ctrl_reg = (SDXC_Ctrl_Reg_t *)&value;
  8303. printk("\t reserved2--%d \n", ctrl_reg->reserved2);
  8304. printk("\t endian--%d \n", ctrl_reg->endian);
  8305. printk("\t rc_period--%d \n", ctrl_reg->rc_period);
  8306. printk("\t rx_timeout--%d \n", ctrl_reg->rx_timeout);
  8307. printk("\t pack_len--%d \n", ctrl_reg->pack_len);
  8308. printk("\t reserved1--%d \n", ctrl_reg->reserved1);
  8309. printk("\t ddr_mode--%d \n", ctrl_reg->ddr_mode);
  8310. if (ctrl_reg->dat_width == 0)
  8311. ptr = "1bit";
  8312. else if (ctrl_reg->dat_width == 1)
  8313. ptr = "4bits";
  8314. else if (ctrl_reg->dat_width == 2)
  8315. ptr = "8bits";
  8316. else
  8317. ptr = "reserved";
  8318. printk("\t dat_width--%d(%s) \n", ctrl_reg->dat_width, ptr);
  8319. }
  8320. value = READ_CBUS_REG(SD_REG3_STAT);
  8321. printk("SD_REG3_STAT=0x%08x -- %u\n", value, value);
  8322. {
  8323. SDXC_Status_Reg_t *status_reg = (SDXC_Status_Reg_t *)&value;
  8324. printk("\t reserved3--%d \n", status_reg->reserved3);
  8325. printk("\t dat_7_4--%d \n", status_reg->dat_7_4);
  8326. printk("\t tx_count--%d \n", status_reg->tx_count);
  8327. printk("\t rx_count--%d \n", status_reg->rx_count);
  8328. printk("\t reserved2--%d \n", status_reg->reserved2);
  8329. printk("\t reserved1--%d \n", status_reg->reserved1);
  8330. printk("\t cmd_state--%d \n", status_reg->cmd_state);
  8331. printk("\t dat_3_0--%d \n", status_reg->dat_3_0);
  8332. printk("\t busy--%d \n", status_reg->busy);
  8333. }
  8334. value = READ_CBUS_REG(SD_REG4_CLKC);
  8335. printk("SD_REG4_CLKC=0x%08x -- %u\n", value, value);
  8336. {
  8337. SDXC_Clk_Reg_t *clk_reg = (SDXC_Clk_Reg_t *)&value;
  8338. printk("\t reserved1--%d \n", clk_reg->reserved1);
  8339. printk("\t clk_jic_control--%d \n", clk_reg->clk_jic_control);
  8340. printk("\t clk_ctl_en--%d \n", clk_reg->clk_ctl_en);
  8341. printk("\t rx_clk_feedback_en--%d \n", clk_reg->rx_clk_feedback_en);
  8342. printk("\t rx_clk_phase_sel--%d \n", clk_reg->rx_clk_phase_sel);
  8343. printk("\t clk_en--%d \n", clk_reg->clk_en);
  8344. switch (clk_reg->clk_in_sel) {
  8345. case 0:
  8346. ptr = "osc";
  8347. break;
  8348. case 1:
  8349. ptr = "sys pll";
  8350. break;
  8351. case 2:
  8352. ptr = "misc pll";
  8353. break;
  8354. case 3:
  8355. ptr = "ddr pll";
  8356. break;
  8357. case 4:
  8358. ptr = "aud pll";
  8359. break;
  8360. case 5:
  8361. ptr = "vid pll";
  8362. break;
  8363. case 6:
  8364. ptr = "vid2 pll";
  8365. break;
  8366. case 7:
  8367. ptr = "sys pll/2";
  8368. break;
  8369. default :
  8370. ptr = "reserved";
  8371. break;
  8372. }
  8373. printk("\t clk_in_sel--%d(%s) \n", clk_reg->clk_in_sel, ptr);
  8374. printk("\t clk_div--%d \n", clk_reg->clk_div);
  8375. }
  8376. value = READ_CBUS_REG(SD_REG5_ADDR);
  8377. printk("SD_REG5_ADDR=0x%08x -- %u\n", value, value);
  8378. value = READ_CBUS_REG(SD_REG6_PDMA);
  8379. printk("SD_REG6_PDMA=0x%08x -- %u\n", value, value);
  8380. {
  8381. SDXC_PDMA_Reg_t *pdma_reg = (SDXC_PDMA_Reg_t *)&value;
  8382. printk("\t reserved1--%d \n", pdma_reg->reserved1);
  8383. printk("\t rx_manual_flush--%d \n", pdma_reg->rx_manual_flush);
  8384. printk("\t tx_threshold--%d \n", pdma_reg->tx_threshold);
  8385. printk("\t rx_threshold--%d \n", pdma_reg->rx_threshold);
  8386. printk("\t rd_burst--%d \n", pdma_reg->rd_burst);
  8387. printk("\t wr_burst--%d \n", pdma_reg->wr_burst);
  8388. printk("\t dma_urgent--%d \n", pdma_reg->dma_urgent);
  8389. printk("\t pio_rd_resp--%d \n", pdma_reg->pio_rd_resp);
  8390. printk("\t dma_mode--%d \n", pdma_reg->dma_mode);
  8391. }
  8392. value = READ_CBUS_REG(SD_REG7_MISC);
  8393. printk("SD_REG7_MISC=0x%08x -- %u\n", value, value);
  8394. {
  8395. SDXC_Misc_Reg_t *misc_reg = (SDXC_Misc_Reg_t *)&value;
  8396. printk("\t reserved1--%d \n", misc_reg->reserved1);
  8397. printk("\t manual_stop--%d \n", misc_reg->manual_stop);
  8398. printk("\t thread_id--%d \n", misc_reg->thread_id);
  8399. printk("\t burst_num--%d \n", misc_reg->burst_num);
  8400. printk("\t tx_empty_threshold--%d \n", misc_reg->tx_empty_threshold);
  8401. printk("\t rx_full_threshold--%d \n", misc_reg->rx_full_threshold);
  8402. printk("\t dat_line_delay--%d \n", misc_reg->dat_line_delay);
  8403. printk("\t cmd_line_delay--%d \n", misc_reg->cmd_line_delay);
  8404. }
  8405. value = READ_CBUS_REG(SD_REG8_DATA);
  8406. printk("SD_REG8_DATA=0x%08x -- %u\n", value, value);
  8407. value = READ_CBUS_REG(SD_REG9_ICTL);
  8408. printk("SD_REG9_ICTL=0x%08x -- %u\n", value, value);
  8409. {
  8410. SDXC_Ictl_Reg_t *ictl_reg = (SDXC_Ictl_Reg_t *)&value;
  8411. printk("\t reserved2--%d \n", ictl_reg->reserved2);
  8412. printk("\t sdio_dat1_mask_delay--%d \n", ictl_reg->sdio_dat1_mask_delay);
  8413. printk("\t reserved1--%d \n", ictl_reg->reserved1);
  8414. printk("\t additional_sdio_dat1_int_en--%d \n", ictl_reg->additional_sdio_dat1_int_en);
  8415. printk("\t tx_fifo_empty_int_en--%d \n", ictl_reg->tx_fifo_empty_int_en);
  8416. printk("\t rx_fifo_full_int_en--%d \n", ictl_reg->rx_fifo_full_int_en);
  8417. printk("\t dma_done_int_en--%d \n", ictl_reg->dma_done_int_en);
  8418. printk("\t sdio_dat1_int_en--%d \n", ictl_reg->sdio_dat1_int_en);
  8419. printk("\t tx_fifo_int_en--%d \n", ictl_reg->tx_fifo_int_en);
  8420. printk("\t rx_fifo_int_en--%d \n", ictl_reg->rx_fifo_int_en);
  8421. printk("\t data_complete_int_en--%d \n", ictl_reg->data_complete_int_en);
  8422. printk("\t pack_crc_err_int_en--%d \n", ictl_reg->pack_crc_err_int_en);
  8423. printk("\t pack_timeout_int_en--%d \n", ictl_reg->pack_timeout_int_en);
  8424. printk("\t pack_complete_int_en--%d \n", ictl_reg->pack_complete_int_en);
  8425. printk("\t dat0_ready_int_en--%d \n", ictl_reg->dat0_ready_int_en);
  8426. printk("\t res_crc_err_int_en--%d \n", ictl_reg->res_crc_err_int_en);
  8427. printk("\t res_timeout_int_en--%d \n", ictl_reg->res_timeout_int_en);
  8428. printk("\t res_ok_int_en--%d \n", ictl_reg->res_ok_int_en);
  8429. }
  8430. value = READ_CBUS_REG(SD_REGA_ISTA);
  8431. printk("SD_REGA_ISTA=0x%08x -- %u\n", value, value);
  8432. {
  8433. SDXC_Ista_Reg_t *ista_reg = (SDXC_Ista_Reg_t *)&value;
  8434. printk("\t reserved1--%d \n", ista_reg->reserved1);
  8435. printk("\t additional_sdio_dat1_int--%d \n", ista_reg->additional_sdio_dat1_int);
  8436. printk("\t tx_fifo_empty_int--%d \n", ista_reg->tx_fifo_empty_int);
  8437. printk("\t rx_fifo_full_int--%d \n", ista_reg->rx_fifo_full_int);
  8438. printk("\t dma_done_int--%d \n", ista_reg->dma_done_int);
  8439. printk("\t sdio_dat1_int*--%d \n", ista_reg->sdio_dat1_int);
  8440. printk("\t tx_fifo_int--%d \n", ista_reg->tx_fifo_int);
  8441. printk("\t rx_fifo_int--%d \n", ista_reg->rx_fifo_int);
  8442. printk("\t data_complete_int*--%d \n", ista_reg->data_complete_int);
  8443. printk("\t pack_crc_err_int--%d \n", ista_reg->pack_crc_err_int);
  8444. printk("\t pack_timeout_int--%d \n", ista_reg->pack_timeout_int);
  8445. printk("\t pack_complete_int--%d \n", ista_reg->pack_complete_int);
  8446. printk("\t dat0_ready_int--%d \n", ista_reg->dat0_ready_int);
  8447. printk("\t res_crc_err_int--%d \n", ista_reg->res_crc_err_int);
  8448. printk("\t res_timeout_int--%d \n", ista_reg->res_timeout_int);
  8449. printk("\t res_ok_int*--%d \n", ista_reg->res_ok_int);
  8450. }
  8451. value = READ_CBUS_REG(SD_REGB_SRST);
  8452. printk("SD_REGB_SRST=0x%08x -- %u\n", value, value);
  8453. {
  8454. SDXC_Srst_Reg_t *srst_reg = (SDXC_Srst_Reg_t *)&value;
  8455. printk("\t reserved1--%d \n", srst_reg->reserved1);
  8456. printk("\t dma_srst--%d \n", srst_reg->dma_srst);
  8457. printk("\t tx_dphy_srst--%d \n", srst_reg->tx_dphy_srst);
  8458. printk("\t rx_dphy_srst--%d \n", srst_reg->rx_dphy_srst);
  8459. printk("\t tx_fifo_srst--%d \n", srst_reg->tx_fifo_srst);
  8460. printk("\t rx_fifo_srst--%d \n", srst_reg->rx_fifo_srst);
  8461. printk("\t main_ctrl_srst--%d \n\n", srst_reg->main_ctrl_srst);
  8462. }
  8463. }
  8464. static void my_write_reg(char *buf)
  8465. {
  8466. unsigned int addr;
  8467. unsigned int value;
  8468. if (!((buf[0] >= '0' && buf[0] <= '9') || buf[0] == 'A' || buf[0] == 'B'))
  8469. {
  8470. printk("wrong addr\n");
  8471. return;
  8472. }
  8473. if (buf[0] >= '0' && buf[0] <= '9')
  8474. addr = buf[0] - '0' + 0x2380; //0x2380 is the sdhc controller's base address
  8475. else
  8476. addr = buf[0] - 'A' + 10 + 0x2380;
  8477. value = my_parse_num(buf + 2, NULL);
  8478. printk("cmd5 : set addr(0x%x) to 0x%08x -- %d\n", addr, value, value);
  8479. switch (buf[0]) {
  8480. case '0' : WRITE_CBUS_REG(SD_REG0_ARGU, value); break;
  8481. case '1' : WRITE_CBUS_REG(SD_REG1_SEND, value); break;
  8482. case '2' : WRITE_CBUS_REG(SD_REG2_CNTL, value); break;
  8483. case '3' : WRITE_CBUS_REG(SD_REG3_STAT, value); break;
  8484. case '4' : WRITE_CBUS_REG(SD_REG4_CLKC, value); break;
  8485. case '5' : WRITE_CBUS_REG(SD_REG5_ADDR, value); break;
  8486. case '6' : WRITE_CBUS_REG(SD_REG6_PDMA, value); break;
  8487. case '7' : WRITE_CBUS_REG(SD_REG7_MISC, value); break;
  8488. case '8' : WRITE_CBUS_REG(SD_REG8_DATA, value); break;
  8489. case '9' : WRITE_CBUS_REG(SD_REG9_ICTL, value); break;
  8490. case 'A' : WRITE_CBUS_REG(SD_REGA_ISTA, value); break;
  8491. case 'B' : WRITE_CBUS_REG(SD_REGB_SRST, value); break;
  8492. default : printk("wrong reg num\n"); break;
  8493. }
  8494. /*
  8495. if (buf[0] >= '0' && buf[0] <= '9')
  8496. addr = buf[0] - '0' + 0x2380; //0x2380 is the sdhc controller's base address
  8497. else
  8498. addr = buf[0] - 'A' + 10 + 0x2380;
  8499. value = my_parse_num(buf + 2, NULL);
  8500. printk("cmd5 : set addr(0x%x) to 0x%08x -- %d\n", addr, value, value);
  8501. WRITE_CBUS_REG(addr, value);
  8502. */
  8503. }
  8504. #include <linux/init.h>
  8505. #include <linux/module.h>
  8506. #include <linux/moduleparam.h>
  8507. #include <linux/types.h>
  8508. #include <linux/kernel.h>
  8509. #include <linux/proc_fs.h>
  8510. #include <linux/timer.h>
  8511. #include <asm/uaccess.h>
  8512. static struct proc_dir_entry *my_dir,*my_file;
  8513. extern struct card_host * the_card_host;
  8514. //echo 10 > /proc/sdxc/cmd
  8515. ///sdxc_send_cmd_hw()
  8516. static ssize_t my_write( struct file *file,
  8517. const char __user *buffer,
  8518. size_t len,
  8519. loff_t *offset )
  8520. {
  8521. char command;
  8522. char *tmp_buf = kmalloc(len + 1, GFP_KERNEL);
  8523. if (tmp_buf == NULL)
  8524. return -EINVAL;
  8525. if (copy_from_user(tmp_buf, buffer, len))
  8526. return -EFAULT;
  8527. tmp_buf[len] = '\0';
  8528. command = tmp_buf[0];
  8529. switch (command)
  8530. {
  8531. case '0' :
  8532. my_test(&tmp_buf[2]);
  8533. break;
  8534. case '1' : //setup : 1 0 or 1 1
  8535. if (sdxc_card != NULL)
  8536. {
  8537. printk("card(%p) exist, will be freed first\n", sdxc_card);
  8538. kfree(sdxc_card);
  8539. sdxc_card = NULL;
  8540. }
  8541. sdxc_card = sdxc_card_setup(the_card_host, my_parse_num(&tmp_buf[2], NULL));
  8542. if (sdxc_card)
  8543. printk("card(%p) setup success\n", sdxc_card);
  8544. else
  8545. printk("card setup fail\n");
  8546. break;
  8547. case '2' : //check present : 2
  8548. if (sdxc_card == NULL)
  8549. {
  8550. printk("send me command 1 first\n");
  8551. }
  8552. else
  8553. {
  8554. if (sdxc_card_present(sdxc_card))
  8555. printk("card is present\n");
  8556. else
  8557. printk("card not present\n");
  8558. }
  8559. break;
  8560. case '3' : //identify : 36 //6 is steps (1~6)
  8561. if (sdxc_card == NULL)
  8562. {
  8563. printk("send me command 1 first\n");
  8564. }
  8565. else
  8566. {
  8567. int steps;
  8568. if (tmp_buf[1] >= '1' && tmp_buf[1] <= '9')
  8569. steps = tmp_buf[1] - '0';
  8570. else
  8571. steps = 2;
  8572. if (sdxc_card_identify(sdxc_card, steps) == 0) ///sdxc_identify_verbose()
  8573. printk("steps=%d success\n", steps);
  8574. else
  8575. printk("steps=%d fail\n", steps);
  8576. }
  8577. break;
  8578. case '4' : //disp regs : 4
  8579. my_disp_sdhc_regs();
  8580. break;
  8581. case '5' : //write reg : 5 2 37 //2nd is reg num (0~9,A,B), 3rd is value in decimal
  8582. my_write_reg(&tmp_buf[2]);
  8583. break;
  8584. case '7' : //send single cmd : 7 0 //2nd is cmd idx (0, 8, 41, 2, 3, 10, 9, 7, 51, 6) //acmd41, acmd51, acmd6
  8585. //other cmds : 55, 42, 46
  8586. {
  8587. unsigned int cmd;
  8588. int ret;
  8589. cmd = my_parse_num(&tmp_buf[2], NULL);
  8590. ret = sdxc_card_cmd(sdxc_card, cmd);
  8591. if (ret == 0)
  8592. printk("send cmd%d success\n", cmd);
  8593. else
  8594. printk("send cmd%d fail with %s\n", cmd, sd_error_to_string(ret));
  8595. break;
  8596. }
  8597. case '8' : //send all identify cmds except acmd6 : 8
  8598. {
  8599. int ret = 0;
  8600. unsigned int cmds[] = {0, 8, 42, 2, 3, 10, 9, 7, 51};
  8601. int count = sizeof(cmds) / sizeof(cmds[0]);
  8602. int i = 0;
  8603. while (ret == 0 && i < count)
  8604. {
  8605. ret = sdxc_card_cmd(sdxc_card, cmds[i]);
  8606. i++;
  8607. }
  8608. if (ret == 0)
  8609. printk("card identify success\n");
  8610. else
  8611. printk("card identify fail\n");
  8612. break;
  8613. }
  8614. case '9' : //send rw cmds : 9 17 6550550 //2nd is cmd (17, 18, 24, 25), 3rd is lba, 4th is cnt
  8615. //two other funcs(20, 21) : 9 20 wr_start_num, 9 21 rw_delay_us
  8616. {
  8617. int ret;
  8618. unsigned int cmd;
  8619. unsigned int lba;
  8620. unsigned int cnt;
  8621. char *pcur;
  8622. cmd = my_parse_num(&tmp_buf[2], &pcur);
  8623. lba = my_parse_num(pcur, &pcur);
  8624. cnt = my_parse_num(pcur, &pcur);
  8625. ret = sdxc_card_rw(sdxc_card, cmd, lba, cnt);
  8626. if (ret == 0)
  8627. printk("card rw success\n");
  8628. else
  8629. printk("card rw fail : %s\n", sd_error_to_string(ret));
  8630. break;
  8631. }
  8632. default :
  8633. printk("unknow command : %c\n", command);
  8634. break;
  8635. }
  8636. kfree(tmp_buf);
  8637. return len;
  8638. }
  8639. static ssize_t my_read( struct file *file,
  8640. char __user *buffer,
  8641. size_t len,
  8642. loff_t *offset )
  8643. {
  8644. int ret;
  8645. printk("params : buffer=%p, len=%d, offset=%d\n", buffer, len, (unsigned int)*offset);
  8646. if (*offset == 0)
  8647. {
  8648. ret = sprintf(buffer, "sdxc_card(%p)\n", sdxc_card);
  8649. *offset = ret;
  8650. }
  8651. else
  8652. {
  8653. ret = 0;
  8654. }
  8655. return ret;
  8656. }
  8657. static int my_open( struct inode *inode,
  8658. struct file *file )
  8659. {
  8660. return 0;
  8661. }
  8662. static int my_close( struct inode *inode, struct file *file )
  8663. {
  8664. return 0;
  8665. }
  8666. static const struct file_operations my_ops = {
  8667. .owner = THIS_MODULE,
  8668. .read = my_read,
  8669. .write = my_write,
  8670. .open = my_open,
  8671. .release = my_close
  8672. };
  8673. #define MYDIR "sdxc"
  8674. #define MYFILE "cmd"
  8675. int my_init(void)
  8676. {
  8677. my_dir = (struct proc_dir_entry * )proc_mkdir(MYDIR,NULL);
  8678. if(my_dir == NULL){
  8679. printk("mkdir fail\n");
  8680. return -1;
  8681. }
  8682. my_file = (struct proc_dir_entry * )proc_create_data(MYFILE,0777,my_dir, &my_ops, NULL);
  8683. if(my_file == NULL){
  8684. remove_proc_entry(MYDIR, NULL);
  8685. my_dir = NULL;
  8686. printk("mkfile fail\n");
  8687. return -1;
  8688. }
  8689. return 0;
  8690. }
  8691. void my_cleanup(void)
  8692. {
  8693. if (my_file)
  8694. remove_proc_entry(MYFILE,my_dir);
  8695. if (my_dir)
  8696. remove_proc_entry(MYDIR, NULL);
  8697. }
  8698. module_init(my_init);
  8699. module_exit(my_cleanup);