tlb.c 1.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /* arch/sparc64/mm/tlb.c
  2. *
  3. * Copyright (C) 2004 David S. Miller <davem@redhat.com>
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/init.h>
  7. #include <linux/percpu.h>
  8. #include <linux/mm.h>
  9. #include <linux/swap.h>
  10. #include <linux/preempt.h>
  11. #include <asm/pgtable.h>
  12. #include <asm/pgalloc.h>
  13. #include <asm/tlbflush.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/mmu_context.h>
  16. #include <asm/tlb.h>
  17. /* Heavily inspired by the ppc64 code. */
  18. static DEFINE_PER_CPU(struct tlb_batch, tlb_batch);
  19. void flush_tlb_pending(void)
  20. {
  21. struct tlb_batch *tb = &get_cpu_var(tlb_batch);
  22. if (tb->tlb_nr) {
  23. flush_tsb_user(tb);
  24. if (CTX_VALID(tb->mm->context)) {
  25. #ifdef CONFIG_SMP
  26. smp_flush_tlb_pending(tb->mm, tb->tlb_nr,
  27. &tb->vaddrs[0]);
  28. #else
  29. __flush_tlb_pending(CTX_HWBITS(tb->mm->context),
  30. tb->tlb_nr, &tb->vaddrs[0]);
  31. #endif
  32. }
  33. tb->tlb_nr = 0;
  34. }
  35. put_cpu_var(tlb_batch);
  36. }
  37. void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
  38. pte_t *ptep, pte_t orig, int fullmm)
  39. {
  40. struct tlb_batch *tb = &get_cpu_var(tlb_batch);
  41. unsigned long nr;
  42. vaddr &= PAGE_MASK;
  43. if (pte_exec(orig))
  44. vaddr |= 0x1UL;
  45. if (tlb_type != hypervisor &&
  46. pte_dirty(orig)) {
  47. unsigned long paddr, pfn = pte_pfn(orig);
  48. struct address_space *mapping;
  49. struct page *page;
  50. if (!pfn_valid(pfn))
  51. goto no_cache_flush;
  52. page = pfn_to_page(pfn);
  53. if (PageReserved(page))
  54. goto no_cache_flush;
  55. /* A real file page? */
  56. mapping = page_mapping(page);
  57. if (!mapping)
  58. goto no_cache_flush;
  59. paddr = (unsigned long) page_address(page);
  60. if ((paddr ^ vaddr) & (1 << 13))
  61. flush_dcache_page_all(mm, page);
  62. }
  63. no_cache_flush:
  64. if (fullmm) {
  65. put_cpu_var(tlb_batch);
  66. return;
  67. }
  68. nr = tb->tlb_nr;
  69. if (unlikely(nr != 0 && mm != tb->mm)) {
  70. flush_tlb_pending();
  71. nr = 0;
  72. }
  73. if (nr == 0)
  74. tb->mm = mm;
  75. tb->vaddrs[nr] = vaddr;
  76. tb->tlb_nr = ++nr;
  77. if (nr >= TLB_BATCH_NR)
  78. flush_tlb_pending();
  79. put_cpu_var(tlb_batch);
  80. }