sun4d_irq.c 12 KB

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  1. /*
  2. * SS1000/SC2000 interrupt handling.
  3. *
  4. * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  5. * Heavily based on arch/sparc/kernel/irq.c.
  6. */
  7. #include <linux/kernel_stat.h>
  8. #include <linux/seq_file.h>
  9. #include <asm/timer.h>
  10. #include <asm/traps.h>
  11. #include <asm/irq.h>
  12. #include <asm/io.h>
  13. #include <asm/sbi.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/setup.h>
  16. #include "kernel.h"
  17. #include "irq.h"
  18. /* Sun4d interrupts fall roughly into two categories. SBUS and
  19. * cpu local. CPU local interrupts cover the timer interrupts
  20. * and whatnot, and we encode those as normal PILs between
  21. * 0 and 15.
  22. * SBUS interrupts are encodes as a combination of board, level and slot.
  23. */
  24. struct sun4d_handler_data {
  25. unsigned int cpuid; /* target cpu */
  26. unsigned int real_irq; /* interrupt level */
  27. };
  28. static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
  29. {
  30. return (board + 1) << 5 | (lvl << 2) | slot;
  31. }
  32. struct sun4d_timer_regs {
  33. u32 l10_timer_limit;
  34. u32 l10_cur_countx;
  35. u32 l10_limit_noclear;
  36. u32 ctrl;
  37. u32 l10_cur_count;
  38. };
  39. static struct sun4d_timer_regs __iomem *sun4d_timers;
  40. #define SUN4D_TIMER_IRQ 10
  41. /* Specify which cpu handle interrupts from which board.
  42. * Index is board - value is cpu.
  43. */
  44. static unsigned char board_to_cpu[32];
  45. static int pil_to_sbus[] = {
  46. 0,
  47. 0,
  48. 1,
  49. 2,
  50. 0,
  51. 3,
  52. 0,
  53. 4,
  54. 0,
  55. 5,
  56. 0,
  57. 6,
  58. 0,
  59. 7,
  60. 0,
  61. 0,
  62. };
  63. /* Exported for sun4d_smp.c */
  64. DEFINE_SPINLOCK(sun4d_imsk_lock);
  65. /* SBUS interrupts are encoded integers including the board number
  66. * (plus one), the SBUS level, and the SBUS slot number. Sun4D
  67. * IRQ dispatch is done by:
  68. *
  69. * 1) Reading the BW local interrupt table in order to get the bus
  70. * interrupt mask.
  71. *
  72. * This table is indexed by SBUS interrupt level which can be
  73. * derived from the PIL we got interrupted on.
  74. *
  75. * 2) For each bus showing interrupt pending from #1, read the
  76. * SBI interrupt state register. This will indicate which slots
  77. * have interrupts pending for that SBUS interrupt level.
  78. *
  79. * 3) Call the genreric IRQ support.
  80. */
  81. static void sun4d_sbus_handler_irq(int sbusl)
  82. {
  83. unsigned int bus_mask;
  84. unsigned int sbino, slot;
  85. unsigned int sbil;
  86. bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
  87. bw_clear_intr_mask(sbusl, bus_mask);
  88. sbil = (sbusl << 2);
  89. /* Loop for each pending SBI */
  90. for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
  91. unsigned int idx, mask;
  92. if (!(bus_mask & 1))
  93. continue;
  94. /* XXX This seems to ACK the irq twice. acquire_sbi()
  95. * XXX uses swap, therefore this writes 0xf << sbil,
  96. * XXX then later release_sbi() will write the individual
  97. * XXX bits which were set again.
  98. */
  99. mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
  100. mask &= (0xf << sbil);
  101. /* Loop for each pending SBI slot */
  102. slot = (1 << sbil);
  103. for (idx = 0; mask != 0; idx++, slot <<= 1) {
  104. unsigned int pil;
  105. struct irq_bucket *p;
  106. if (!(mask & slot))
  107. continue;
  108. mask &= ~slot;
  109. pil = sun4d_encode_irq(sbino, sbusl, idx);
  110. p = irq_map[pil];
  111. while (p) {
  112. struct irq_bucket *next;
  113. next = p->next;
  114. generic_handle_irq(p->irq);
  115. p = next;
  116. }
  117. release_sbi(SBI2DEVID(sbino), slot);
  118. }
  119. }
  120. }
  121. void sun4d_handler_irq(int pil, struct pt_regs *regs)
  122. {
  123. struct pt_regs *old_regs;
  124. /* SBUS IRQ level (1 - 7) */
  125. int sbusl = pil_to_sbus[pil];
  126. /* FIXME: Is this necessary?? */
  127. cc_get_ipen();
  128. cc_set_iclr(1 << pil);
  129. #ifdef CONFIG_SMP
  130. /*
  131. * Check IPI data structures after IRQ has been cleared. Hard and Soft
  132. * IRQ can happen at the same time, so both cases are always handled.
  133. */
  134. if (pil == SUN4D_IPI_IRQ)
  135. sun4d_ipi_interrupt();
  136. #endif
  137. old_regs = set_irq_regs(regs);
  138. irq_enter();
  139. if (sbusl == 0) {
  140. /* cpu interrupt */
  141. struct irq_bucket *p;
  142. p = irq_map[pil];
  143. while (p) {
  144. struct irq_bucket *next;
  145. next = p->next;
  146. generic_handle_irq(p->irq);
  147. p = next;
  148. }
  149. } else {
  150. /* SBUS interrupt */
  151. sun4d_sbus_handler_irq(sbusl);
  152. }
  153. irq_exit();
  154. set_irq_regs(old_regs);
  155. }
  156. static void sun4d_mask_irq(struct irq_data *data)
  157. {
  158. struct sun4d_handler_data *handler_data = data->handler_data;
  159. unsigned int real_irq;
  160. #ifdef CONFIG_SMP
  161. int cpuid = handler_data->cpuid;
  162. unsigned long flags;
  163. #endif
  164. real_irq = handler_data->real_irq;
  165. #ifdef CONFIG_SMP
  166. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  167. cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
  168. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  169. #else
  170. cc_set_imsk(cc_get_imsk() | (1 << real_irq));
  171. #endif
  172. }
  173. static void sun4d_unmask_irq(struct irq_data *data)
  174. {
  175. struct sun4d_handler_data *handler_data = data->handler_data;
  176. unsigned int real_irq;
  177. #ifdef CONFIG_SMP
  178. int cpuid = handler_data->cpuid;
  179. unsigned long flags;
  180. #endif
  181. real_irq = handler_data->real_irq;
  182. #ifdef CONFIG_SMP
  183. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  184. cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
  185. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  186. #else
  187. cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
  188. #endif
  189. }
  190. static unsigned int sun4d_startup_irq(struct irq_data *data)
  191. {
  192. irq_link(data->irq);
  193. sun4d_unmask_irq(data);
  194. return 0;
  195. }
  196. static void sun4d_shutdown_irq(struct irq_data *data)
  197. {
  198. sun4d_mask_irq(data);
  199. irq_unlink(data->irq);
  200. }
  201. struct irq_chip sun4d_irq = {
  202. .name = "sun4d",
  203. .irq_startup = sun4d_startup_irq,
  204. .irq_shutdown = sun4d_shutdown_irq,
  205. .irq_unmask = sun4d_unmask_irq,
  206. .irq_mask = sun4d_mask_irq,
  207. };
  208. #ifdef CONFIG_SMP
  209. static void sun4d_set_cpu_int(int cpu, int level)
  210. {
  211. sun4d_send_ipi(cpu, level);
  212. }
  213. static void sun4d_clear_ipi(int cpu, int level)
  214. {
  215. }
  216. static void sun4d_set_udt(int cpu)
  217. {
  218. }
  219. /* Setup IRQ distribution scheme. */
  220. void __init sun4d_distribute_irqs(void)
  221. {
  222. struct device_node *dp;
  223. int cpuid = cpu_logical_map(1);
  224. if (cpuid == -1)
  225. cpuid = cpu_logical_map(0);
  226. for_each_node_by_name(dp, "sbi") {
  227. int devid = of_getintprop_default(dp, "device-id", 0);
  228. int board = of_getintprop_default(dp, "board#", 0);
  229. board_to_cpu[board] = cpuid;
  230. set_sbi_tid(devid, cpuid << 3);
  231. }
  232. printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
  233. }
  234. #endif
  235. static void sun4d_clear_clock_irq(void)
  236. {
  237. sbus_readl(&sun4d_timers->l10_timer_limit);
  238. }
  239. static void sun4d_load_profile_irq(int cpu, unsigned int limit)
  240. {
  241. bw_set_prof_limit(cpu, limit);
  242. }
  243. static void __init sun4d_load_profile_irqs(void)
  244. {
  245. int cpu = 0, mid;
  246. while (!cpu_find_by_instance(cpu, NULL, &mid)) {
  247. sun4d_load_profile_irq(mid >> 3, 0);
  248. cpu++;
  249. }
  250. }
  251. unsigned int _sun4d_build_device_irq(unsigned int real_irq,
  252. unsigned int pil,
  253. unsigned int board)
  254. {
  255. struct sun4d_handler_data *handler_data;
  256. unsigned int irq;
  257. irq = irq_alloc(real_irq, pil);
  258. if (irq == 0) {
  259. prom_printf("IRQ: allocate for %d %d %d failed\n",
  260. real_irq, pil, board);
  261. goto err_out;
  262. }
  263. handler_data = irq_get_handler_data(irq);
  264. if (unlikely(handler_data))
  265. goto err_out;
  266. handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
  267. if (unlikely(!handler_data)) {
  268. prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
  269. prom_halt();
  270. }
  271. handler_data->cpuid = board_to_cpu[board];
  272. handler_data->real_irq = real_irq;
  273. irq_set_chip_and_handler_name(irq, &sun4d_irq,
  274. handle_level_irq, "level");
  275. irq_set_handler_data(irq, handler_data);
  276. err_out:
  277. return irq;
  278. }
  279. unsigned int sun4d_build_device_irq(struct platform_device *op,
  280. unsigned int real_irq)
  281. {
  282. struct device_node *dp = op->dev.of_node;
  283. struct device_node *board_parent, *bus = dp->parent;
  284. char *bus_connection;
  285. const struct linux_prom_registers *regs;
  286. unsigned int pil;
  287. unsigned int irq;
  288. int board, slot;
  289. int sbusl;
  290. irq = real_irq;
  291. while (bus) {
  292. if (!strcmp(bus->name, "sbi")) {
  293. bus_connection = "io-unit";
  294. break;
  295. }
  296. if (!strcmp(bus->name, "bootbus")) {
  297. bus_connection = "cpu-unit";
  298. break;
  299. }
  300. bus = bus->parent;
  301. }
  302. if (!bus)
  303. goto err_out;
  304. regs = of_get_property(dp, "reg", NULL);
  305. if (!regs)
  306. goto err_out;
  307. slot = regs->which_io;
  308. /*
  309. * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
  310. * lacks a "board#" property, something is very wrong.
  311. */
  312. if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
  313. printk(KERN_ERR "%s: Error, parent is not %s.\n",
  314. bus->full_name, bus_connection);
  315. goto err_out;
  316. }
  317. board_parent = bus->parent;
  318. board = of_getintprop_default(board_parent, "board#", -1);
  319. if (board == -1) {
  320. printk(KERN_ERR "%s: Error, lacks board# property.\n",
  321. board_parent->full_name);
  322. goto err_out;
  323. }
  324. sbusl = pil_to_sbus[real_irq];
  325. if (sbusl)
  326. pil = sun4d_encode_irq(board, sbusl, slot);
  327. else
  328. pil = real_irq;
  329. irq = _sun4d_build_device_irq(real_irq, pil, board);
  330. err_out:
  331. return irq;
  332. }
  333. unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
  334. {
  335. return _sun4d_build_device_irq(real_irq, real_irq, board);
  336. }
  337. static void __init sun4d_fixup_trap_table(void)
  338. {
  339. #ifdef CONFIG_SMP
  340. unsigned long flags;
  341. struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
  342. /* Adjust so that we jump directly to smp4d_ticker */
  343. lvl14_save[2] += smp4d_ticker - real_irq_entry;
  344. /* For SMP we use the level 14 ticker, however the bootup code
  345. * has copied the firmware's level 14 vector into the boot cpu's
  346. * trap table, we must fix this now or we get squashed.
  347. */
  348. local_irq_save(flags);
  349. patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
  350. trap_table->inst_one = lvl14_save[0];
  351. trap_table->inst_two = lvl14_save[1];
  352. trap_table->inst_three = lvl14_save[2];
  353. trap_table->inst_four = lvl14_save[3];
  354. local_flush_cache_all();
  355. local_irq_restore(flags);
  356. #endif
  357. }
  358. static void __init sun4d_init_timers(irq_handler_t counter_fn)
  359. {
  360. struct device_node *dp;
  361. struct resource res;
  362. unsigned int irq;
  363. const u32 *reg;
  364. int err;
  365. int board;
  366. dp = of_find_node_by_name(NULL, "cpu-unit");
  367. if (!dp) {
  368. prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
  369. prom_halt();
  370. }
  371. /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
  372. * registers via any cpu's mapping. The first 'reg' property is the
  373. * bootbus.
  374. */
  375. reg = of_get_property(dp, "reg", NULL);
  376. if (!reg) {
  377. prom_printf("sun4d_init_timers: No reg property\n");
  378. prom_halt();
  379. }
  380. board = of_getintprop_default(dp, "board#", -1);
  381. if (board == -1) {
  382. prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
  383. prom_halt();
  384. }
  385. of_node_put(dp);
  386. res.start = reg[1];
  387. res.end = reg[2] - 1;
  388. res.flags = reg[0] & 0xff;
  389. sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
  390. sizeof(struct sun4d_timer_regs), "user timer");
  391. if (!sun4d_timers) {
  392. prom_printf("sun4d_init_timers: Can't map timer regs\n");
  393. prom_halt();
  394. }
  395. sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit);
  396. master_l10_counter = &sun4d_timers->l10_cur_count;
  397. irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
  398. err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
  399. if (err) {
  400. prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
  401. err);
  402. prom_halt();
  403. }
  404. sun4d_load_profile_irqs();
  405. sun4d_fixup_trap_table();
  406. }
  407. void __init sun4d_init_sbi_irq(void)
  408. {
  409. struct device_node *dp;
  410. int target_cpu;
  411. target_cpu = boot_cpu_id;
  412. for_each_node_by_name(dp, "sbi") {
  413. int devid = of_getintprop_default(dp, "device-id", 0);
  414. int board = of_getintprop_default(dp, "board#", 0);
  415. unsigned int mask;
  416. set_sbi_tid(devid, target_cpu << 3);
  417. board_to_cpu[board] = target_cpu;
  418. /* Get rid of pending irqs from PROM */
  419. mask = acquire_sbi(devid, 0xffffffff);
  420. if (mask) {
  421. printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
  422. mask, board);
  423. release_sbi(devid, mask);
  424. }
  425. }
  426. }
  427. void __init sun4d_init_IRQ(void)
  428. {
  429. local_irq_disable();
  430. BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
  431. BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
  432. sparc_irq_config.init_timers = sun4d_init_timers;
  433. sparc_irq_config.build_device_irq = sun4d_build_device_irq;
  434. #ifdef CONFIG_SMP
  435. BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
  436. BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
  437. BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
  438. #endif
  439. /* Cannot enable interrupts until OBP ticker is disabled. */
  440. }