mpc8xx_pic.c 4.1 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/module.h>
  3. #include <linux/stddef.h>
  4. #include <linux/init.h>
  5. #include <linux/sched.h>
  6. #include <linux/signal.h>
  7. #include <linux/irq.h>
  8. #include <linux/dma-mapping.h>
  9. #include <asm/prom.h>
  10. #include <asm/irq.h>
  11. #include <asm/io.h>
  12. #include <asm/8xx_immap.h>
  13. #include "mpc8xx_pic.h"
  14. #define PIC_VEC_SPURRIOUS 15
  15. extern int cpm_get_irq(struct pt_regs *regs);
  16. static struct irq_host *mpc8xx_pic_host;
  17. #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
  18. static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  19. static sysconf8xx_t __iomem *siu_reg;
  20. int cpm_get_irq(struct pt_regs *regs);
  21. static void mpc8xx_unmask_irq(struct irq_data *d)
  22. {
  23. int bit, word;
  24. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  25. bit = irq_nr & 0x1f;
  26. word = irq_nr >> 5;
  27. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  28. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  29. }
  30. static void mpc8xx_mask_irq(struct irq_data *d)
  31. {
  32. int bit, word;
  33. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  34. bit = irq_nr & 0x1f;
  35. word = irq_nr >> 5;
  36. ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  37. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  38. }
  39. static void mpc8xx_ack(struct irq_data *d)
  40. {
  41. int bit;
  42. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  43. bit = irq_nr & 0x1f;
  44. out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  45. }
  46. static void mpc8xx_end_irq(struct irq_data *d)
  47. {
  48. int bit, word;
  49. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  50. bit = irq_nr & 0x1f;
  51. word = irq_nr >> 5;
  52. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  53. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  54. }
  55. static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
  56. {
  57. if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  58. irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
  59. unsigned int siel = in_be32(&siu_reg->sc_siel);
  60. /* only external IRQ senses are programmable */
  61. if ((hw & 1) == 0) {
  62. siel |= (0x80000000 >> hw);
  63. out_be32(&siu_reg->sc_siel, siel);
  64. __irq_set_handler_locked(d->irq, handle_edge_irq);
  65. }
  66. }
  67. return 0;
  68. }
  69. static struct irq_chip mpc8xx_pic = {
  70. .name = "MPC8XX SIU",
  71. .irq_unmask = mpc8xx_unmask_irq,
  72. .irq_mask = mpc8xx_mask_irq,
  73. .irq_ack = mpc8xx_ack,
  74. .irq_eoi = mpc8xx_end_irq,
  75. .irq_set_type = mpc8xx_set_irq_type,
  76. };
  77. unsigned int mpc8xx_get_irq(void)
  78. {
  79. int irq;
  80. /* For MPC8xx, read the SIVEC register and shift the bits down
  81. * to get the irq number.
  82. */
  83. irq = in_be32(&siu_reg->sc_sivec) >> 26;
  84. if (irq == PIC_VEC_SPURRIOUS)
  85. irq = NO_IRQ;
  86. return irq_linear_revmap(mpc8xx_pic_host, irq);
  87. }
  88. static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
  89. irq_hw_number_t hw)
  90. {
  91. pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
  92. /* Set default irq handle */
  93. irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
  94. return 0;
  95. }
  96. static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
  97. const u32 *intspec, unsigned int intsize,
  98. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  99. {
  100. static unsigned char map_pic_senses[4] = {
  101. IRQ_TYPE_EDGE_RISING,
  102. IRQ_TYPE_LEVEL_LOW,
  103. IRQ_TYPE_LEVEL_HIGH,
  104. IRQ_TYPE_EDGE_FALLING,
  105. };
  106. *out_hwirq = intspec[0];
  107. if (intsize > 1 && intspec[1] < 4)
  108. *out_flags = map_pic_senses[intspec[1]];
  109. else
  110. *out_flags = IRQ_TYPE_NONE;
  111. return 0;
  112. }
  113. static struct irq_host_ops mpc8xx_pic_host_ops = {
  114. .map = mpc8xx_pic_host_map,
  115. .xlate = mpc8xx_pic_host_xlate,
  116. };
  117. int mpc8xx_pic_init(void)
  118. {
  119. struct resource res;
  120. struct device_node *np;
  121. int ret;
  122. np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
  123. if (np == NULL)
  124. np = of_find_node_by_type(NULL, "mpc8xx-pic");
  125. if (np == NULL) {
  126. printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
  127. return -ENOMEM;
  128. }
  129. ret = of_address_to_resource(np, 0, &res);
  130. if (ret)
  131. goto out;
  132. siu_reg = ioremap(res.start, res.end - res.start + 1);
  133. if (siu_reg == NULL) {
  134. ret = -EINVAL;
  135. goto out;
  136. }
  137. mpc8xx_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
  138. 64, &mpc8xx_pic_host_ops, 64);
  139. if (mpc8xx_pic_host == NULL) {
  140. printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
  141. ret = -ENOMEM;
  142. goto out;
  143. }
  144. return 0;
  145. out:
  146. of_node_put(np);
  147. return ret;
  148. }