tqm8560.dts 8.8 KB

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  1. /*
  2. * TQM 8560 Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor Inc.
  5. * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. model = "tqc,tqm8560";
  15. compatible = "tqc,tqm8560";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. ethernet0 = &enet0;
  20. ethernet1 = &enet1;
  21. ethernet2 = &enet2;
  22. serial0 = &serial0;
  23. serial1 = &serial1;
  24. pci0 = &pci0;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. PowerPC,8560@0 {
  30. device_type = "cpu";
  31. reg = <0>;
  32. d-cache-line-size = <32>;
  33. i-cache-line-size = <32>;
  34. d-cache-size = <32768>;
  35. i-cache-size = <32768>;
  36. timebase-frequency = <0>;
  37. bus-frequency = <0>;
  38. clock-frequency = <0>;
  39. next-level-cache = <&L2>;
  40. };
  41. };
  42. memory {
  43. device_type = "memory";
  44. reg = <0x00000000 0x10000000>;
  45. };
  46. soc@e0000000 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. device_type = "soc";
  50. ranges = <0x0 0xe0000000 0x100000>;
  51. bus-frequency = <0>;
  52. compatible = "fsl,mpc8560-immr", "simple-bus";
  53. ecm-law@0 {
  54. compatible = "fsl,ecm-law";
  55. reg = <0x0 0x1000>;
  56. fsl,num-laws = <8>;
  57. };
  58. ecm@1000 {
  59. compatible = "fsl,mpc8560-ecm", "fsl,ecm";
  60. reg = <0x1000 0x1000>;
  61. interrupts = <17 2>;
  62. interrupt-parent = <&mpic>;
  63. };
  64. memory-controller@2000 {
  65. compatible = "fsl,mpc8540-memory-controller";
  66. reg = <0x2000 0x1000>;
  67. interrupt-parent = <&mpic>;
  68. interrupts = <18 2>;
  69. };
  70. L2: l2-cache-controller@20000 {
  71. compatible = "fsl,mpc8540-l2-cache-controller";
  72. reg = <0x20000 0x1000>;
  73. cache-line-size = <32>;
  74. cache-size = <0x40000>; // L2, 256K
  75. interrupt-parent = <&mpic>;
  76. interrupts = <16 2>;
  77. };
  78. i2c@3000 {
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. cell-index = <0>;
  82. compatible = "fsl-i2c";
  83. reg = <0x3000 0x100>;
  84. interrupts = <43 2>;
  85. interrupt-parent = <&mpic>;
  86. dfsrr;
  87. dtt@48 {
  88. compatible = "national,lm75";
  89. reg = <0x48>;
  90. };
  91. rtc@68 {
  92. compatible = "dallas,ds1337";
  93. reg = <0x68>;
  94. };
  95. };
  96. dma@21300 {
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  100. reg = <0x21300 0x4>;
  101. ranges = <0x0 0x21100 0x200>;
  102. cell-index = <0>;
  103. dma-channel@0 {
  104. compatible = "fsl,mpc8560-dma-channel",
  105. "fsl,eloplus-dma-channel";
  106. reg = <0x0 0x80>;
  107. cell-index = <0>;
  108. interrupt-parent = <&mpic>;
  109. interrupts = <20 2>;
  110. };
  111. dma-channel@80 {
  112. compatible = "fsl,mpc8560-dma-channel",
  113. "fsl,eloplus-dma-channel";
  114. reg = <0x80 0x80>;
  115. cell-index = <1>;
  116. interrupt-parent = <&mpic>;
  117. interrupts = <21 2>;
  118. };
  119. dma-channel@100 {
  120. compatible = "fsl,mpc8560-dma-channel",
  121. "fsl,eloplus-dma-channel";
  122. reg = <0x100 0x80>;
  123. cell-index = <2>;
  124. interrupt-parent = <&mpic>;
  125. interrupts = <22 2>;
  126. };
  127. dma-channel@180 {
  128. compatible = "fsl,mpc8560-dma-channel",
  129. "fsl,eloplus-dma-channel";
  130. reg = <0x180 0x80>;
  131. cell-index = <3>;
  132. interrupt-parent = <&mpic>;
  133. interrupts = <23 2>;
  134. };
  135. };
  136. enet0: ethernet@24000 {
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. cell-index = <0>;
  140. device_type = "network";
  141. model = "TSEC";
  142. compatible = "gianfar";
  143. reg = <0x24000 0x1000>;
  144. ranges = <0x0 0x24000 0x1000>;
  145. local-mac-address = [ 00 00 00 00 00 00 ];
  146. interrupts = <29 2 30 2 34 2>;
  147. interrupt-parent = <&mpic>;
  148. tbi-handle = <&tbi0>;
  149. phy-handle = <&phy2>;
  150. mdio@520 {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. compatible = "fsl,gianfar-mdio";
  154. reg = <0x520 0x20>;
  155. phy1: ethernet-phy@1 {
  156. interrupt-parent = <&mpic>;
  157. interrupts = <8 1>;
  158. reg = <1>;
  159. device_type = "ethernet-phy";
  160. };
  161. phy2: ethernet-phy@2 {
  162. interrupt-parent = <&mpic>;
  163. interrupts = <8 1>;
  164. reg = <2>;
  165. device_type = "ethernet-phy";
  166. };
  167. phy3: ethernet-phy@3 {
  168. interrupt-parent = <&mpic>;
  169. interrupts = <8 1>;
  170. reg = <3>;
  171. device_type = "ethernet-phy";
  172. };
  173. tbi0: tbi-phy@11 {
  174. reg = <0x11>;
  175. device_type = "tbi-phy";
  176. };
  177. };
  178. };
  179. enet1: ethernet@25000 {
  180. #address-cells = <1>;
  181. #size-cells = <1>;
  182. cell-index = <1>;
  183. device_type = "network";
  184. model = "TSEC";
  185. compatible = "gianfar";
  186. reg = <0x25000 0x1000>;
  187. ranges = <0x0 0x25000 0x1000>;
  188. local-mac-address = [ 00 00 00 00 00 00 ];
  189. interrupts = <35 2 36 2 40 2>;
  190. interrupt-parent = <&mpic>;
  191. tbi-handle = <&tbi1>;
  192. phy-handle = <&phy1>;
  193. mdio@520 {
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. compatible = "fsl,gianfar-tbi";
  197. reg = <0x520 0x20>;
  198. tbi1: tbi-phy@11 {
  199. reg = <0x11>;
  200. device_type = "tbi-phy";
  201. };
  202. };
  203. };
  204. mpic: pic@40000 {
  205. interrupt-controller;
  206. #address-cells = <0>;
  207. #interrupt-cells = <2>;
  208. reg = <0x40000 0x40000>;
  209. device_type = "open-pic";
  210. compatible = "chrp,open-pic";
  211. };
  212. cpm@919c0 {
  213. #address-cells = <1>;
  214. #size-cells = <1>;
  215. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  216. reg = <0x919c0 0x30>;
  217. ranges;
  218. muram@80000 {
  219. #address-cells = <1>;
  220. #size-cells = <1>;
  221. ranges = <0 0x80000 0x10000>;
  222. data@0 {
  223. compatible = "fsl,cpm-muram-data";
  224. reg = <0 0x4000 0x9000 0x2000>;
  225. };
  226. };
  227. brg@919f0 {
  228. compatible = "fsl,mpc8560-brg",
  229. "fsl,cpm2-brg",
  230. "fsl,cpm-brg";
  231. reg = <0x919f0 0x10 0x915f0 0x10>;
  232. clock-frequency = <0>;
  233. };
  234. cpmpic: pic@90c00 {
  235. interrupt-controller;
  236. #address-cells = <0>;
  237. #interrupt-cells = <2>;
  238. interrupts = <46 2>;
  239. interrupt-parent = <&mpic>;
  240. reg = <0x90c00 0x80>;
  241. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  242. };
  243. serial0: serial@91a00 {
  244. device_type = "serial";
  245. compatible = "fsl,mpc8560-scc-uart",
  246. "fsl,cpm2-scc-uart";
  247. reg = <0x91a00 0x20 0x88000 0x100>;
  248. fsl,cpm-brg = <1>;
  249. fsl,cpm-command = <0x800000>;
  250. current-speed = <115200>;
  251. interrupts = <40 8>;
  252. interrupt-parent = <&cpmpic>;
  253. };
  254. serial1: serial@91a20 {
  255. device_type = "serial";
  256. compatible = "fsl,mpc8560-scc-uart",
  257. "fsl,cpm2-scc-uart";
  258. reg = <0x91a20 0x20 0x88100 0x100>;
  259. fsl,cpm-brg = <2>;
  260. fsl,cpm-command = <0x4a00000>;
  261. current-speed = <115200>;
  262. interrupts = <41 8>;
  263. interrupt-parent = <&cpmpic>;
  264. };
  265. enet2: ethernet@91340 {
  266. device_type = "network";
  267. compatible = "fsl,mpc8560-fcc-enet",
  268. "fsl,cpm2-fcc-enet";
  269. reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
  270. local-mac-address = [ 00 00 00 00 00 00 ];
  271. fsl,cpm-command = <0x1a400300>;
  272. interrupts = <34 8>;
  273. interrupt-parent = <&cpmpic>;
  274. phy-handle = <&phy3>;
  275. };
  276. };
  277. };
  278. localbus@e0005000 {
  279. compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
  280. "simple-bus";
  281. #address-cells = <2>;
  282. #size-cells = <1>;
  283. reg = <0xe0005000 0x100>; // BRx, ORx, etc.
  284. ranges = <
  285. 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
  286. 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
  287. 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
  288. >;
  289. flash@1,0 {
  290. #address-cells = <1>;
  291. #size-cells = <1>;
  292. compatible = "cfi-flash";
  293. reg = <1 0x0 0x8000000>;
  294. bank-width = <4>;
  295. device-width = <1>;
  296. partition@0 {
  297. label = "kernel";
  298. reg = <0x00000000 0x00200000>;
  299. };
  300. partition@200000 {
  301. label = "root";
  302. reg = <0x00200000 0x00300000>;
  303. };
  304. partition@500000 {
  305. label = "user";
  306. reg = <0x00500000 0x07a00000>;
  307. };
  308. partition@7f00000 {
  309. label = "env1";
  310. reg = <0x07f00000 0x00040000>;
  311. };
  312. partition@7f40000 {
  313. label = "env2";
  314. reg = <0x07f40000 0x00040000>;
  315. };
  316. partition@7f80000 {
  317. label = "u-boot";
  318. reg = <0x07f80000 0x00080000>;
  319. read-only;
  320. };
  321. };
  322. /* Note: CAN support needs be enabled in U-Boot */
  323. can0@2,0 {
  324. compatible = "intel,82527"; // Bosch CC770
  325. reg = <2 0x0 0x100>;
  326. interrupts = <4 1>;
  327. interrupt-parent = <&mpic>;
  328. };
  329. can1@2,100 {
  330. compatible = "intel,82527"; // Bosch CC770
  331. reg = <2 0x100 0x100>;
  332. interrupts = <4 1>;
  333. interrupt-parent = <&mpic>;
  334. };
  335. };
  336. pci0: pci@e0008000 {
  337. #interrupt-cells = <1>;
  338. #size-cells = <2>;
  339. #address-cells = <3>;
  340. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  341. device_type = "pci";
  342. reg = <0xe0008000 0x1000>;
  343. clock-frequency = <66666666>;
  344. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  345. interrupt-map = <
  346. /* IDSEL 28 */
  347. 0xe000 0 0 1 &mpic 2 1
  348. 0xe000 0 0 2 &mpic 3 1
  349. 0xe000 0 0 3 &mpic 6 1
  350. 0xe000 0 0 4 &mpic 5 1
  351. /* IDSEL 11 */
  352. 0x5800 0 0 1 &mpic 6 1
  353. 0x5800 0 0 2 &mpic 5 1
  354. >;
  355. interrupt-parent = <&mpic>;
  356. interrupts = <24 2>;
  357. bus-range = <0 0>;
  358. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  359. 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
  360. };
  361. };