p2020ds.dts 8.0 KB

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  1. /*
  2. * P2020 DS Device Tree Source
  3. *
  4. * Copyright 2009-2011 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /include/ "p2020si.dtsi"
  12. / {
  13. model = "fsl,P2020DS";
  14. compatible = "fsl,P2020DS";
  15. aliases {
  16. ethernet0 = &enet0;
  17. ethernet1 = &enet1;
  18. ethernet2 = &enet2;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. pci1 = &pci1;
  23. pci2 = &pci2;
  24. };
  25. memory {
  26. device_type = "memory";
  27. };
  28. localbus@ffe05000 {
  29. compatible = "fsl,elbc", "simple-bus";
  30. ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  31. 0x1 0x0 0x0 0xe0000000 0x08000000
  32. 0x2 0x0 0x0 0xffa00000 0x00040000
  33. 0x3 0x0 0x0 0xffdf0000 0x00008000
  34. 0x4 0x0 0x0 0xffa40000 0x00040000
  35. 0x5 0x0 0x0 0xffa80000 0x00040000
  36. 0x6 0x0 0x0 0xffac0000 0x00040000>;
  37. nor@0,0 {
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. compatible = "cfi-flash";
  41. reg = <0x0 0x0 0x8000000>;
  42. bank-width = <2>;
  43. device-width = <1>;
  44. ramdisk@0 {
  45. reg = <0x0 0x03000000>;
  46. read-only;
  47. };
  48. diagnostic@3000000 {
  49. reg = <0x03000000 0x00e00000>;
  50. read-only;
  51. };
  52. dink@3e00000 {
  53. reg = <0x03e00000 0x00200000>;
  54. read-only;
  55. };
  56. kernel@4000000 {
  57. reg = <0x04000000 0x00400000>;
  58. read-only;
  59. };
  60. jffs2@4400000 {
  61. reg = <0x04400000 0x03b00000>;
  62. };
  63. dtb@7f00000 {
  64. reg = <0x07f00000 0x00080000>;
  65. read-only;
  66. };
  67. u-boot@7f80000 {
  68. reg = <0x07f80000 0x00080000>;
  69. read-only;
  70. };
  71. };
  72. nand@2,0 {
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. compatible = "fsl,elbc-fcm-nand";
  76. reg = <0x2 0x0 0x40000>;
  77. u-boot@0 {
  78. reg = <0x0 0x02000000>;
  79. read-only;
  80. };
  81. jffs2@2000000 {
  82. reg = <0x02000000 0x10000000>;
  83. };
  84. ramdisk@12000000 {
  85. reg = <0x12000000 0x08000000>;
  86. read-only;
  87. };
  88. kernel@1a000000 {
  89. reg = <0x1a000000 0x04000000>;
  90. };
  91. dtb@1e000000 {
  92. reg = <0x1e000000 0x01000000>;
  93. read-only;
  94. };
  95. empty@1f000000 {
  96. reg = <0x1f000000 0x21000000>;
  97. };
  98. };
  99. nand@4,0 {
  100. compatible = "fsl,elbc-fcm-nand";
  101. reg = <0x4 0x0 0x40000>;
  102. };
  103. nand@5,0 {
  104. compatible = "fsl,elbc-fcm-nand";
  105. reg = <0x5 0x0 0x40000>;
  106. };
  107. nand@6,0 {
  108. compatible = "fsl,elbc-fcm-nand";
  109. reg = <0x6 0x0 0x40000>;
  110. };
  111. };
  112. soc@ffe00000 {
  113. usb@22000 {
  114. phy_type = "ulpi";
  115. };
  116. mdio@24520 {
  117. phy0: ethernet-phy@0 {
  118. interrupt-parent = <&mpic>;
  119. interrupts = <3 1>;
  120. reg = <0x0>;
  121. };
  122. phy1: ethernet-phy@1 {
  123. interrupt-parent = <&mpic>;
  124. interrupts = <3 1>;
  125. reg = <0x1>;
  126. };
  127. phy2: ethernet-phy@2 {
  128. interrupt-parent = <&mpic>;
  129. interrupts = <3 1>;
  130. reg = <0x2>;
  131. };
  132. tbi0: tbi-phy@11 {
  133. reg = <0x11>;
  134. device_type = "tbi-phy";
  135. };
  136. };
  137. mdio@25520 {
  138. tbi1: tbi-phy@11 {
  139. reg = <0x11>;
  140. device_type = "tbi-phy";
  141. };
  142. };
  143. mdio@26520 {
  144. tbi2: tbi-phy@11 {
  145. reg = <0x11>;
  146. device_type = "tbi-phy";
  147. };
  148. };
  149. ptp_clock@24E00 {
  150. compatible = "fsl,etsec-ptp";
  151. reg = <0x24E00 0xB0>;
  152. interrupts = <68 2 69 2 70 2>;
  153. interrupt-parent = < &mpic >;
  154. fsl,tclk-period = <5>;
  155. fsl,tmr-prsc = <200>;
  156. fsl,tmr-add = <0xCCCCCCCD>;
  157. fsl,tmr-fiper1 = <0x3B9AC9FB>;
  158. fsl,tmr-fiper2 = <0x0001869B>;
  159. fsl,max-adj = <249999999>;
  160. };
  161. enet0: ethernet@24000 {
  162. tbi-handle = <&tbi0>;
  163. phy-handle = <&phy0>;
  164. phy-connection-type = "rgmii-id";
  165. };
  166. enet1: ethernet@25000 {
  167. tbi-handle = <&tbi1>;
  168. phy-handle = <&phy1>;
  169. phy-connection-type = "rgmii-id";
  170. };
  171. enet2: ethernet@26000 {
  172. tbi-handle = <&tbi2>;
  173. phy-handle = <&phy2>;
  174. phy-connection-type = "rgmii-id";
  175. };
  176. msi@41600 {
  177. compatible = "fsl,mpic-msi";
  178. };
  179. };
  180. pci0: pcie@ffe08000 {
  181. ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  182. 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  183. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  184. interrupt-map = <
  185. /* IDSEL 0x0 */
  186. 0000 0x0 0x0 0x1 &mpic 0x8 0x1
  187. 0000 0x0 0x0 0x2 &mpic 0x9 0x1
  188. 0000 0x0 0x0 0x3 &mpic 0xa 0x1
  189. 0000 0x0 0x0 0x4 &mpic 0xb 0x1
  190. >;
  191. pcie@0 {
  192. reg = <0x0 0x0 0x0 0x0 0x0>;
  193. #size-cells = <2>;
  194. #address-cells = <3>;
  195. device_type = "pci";
  196. ranges = <0x2000000 0x0 0x80000000
  197. 0x2000000 0x0 0x80000000
  198. 0x0 0x20000000
  199. 0x1000000 0x0 0x0
  200. 0x1000000 0x0 0x0
  201. 0x0 0x10000>;
  202. };
  203. };
  204. pci1: pcie@ffe09000 {
  205. ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  206. 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  207. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  208. interrupt-map = <
  209. // IDSEL 0x11 func 0 - PCI slot 1
  210. 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
  211. 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
  212. // IDSEL 0x11 func 1 - PCI slot 1
  213. 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
  214. 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
  215. // IDSEL 0x11 func 2 - PCI slot 1
  216. 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
  217. 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
  218. // IDSEL 0x11 func 3 - PCI slot 1
  219. 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
  220. 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
  221. // IDSEL 0x11 func 4 - PCI slot 1
  222. 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
  223. 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
  224. // IDSEL 0x11 func 5 - PCI slot 1
  225. 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
  226. 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
  227. // IDSEL 0x11 func 6 - PCI slot 1
  228. 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
  229. 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
  230. // IDSEL 0x11 func 7 - PCI slot 1
  231. 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
  232. 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
  233. // IDSEL 0x1d Audio
  234. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  235. // IDSEL 0x1e Legacy
  236. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  237. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  238. // IDSEL 0x1f IDE/SATA
  239. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  240. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  241. >;
  242. pcie@0 {
  243. reg = <0x0 0x0 0x0 0x0 0x0>;
  244. #size-cells = <2>;
  245. #address-cells = <3>;
  246. device_type = "pci";
  247. ranges = <0x2000000 0x0 0xa0000000
  248. 0x2000000 0x0 0xa0000000
  249. 0x0 0x20000000
  250. 0x1000000 0x0 0x0
  251. 0x1000000 0x0 0x0
  252. 0x0 0x10000>;
  253. uli1575@0 {
  254. reg = <0x0 0x0 0x0 0x0 0x0>;
  255. #size-cells = <2>;
  256. #address-cells = <3>;
  257. ranges = <0x2000000 0x0 0xa0000000
  258. 0x2000000 0x0 0xa0000000
  259. 0x0 0x20000000
  260. 0x1000000 0x0 0x0
  261. 0x1000000 0x0 0x0
  262. 0x0 0x10000>;
  263. isa@1e {
  264. device_type = "isa";
  265. #interrupt-cells = <2>;
  266. #size-cells = <1>;
  267. #address-cells = <2>;
  268. reg = <0xf000 0x0 0x0 0x0 0x0>;
  269. ranges = <0x1 0x0 0x1000000 0x0 0x0
  270. 0x1000>;
  271. interrupt-parent = <&i8259>;
  272. i8259: interrupt-controller@20 {
  273. reg = <0x1 0x20 0x2
  274. 0x1 0xa0 0x2
  275. 0x1 0x4d0 0x2>;
  276. interrupt-controller;
  277. device_type = "interrupt-controller";
  278. #address-cells = <0>;
  279. #interrupt-cells = <2>;
  280. compatible = "chrp,iic";
  281. interrupts = <4 1>;
  282. interrupt-parent = <&mpic>;
  283. };
  284. i8042@60 {
  285. #size-cells = <0>;
  286. #address-cells = <1>;
  287. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  288. interrupts = <1 3 12 3>;
  289. interrupt-parent =
  290. <&i8259>;
  291. keyboard@0 {
  292. reg = <0x0>;
  293. compatible = "pnpPNP,303";
  294. };
  295. mouse@1 {
  296. reg = <0x1>;
  297. compatible = "pnpPNP,f03";
  298. };
  299. };
  300. rtc@70 {
  301. compatible = "pnpPNP,b00";
  302. reg = <0x1 0x70 0x2>;
  303. };
  304. gpio@400 {
  305. reg = <0x1 0x400 0x80>;
  306. };
  307. };
  308. };
  309. };
  310. };
  311. pci2: pcie@ffe0a000 {
  312. ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
  313. 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
  314. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  315. interrupt-map = <
  316. /* IDSEL 0x0 */
  317. 0000 0x0 0x0 0x1 &mpic 0x0 0x1
  318. 0000 0x0 0x0 0x2 &mpic 0x1 0x1
  319. 0000 0x0 0x0 0x3 &mpic 0x2 0x1
  320. 0000 0x0 0x0 0x4 &mpic 0x3 0x1
  321. >;
  322. pcie@0 {
  323. reg = <0x0 0x0 0x0 0x0 0x0>;
  324. #size-cells = <2>;
  325. #address-cells = <3>;
  326. device_type = "pci";
  327. ranges = <0x2000000 0x0 0xc0000000
  328. 0x2000000 0x0 0xc0000000
  329. 0x0 0x20000000
  330. 0x1000000 0x0 0x0
  331. 0x1000000 0x0 0x0
  332. 0x0 0x10000>;
  333. };
  334. };
  335. };