mpc834x_mds.dts 9.8 KB

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  1. /*
  2. * MPC8349E MDS Device Tree Source
  3. *
  4. * Copyright 2005, 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMDS";
  14. compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>; // 256MB at 0
  43. };
  44. bcsr@e2400000 {
  45. compatible = "fsl,mpc8349mds-bcsr";
  46. reg = <0xe2400000 0x8000>;
  47. };
  48. soc8349@e0000000 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. device_type = "soc";
  52. compatible = "simple-bus";
  53. ranges = <0x0 0xe0000000 0x00100000>;
  54. reg = <0xe0000000 0x00000200>;
  55. bus-frequency = <0>;
  56. wdt@200 {
  57. device_type = "watchdog";
  58. compatible = "mpc83xx_wdt";
  59. reg = <0x200 0x100>;
  60. };
  61. i2c@3000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. cell-index = <0>;
  65. compatible = "fsl-i2c";
  66. reg = <0x3000 0x100>;
  67. interrupts = <14 0x8>;
  68. interrupt-parent = <&ipic>;
  69. dfsrr;
  70. rtc@68 {
  71. compatible = "dallas,ds1374";
  72. reg = <0x68>;
  73. };
  74. };
  75. i2c@3100 {
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. cell-index = <1>;
  79. compatible = "fsl-i2c";
  80. reg = <0x3100 0x100>;
  81. interrupts = <15 0x8>;
  82. interrupt-parent = <&ipic>;
  83. dfsrr;
  84. };
  85. spi@7000 {
  86. cell-index = <0>;
  87. compatible = "fsl,spi";
  88. reg = <0x7000 0x1000>;
  89. interrupts = <16 0x8>;
  90. interrupt-parent = <&ipic>;
  91. mode = "cpu";
  92. };
  93. dma@82a8 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  97. reg = <0x82a8 4>;
  98. ranges = <0 0x8100 0x1a8>;
  99. interrupt-parent = <&ipic>;
  100. interrupts = <71 8>;
  101. cell-index = <0>;
  102. dma-channel@0 {
  103. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  104. reg = <0 0x80>;
  105. cell-index = <0>;
  106. interrupt-parent = <&ipic>;
  107. interrupts = <71 8>;
  108. };
  109. dma-channel@80 {
  110. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  111. reg = <0x80 0x80>;
  112. cell-index = <1>;
  113. interrupt-parent = <&ipic>;
  114. interrupts = <71 8>;
  115. };
  116. dma-channel@100 {
  117. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  118. reg = <0x100 0x80>;
  119. cell-index = <2>;
  120. interrupt-parent = <&ipic>;
  121. interrupts = <71 8>;
  122. };
  123. dma-channel@180 {
  124. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  125. reg = <0x180 0x28>;
  126. cell-index = <3>;
  127. interrupt-parent = <&ipic>;
  128. interrupts = <71 8>;
  129. };
  130. };
  131. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  132. /* port = 0 or 1 */
  133. usb@22000 {
  134. compatible = "fsl-usb2-mph";
  135. reg = <0x22000 0x1000>;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. interrupt-parent = <&ipic>;
  139. interrupts = <39 0x8>;
  140. phy_type = "ulpi";
  141. port0;
  142. };
  143. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  144. usb@23000 {
  145. compatible = "fsl-usb2-dr";
  146. reg = <0x23000 0x1000>;
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. interrupt-parent = <&ipic>;
  150. interrupts = <38 0x8>;
  151. dr_mode = "otg";
  152. phy_type = "ulpi";
  153. };
  154. enet0: ethernet@24000 {
  155. #address-cells = <1>;
  156. #size-cells = <1>;
  157. cell-index = <0>;
  158. device_type = "network";
  159. model = "TSEC";
  160. compatible = "gianfar";
  161. reg = <0x24000 0x1000>;
  162. ranges = <0x0 0x24000 0x1000>;
  163. local-mac-address = [ 00 00 00 00 00 00 ];
  164. interrupts = <32 0x8 33 0x8 34 0x8>;
  165. interrupt-parent = <&ipic>;
  166. tbi-handle = <&tbi0>;
  167. phy-handle = <&phy0>;
  168. linux,network-index = <0>;
  169. mdio@520 {
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. compatible = "fsl,gianfar-mdio";
  173. reg = <0x520 0x20>;
  174. phy0: ethernet-phy@0 {
  175. interrupt-parent = <&ipic>;
  176. interrupts = <17 0x8>;
  177. reg = <0x0>;
  178. device_type = "ethernet-phy";
  179. };
  180. phy1: ethernet-phy@1 {
  181. interrupt-parent = <&ipic>;
  182. interrupts = <18 0x8>;
  183. reg = <0x1>;
  184. device_type = "ethernet-phy";
  185. };
  186. tbi0: tbi-phy@11 {
  187. reg = <0x11>;
  188. device_type = "tbi-phy";
  189. };
  190. };
  191. };
  192. enet1: ethernet@25000 {
  193. #address-cells = <1>;
  194. #size-cells = <1>;
  195. cell-index = <1>;
  196. device_type = "network";
  197. model = "TSEC";
  198. compatible = "gianfar";
  199. reg = <0x25000 0x1000>;
  200. ranges = <0x0 0x25000 0x1000>;
  201. local-mac-address = [ 00 00 00 00 00 00 ];
  202. interrupts = <35 0x8 36 0x8 37 0x8>;
  203. interrupt-parent = <&ipic>;
  204. tbi-handle = <&tbi1>;
  205. phy-handle = <&phy1>;
  206. linux,network-index = <1>;
  207. mdio@520 {
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. compatible = "fsl,gianfar-tbi";
  211. reg = <0x520 0x20>;
  212. tbi1: tbi-phy@11 {
  213. reg = <0x11>;
  214. device_type = "tbi-phy";
  215. };
  216. };
  217. };
  218. serial0: serial@4500 {
  219. cell-index = <0>;
  220. device_type = "serial";
  221. compatible = "ns16550";
  222. reg = <0x4500 0x100>;
  223. clock-frequency = <0>;
  224. interrupts = <9 0x8>;
  225. interrupt-parent = <&ipic>;
  226. };
  227. serial1: serial@4600 {
  228. cell-index = <1>;
  229. device_type = "serial";
  230. compatible = "ns16550";
  231. reg = <0x4600 0x100>;
  232. clock-frequency = <0>;
  233. interrupts = <10 0x8>;
  234. interrupt-parent = <&ipic>;
  235. };
  236. crypto@30000 {
  237. compatible = "fsl,sec2.0";
  238. reg = <0x30000 0x10000>;
  239. interrupts = <11 0x8>;
  240. interrupt-parent = <&ipic>;
  241. fsl,num-channels = <4>;
  242. fsl,channel-fifo-len = <24>;
  243. fsl,exec-units-mask = <0x7e>;
  244. fsl,descriptor-types-mask = <0x01010ebf>;
  245. };
  246. /* IPIC
  247. * interrupts cell = <intr #, sense>
  248. * sense values match linux IORESOURCE_IRQ_* defines:
  249. * sense == 8: Level, low assertion
  250. * sense == 2: Edge, high-to-low change
  251. */
  252. ipic: pic@700 {
  253. interrupt-controller;
  254. #address-cells = <0>;
  255. #interrupt-cells = <2>;
  256. reg = <0x700 0x100>;
  257. device_type = "ipic";
  258. };
  259. };
  260. pci0: pci@e0008500 {
  261. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  262. interrupt-map = <
  263. /* IDSEL 0x11 */
  264. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  265. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  266. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  267. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  268. /* IDSEL 0x12 */
  269. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  270. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  271. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  272. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  273. /* IDSEL 0x13 */
  274. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  275. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  276. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  277. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  278. /* IDSEL 0x15 */
  279. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  280. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  281. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  282. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  283. /* IDSEL 0x16 */
  284. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  285. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  286. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  287. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  288. /* IDSEL 0x17 */
  289. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  290. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  291. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  292. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  293. /* IDSEL 0x18 */
  294. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  295. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  296. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  297. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  298. interrupt-parent = <&ipic>;
  299. interrupts = <66 0x8>;
  300. bus-range = <0 0>;
  301. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  302. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  303. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  304. clock-frequency = <66666666>;
  305. #interrupt-cells = <1>;
  306. #size-cells = <2>;
  307. #address-cells = <3>;
  308. reg = <0xe0008500 0x100 /* internal registers */
  309. 0xe0008300 0x8>; /* config space access registers */
  310. compatible = "fsl,mpc8349-pci";
  311. device_type = "pci";
  312. };
  313. pci1: pci@e0008600 {
  314. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  315. interrupt-map = <
  316. /* IDSEL 0x11 */
  317. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  318. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  319. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  320. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  321. /* IDSEL 0x12 */
  322. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  323. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  324. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  325. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  326. /* IDSEL 0x13 */
  327. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  328. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  329. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  330. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  331. /* IDSEL 0x15 */
  332. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  333. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  334. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  335. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  336. /* IDSEL 0x16 */
  337. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  338. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  339. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  340. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  341. /* IDSEL 0x17 */
  342. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  343. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  344. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  345. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  346. /* IDSEL 0x18 */
  347. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  348. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  349. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  350. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  351. interrupt-parent = <&ipic>;
  352. interrupts = <67 0x8>;
  353. bus-range = <0 0>;
  354. ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  355. 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  356. 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
  357. clock-frequency = <66666666>;
  358. #interrupt-cells = <1>;
  359. #size-cells = <2>;
  360. #address-cells = <3>;
  361. reg = <0xe0008600 0x100 /* internal registers */
  362. 0xe0008380 0x8>; /* config space access registers */
  363. compatible = "fsl,mpc8349-pci";
  364. device_type = "pci";
  365. };
  366. };