irq.c 6.0 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License as published by the
  4. * Free Software Foundation; either version 2 of the License, or (at your
  5. * option) any later version.
  6. *
  7. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  8. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  10. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  11. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  12. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  13. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  14. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  15. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  16. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * Copyright 2002 MontaVista Software Inc.
  23. * Author: MontaVista Software, Inc.
  24. * stevel@mvista.com or source@mvista.com
  25. */
  26. #include <linux/bitops.h>
  27. #include <linux/errno.h>
  28. #include <linux/init.h>
  29. #include <linux/io.h>
  30. #include <linux/kernel_stat.h>
  31. #include <linux/module.h>
  32. #include <linux/signal.h>
  33. #include <linux/sched.h>
  34. #include <linux/types.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/ioport.h>
  37. #include <linux/timex.h>
  38. #include <linux/random.h>
  39. #include <linux/delay.h>
  40. #include <asm/bootinfo.h>
  41. #include <asm/time.h>
  42. #include <asm/mipsregs.h>
  43. #include <asm/system.h>
  44. #include <asm/mach-rc32434/irq.h>
  45. #include <asm/mach-rc32434/gpio.h>
  46. struct intr_group {
  47. u32 mask; /* mask of valid bits in pending/mask registers */
  48. volatile u32 *base_addr;
  49. };
  50. #define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
  51. #if (NR_IRQS < RC32434_NR_IRQS)
  52. #error Too little irqs defined. Did you override <asm/irq.h> ?
  53. #endif
  54. static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
  55. {
  56. .mask = 0x0000efff,
  57. .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
  58. {
  59. .mask = 0x00001fff,
  60. .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
  61. {
  62. .mask = 0x00000007,
  63. .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
  64. {
  65. .mask = 0x0003ffff,
  66. .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
  67. {
  68. .mask = 0xffffffff,
  69. .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
  70. };
  71. #define READ_PEND(base) (*(base))
  72. #define READ_MASK(base) (*(base + 2))
  73. #define WRITE_MASK(base, val) (*(base + 2) = (val))
  74. static inline int irq_to_group(unsigned int irq_nr)
  75. {
  76. return (irq_nr - GROUP0_IRQ_BASE) >> 5;
  77. }
  78. static inline int group_to_ip(unsigned int group)
  79. {
  80. return group + 2;
  81. }
  82. static inline void enable_local_irq(unsigned int ip)
  83. {
  84. int ipnum = 0x100 << ip;
  85. set_c0_status(ipnum);
  86. }
  87. static inline void disable_local_irq(unsigned int ip)
  88. {
  89. int ipnum = 0x100 << ip;
  90. clear_c0_status(ipnum);
  91. }
  92. static inline void ack_local_irq(unsigned int ip)
  93. {
  94. int ipnum = 0x100 << ip;
  95. clear_c0_cause(ipnum);
  96. }
  97. static void rb532_enable_irq(struct irq_data *d)
  98. {
  99. unsigned int group, intr_bit, irq_nr = d->irq;
  100. int ip = irq_nr - GROUP0_IRQ_BASE;
  101. volatile unsigned int *addr;
  102. if (ip < 0)
  103. enable_local_irq(irq_nr);
  104. else {
  105. group = ip >> 5;
  106. ip &= (1 << 5) - 1;
  107. intr_bit = 1 << ip;
  108. enable_local_irq(group_to_ip(group));
  109. addr = intr_group[group].base_addr;
  110. WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
  111. }
  112. }
  113. static void rb532_disable_irq(struct irq_data *d)
  114. {
  115. unsigned int group, intr_bit, mask, irq_nr = d->irq;
  116. int ip = irq_nr - GROUP0_IRQ_BASE;
  117. volatile unsigned int *addr;
  118. if (ip < 0) {
  119. disable_local_irq(irq_nr);
  120. } else {
  121. group = ip >> 5;
  122. ip &= (1 << 5) - 1;
  123. intr_bit = 1 << ip;
  124. addr = intr_group[group].base_addr;
  125. mask = READ_MASK(addr);
  126. mask |= intr_bit;
  127. WRITE_MASK(addr, mask);
  128. /* There is a maximum of 14 GPIO interrupts */
  129. if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
  130. rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
  131. /*
  132. * if there are no more interrupts enabled in this
  133. * group, disable corresponding IP
  134. */
  135. if (mask == intr_group[group].mask)
  136. disable_local_irq(group_to_ip(group));
  137. }
  138. }
  139. static void rb532_mask_and_ack_irq(struct irq_data *d)
  140. {
  141. rb532_disable_irq(d);
  142. ack_local_irq(group_to_ip(irq_to_group(d->irq)));
  143. }
  144. static int rb532_set_type(struct irq_data *d, unsigned type)
  145. {
  146. int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
  147. int group = irq_to_group(d->irq);
  148. if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
  149. return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
  150. switch (type) {
  151. case IRQ_TYPE_LEVEL_HIGH:
  152. rb532_gpio_set_ilevel(1, gpio);
  153. break;
  154. case IRQ_TYPE_LEVEL_LOW:
  155. rb532_gpio_set_ilevel(0, gpio);
  156. break;
  157. default:
  158. return -EINVAL;
  159. }
  160. return 0;
  161. }
  162. static struct irq_chip rc32434_irq_type = {
  163. .name = "RB532",
  164. .irq_ack = rb532_disable_irq,
  165. .irq_mask = rb532_disable_irq,
  166. .irq_mask_ack = rb532_mask_and_ack_irq,
  167. .irq_unmask = rb532_enable_irq,
  168. .irq_set_type = rb532_set_type,
  169. };
  170. void __init arch_init_irq(void)
  171. {
  172. int i;
  173. pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
  174. for (i = 0; i < RC32434_NR_IRQS; i++)
  175. irq_set_chip_and_handler(i, &rc32434_irq_type,
  176. handle_level_irq);
  177. }
  178. /* Main Interrupt dispatcher */
  179. asmlinkage void plat_irq_dispatch(void)
  180. {
  181. unsigned int ip, pend, group;
  182. volatile unsigned int *addr;
  183. unsigned int cp0_cause = read_c0_cause() & read_c0_status();
  184. if (cp0_cause & CAUSEF_IP7) {
  185. do_IRQ(7);
  186. } else {
  187. ip = (cp0_cause & 0x7c00);
  188. if (ip) {
  189. group = 21 + (fls(ip) - 32);
  190. addr = intr_group[group].base_addr;
  191. pend = READ_PEND(addr);
  192. pend &= ~READ_MASK(addr); /* only unmasked interrupts */
  193. pend = 39 + (fls(pend) - 32);
  194. do_IRQ((group << 5) + pend);
  195. }
  196. }
  197. }