bios.c 2.9 KB

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  1. #include <linux/pci.h>
  2. #include <linux/kernel.h>
  3. #include <arch/hwregs/intr_vect.h>
  4. void __devinit pcibios_fixup_bus(struct pci_bus *b)
  5. {
  6. }
  7. char * __devinit pcibios_setup(char *str)
  8. {
  9. return NULL;
  10. }
  11. void pcibios_set_master(struct pci_dev *dev)
  12. {
  13. u8 lat;
  14. pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
  15. printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
  16. pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
  17. }
  18. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  19. enum pci_mmap_state mmap_state, int write_combine)
  20. {
  21. unsigned long prot;
  22. /* Leave vm_pgoff as-is, the PCI space address is the physical
  23. * address on this platform.
  24. */
  25. prot = pgprot_val(vma->vm_page_prot);
  26. vma->vm_page_prot = __pgprot(prot);
  27. /* Write-combine setting is ignored, it is changed via the mtrr
  28. * interfaces on this platform.
  29. */
  30. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  31. vma->vm_end - vma->vm_start,
  32. vma->vm_page_prot))
  33. return -EAGAIN;
  34. return 0;
  35. }
  36. resource_size_t
  37. pcibios_align_resource(void *data, const struct resource *res,
  38. resource_size_t size, resource_size_t align)
  39. {
  40. resource_size_t start = res->start;
  41. if ((res->flags & IORESOURCE_IO) && (start & 0x300))
  42. start = (start + 0x3ff) & ~0x3ff;
  43. return start;
  44. }
  45. int pcibios_enable_resources(struct pci_dev *dev, int mask)
  46. {
  47. u16 cmd, old_cmd;
  48. int idx;
  49. struct resource *r;
  50. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  51. old_cmd = cmd;
  52. for(idx=0; idx<6; idx++) {
  53. /* Only set up the requested stuff */
  54. if (!(mask & (1<<idx)))
  55. continue;
  56. r = &dev->resource[idx];
  57. if (!r->start && r->end) {
  58. printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
  59. return -EINVAL;
  60. }
  61. if (r->flags & IORESOURCE_IO)
  62. cmd |= PCI_COMMAND_IO;
  63. if (r->flags & IORESOURCE_MEM)
  64. cmd |= PCI_COMMAND_MEMORY;
  65. }
  66. if (dev->resource[PCI_ROM_RESOURCE].start)
  67. cmd |= PCI_COMMAND_MEMORY;
  68. if (cmd != old_cmd) {
  69. printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
  70. pci_write_config_word(dev, PCI_COMMAND, cmd);
  71. }
  72. return 0;
  73. }
  74. int pcibios_enable_irq(struct pci_dev *dev)
  75. {
  76. dev->irq = EXT_INTR_VECT;
  77. return 0;
  78. }
  79. int pcibios_enable_device(struct pci_dev *dev, int mask)
  80. {
  81. int err;
  82. if ((err = pcibios_enable_resources(dev, mask)) < 0)
  83. return err;
  84. if (!dev->msi_enabled)
  85. pcibios_enable_irq(dev);
  86. return 0;
  87. }
  88. int pcibios_assign_resources(void)
  89. {
  90. struct pci_dev *dev = NULL;
  91. int idx;
  92. struct resource *r;
  93. while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
  94. int class = dev->class >> 8;
  95. /* Don't touch classless devices and host bridges */
  96. if (!class || class == PCI_CLASS_BRIDGE_HOST)
  97. continue;
  98. for(idx=0; idx<6; idx++) {
  99. r = &dev->resource[idx];
  100. if (!r->start && r->end)
  101. pci_assign_resource(dev, idx);
  102. }
  103. }
  104. return 0;
  105. }
  106. EXPORT_SYMBOL(pcibios_assign_resources);