sys_eb64p.c 5.6 KB

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  1. /*
  2. * linux/arch/alpha/kernel/sys_eb64p.c
  3. *
  4. * Copyright (C) 1995 David A Rusling
  5. * Copyright (C) 1996 Jay A Estabrook
  6. * Copyright (C) 1998, 1999 Richard Henderson
  7. *
  8. * Code supporting the EB64+ and EB66.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/mm.h>
  13. #include <linux/sched.h>
  14. #include <linux/pci.h>
  15. #include <linux/init.h>
  16. #include <linux/bitops.h>
  17. #include <asm/ptrace.h>
  18. #include <asm/system.h>
  19. #include <asm/dma.h>
  20. #include <asm/irq.h>
  21. #include <asm/mmu_context.h>
  22. #include <asm/io.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/core_apecs.h>
  25. #include <asm/core_lca.h>
  26. #include <asm/hwrpb.h>
  27. #include <asm/tlbflush.h>
  28. #include "proto.h"
  29. #include "irq_impl.h"
  30. #include "pci_impl.h"
  31. #include "machvec_impl.h"
  32. /* Note mask bit is true for DISABLED irqs. */
  33. static unsigned int cached_irq_mask = -1;
  34. static inline void
  35. eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
  36. {
  37. outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26));
  38. }
  39. static inline void
  40. eb64p_enable_irq(struct irq_data *d)
  41. {
  42. eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
  43. }
  44. static void
  45. eb64p_disable_irq(struct irq_data *d)
  46. {
  47. eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
  48. }
  49. static struct irq_chip eb64p_irq_type = {
  50. .name = "EB64P",
  51. .irq_unmask = eb64p_enable_irq,
  52. .irq_mask = eb64p_disable_irq,
  53. .irq_mask_ack = eb64p_disable_irq,
  54. };
  55. static void
  56. eb64p_device_interrupt(unsigned long vector)
  57. {
  58. unsigned long pld;
  59. unsigned int i;
  60. /* Read the interrupt summary registers */
  61. pld = inb(0x26) | (inb(0x27) << 8);
  62. /*
  63. * Now, for every possible bit set, work through
  64. * them and call the appropriate interrupt handler.
  65. */
  66. while (pld) {
  67. i = ffz(~pld);
  68. pld &= pld - 1; /* clear least bit set */
  69. if (i == 5) {
  70. isa_device_interrupt(vector);
  71. } else {
  72. handle_irq(16 + i);
  73. }
  74. }
  75. }
  76. static void __init
  77. eb64p_init_irq(void)
  78. {
  79. long i;
  80. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
  81. /*
  82. * CABRIO SRM may not set variation correctly, so here we test
  83. * the high word of the interrupt summary register for the RAZ
  84. * bits, and hope that a true EB64+ would read all ones...
  85. */
  86. if (inw(0x806) != 0xffff) {
  87. extern struct alpha_machine_vector cabriolet_mv;
  88. printk("Detected Cabriolet: correcting HWRPB.\n");
  89. hwrpb->sys_variation |= 2L << 10;
  90. hwrpb_update_checksum(hwrpb);
  91. alpha_mv = cabriolet_mv;
  92. alpha_mv.init_irq();
  93. return;
  94. }
  95. #endif /* GENERIC */
  96. outb(0xff, 0x26);
  97. outb(0xff, 0x27);
  98. init_i8259a_irqs();
  99. for (i = 16; i < 32; ++i) {
  100. irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
  101. irq_set_status_flags(i, IRQ_LEVEL);
  102. }
  103. common_init_isa_dma();
  104. setup_irq(16+5, &isa_cascade_irqaction);
  105. }
  106. /*
  107. * PCI Fixup configuration.
  108. *
  109. * There are two 8 bit external summary registers as follows:
  110. *
  111. * Summary @ 0x26:
  112. * Bit Meaning
  113. * 0 Interrupt Line A from slot 0
  114. * 1 Interrupt Line A from slot 1
  115. * 2 Interrupt Line B from slot 0
  116. * 3 Interrupt Line B from slot 1
  117. * 4 Interrupt Line C from slot 0
  118. * 5 Interrupt line from the two ISA PICs
  119. * 6 Tulip
  120. * 7 NCR SCSI
  121. *
  122. * Summary @ 0x27
  123. * Bit Meaning
  124. * 0 Interrupt Line C from slot 1
  125. * 1 Interrupt Line D from slot 0
  126. * 2 Interrupt Line D from slot 1
  127. * 3 RAZ
  128. * 4 RAZ
  129. * 5 RAZ
  130. * 6 RAZ
  131. * 7 RAZ
  132. *
  133. * The device to slot mapping looks like:
  134. *
  135. * Slot Device
  136. * 5 NCR SCSI controller
  137. * 6 PCI on board slot 0
  138. * 7 PCI on board slot 1
  139. * 8 Intel SIO PCI-ISA bridge chip
  140. * 9 Tulip - DECchip 21040 Ethernet controller
  141. *
  142. *
  143. * This two layered interrupt approach means that we allocate IRQ 16 and
  144. * above for PCI interrupts. The IRQ relates to which bit the interrupt
  145. * comes in on. This makes interrupt processing much easier.
  146. */
  147. static int __init
  148. eb64p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  149. {
  150. static char irq_tab[5][5] __initdata = {
  151. /*INT INTA INTB INTC INTD */
  152. {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
  153. {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
  154. {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
  155. { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
  156. {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
  157. };
  158. const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
  159. return COMMON_TABLE_LOOKUP;
  160. }
  161. /*
  162. * The System Vector
  163. */
  164. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P)
  165. struct alpha_machine_vector eb64p_mv __initmv = {
  166. .vector_name = "EB64+",
  167. DO_EV4_MMU,
  168. DO_DEFAULT_RTC,
  169. DO_APECS_IO,
  170. .machine_check = apecs_machine_check,
  171. .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
  172. .min_io_address = DEFAULT_IO_BASE,
  173. .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
  174. .nr_irqs = 32,
  175. .device_interrupt = eb64p_device_interrupt,
  176. .init_arch = apecs_init_arch,
  177. .init_irq = eb64p_init_irq,
  178. .init_rtc = common_init_rtc,
  179. .init_pci = common_init_pci,
  180. .kill_arch = NULL,
  181. .pci_map_irq = eb64p_map_irq,
  182. .pci_swizzle = common_swizzle,
  183. };
  184. ALIAS_MV(eb64p)
  185. #endif
  186. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66)
  187. struct alpha_machine_vector eb66_mv __initmv = {
  188. .vector_name = "EB66",
  189. DO_EV4_MMU,
  190. DO_DEFAULT_RTC,
  191. DO_LCA_IO,
  192. .machine_check = lca_machine_check,
  193. .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
  194. .min_io_address = DEFAULT_IO_BASE,
  195. .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
  196. .nr_irqs = 32,
  197. .device_interrupt = eb64p_device_interrupt,
  198. .init_arch = lca_init_arch,
  199. .init_irq = eb64p_init_irq,
  200. .init_rtc = common_init_rtc,
  201. .init_pci = common_init_pci,
  202. .pci_map_irq = eb64p_map_irq,
  203. .pci_swizzle = common_swizzle,
  204. };
  205. ALIAS_MV(eb66)
  206. #endif