uni/afd/ex3/verilog/top.v

`include "tmr.v"

module top #(parameter CYCLES_SEC = 100_000_000) (
	input clk,
	input reset,
	input [2 : 0] apply,
	input [2 : 0] inject,
	input [2 : 0] mode,
	output [1 : 0] led
);

wire reset_n = ~reset;
wire select;
wire fault;

assign led = {~select, select};

tmr #(.CYCLES_SEC (CYCLES_SEC)) tmr_inst (
	.clk(clk),
	.reset_n(reset_n),
	.apply(apply),
	.inject(inject),
	.mode(mode),
	.select(select),
	.fault(fault)
);

endmodule