\documentclass{beamer}

\usetheme{Pittsburgh}
\usecolortheme{rose}

\usepackage[backend=bibtex,style=ieee]{biblatex}
\usepackage{tabularx}
\usepackage{xcolor}
\usepackage{minted}
\usemintedstyle{manni}

\addtobeamertemplate{navigation symbols}{}{%
    \usebeamerfont{footline}%
    \usebeamercolor[fg]{footline}%
    \hspace{1em}%
    \insertframenumber/\inserttotalframenumber
}

\newcommand*\ruleline[1]{\par\noindent\raisebox{.8ex}{\makebox[\linewidth]{\hrulefill\hspace{1ex}\raisebox{-.8ex}{#1}\hspace{1ex}\hrulefill}}}

% color macros
\definecolor{BrickRed}{HTML}{B6321C}
\definecolor{OliveGreen}{HTML}{3C8031}
\definecolor{MidnightBlue}{HTML}{006795}
\definecolor{RoyalBlue}{HTML}{0091DC}
\newcommand{\red}[1]{\textcolor{BrickRed}{#1} }
\newcommand{\green}[1]{\textcolor{OliveGreen}{#1} }
\newcommand{\blue}[1]{\textcolor{MidnightBlue}{#1} }
\newcommand{\royalblue}[1]{\textcolor{RoyalBlue}{#1} }

\title[fpgas] % (optional, only for long titles)
{System-Level Design Languages}
\subtitle{}
\author[C. Töpfl, N. Tremurici]
{C.~Töpfl, N.~Tremurici}%\inst{1}}
\institute[Universities Here and There] % (optional)
{
  %\inst{1}%
  Institute of Computer Engineering\newline
  TU Wien
}
\date[2023] % (optional)
{HW/SW Codesign VU, 2023}
\subject{Computer Engineering}

\usepackage{filecontents}
\begin{filecontents*}{\jobname.bib}
@ARTICLE{nane2016,
  author={Nane and Razvan and Sima and Vlad-Mihai and Pilato and Christian and Choi and Jongsok and Fort and Blair and Canis and Andrew and Chen and Yu Ting and Hsiao and Hsuan and Brown and Stephen and Ferrandi and Fabrizio and Anderson and Jason and Bertels and Koen},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title={A Survey and Evaluation of FPGA High-Level Synthesis Tools},
  year={2016},
  volume={35},
  number={10},
  pages={1591-1604},
  doi={10.1109/TCAD.2015.2513673}
}
@ARTICLE{lahti2019,
  author={Lahti and Sakari and Sjövall and Panu and Vanne and Jarno and Hämäläinen and Timo D.},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title={Are We There Yet? A Study on the State of High-Level Synthesis},
  year={2019},
  volume={38},
  number={5},
  pages={898-911},
  doi={10.1109/TCAD.2018.2834439}}@ARTICLE{8356004,
  author={Lahti and Sakari and Sjövall and Panu and Vanne and Jarno and Hämäläinen and Timo D.},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title={Are We There Yet? A Study on the State of High-Level Synthesis},
  year={2019},
  volume={38},
  number={5},
  pages={898-911},
  doi={10.1109/TCAD.2018.2834439}
}
@ARTICLE{schafer2020,
  author={Schafer and Benjamin Carrion and Wang and Zi},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title={High-Level Synthesis Design Space Exploration: Past, Present, and Future},
  year={2020},
  volume={39},
  number={10},
  pages={2628-2639},
  doi={10.1109/TCAD.2019.2943570}
}
@book{hwsw-codesign-book,
   title =     {Hardware/Software Co-Design: Principles and Practice},
   author =    {Daniel D. Gajski and Jianwen Zhu and Rainer Dömer (auth.) and Jørgen Staunstrup and Wayne Wolf (eds.)},
   publisher = {Springer US},
   year =      {1997},
   series =    {},
   edition =   {1},
   volume =    {},
}
@book{esl-book,
   title =     {ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon)},
   author =    {Grant Martin and Brian Bailey and Andrew Piziali},
   publisher = {Morgan Kaufmann},
   year =      {2007},
   series =    {},
   edition =   {},
   volume =    {},
}
@misc{intel-hls-course,
   title =     {Introduction to High-Level Synthesis (Part 1 of 7)},
   author =    {Intel},
   year =      {2017},
   url =       {https://learning.intel.com/developer/learn/courses/240/introduction-to-high-level-synthesis-part-1-of-7},
}
@misc{intel-hls-videos,
   title =     {Introduction to High-Level Synthesis (Part 1 of 7)},
   author =    {Intel},
   year =      {2017},
   url =       {https://youtube.com/watch?v=nYbw9k7KNJ4},
}
@misc{systemc,
   title =     {SystemC - The language for System-level design, modeling and verification},
   author =    {systemc.org},
   year =      {2023},
   url =       {https://systemc.org/overview/systemc/},
}
@misc{learn-systemc,
   title =     {Learn SystemC by examples - Process: Method},
   author =    {learnsystemc.com},
   year =      {2020},
   url =       {https://learnsystemc.com/basic/method},
}
\end{filecontents*}
\bibliography{\jobname.bib}

\begin{document}
    \begin{frame}\titlepage\end{frame}
    \begin{frame}
        \frametitle{Outline}
        \ruleline{1 | What are System-Level Design Languages?}
        \newline
        \ruleline{2 | What can System-Level Design Languages do?}
        \newline
        \ruleline{3 | SystemC}
        \newline
        \ruleline{4 | Intel HLS}
        \newline
    \end{frame}
    \begin{frame}
        \frametitle{Implementing a HW/SW System}
        In general, what do we specify using language?
        \begin{table}[H]
            \centering
            \begin{tabularx}{\textwidth}{c|cc}
                & HW & SW \\ \hline
                System instantiation & HW to generate & SW as program to \\
                & & store in memory \\ \hline
                Test model & Testbench model & Testing program \\
                & simulation & trace \\ \hline
                Verification model & State space model & State space model \\
                & (signals) & (logical) \\
            \end{tabularx}
            \caption{HW/SW specification comparison}
        \end{table}
    \end{frame}
    \begin{frame}
        \frametitle{Implementing a HW/SW System}
        Some basic follow-up questions:
        \begin{itemize}
            \item{What is the HW/SW partition?}
            \item{How many languages do we use?}
            \item{Can a single language specify all parts of the system?}
            \item{What should the language have?}
            \item{What sort of languages are available?}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Example (Without Codesign)}
        A methodology that uses no codesign might use:
        \begin{table}[H]
            \centering
            \begin{tabularx}{\textwidth}{c|cc}
                & HW & SW \\ \hline
                System instantiation & \red{VHDL} & \green{C} \\ \hline
                Test model & \red{VHDL} & \green{C} \\ \hline
                Verification model & \blue{temporal logic} & \blue{temporal logic} \\
            \end{tabularx}
            \caption{HW/SW example}
        \end{table}
    \end{frame}
    \begin{frame}
        \frametitle{Using Codesign}
        An idealized methodology that uses codesign might use:
        \begin{table}[H]
            \centering
            \begin{tabularx}{\textwidth}{c|cc}
                & HW & SW \\ \hline
                System instantiation & \red{system language} & \red{system language} \\ \hline
                Test model & \green{testing language} & \green{testing language} \\ \hline
                Verification model & \blue{verification language} & \blue{verification language} \\
            \end{tabularx}
            \caption{HW/SW Codesign}
        \end{table}
    \end{frame}
    \begin{frame}
        \frametitle{All the Languages \cite{hwsw-codesign-book}}
        Categorization from 1997 according to \cite{hwsw-codesign-book}[ch. 7.4]:
        \begin{enumerate}
            \item{VLSI system design}
            \item{protocol specification}
            \item{reactive system design (Petri nets)}
            \item{programming languages}
            \item{parallel programming languages}
            \item{functional programming}
        \end{enumerate}
    \end{frame}
    %\begin{frame}
        %\frametitle{Language Differences \cite{hwsw-codesign-book}}
        %\begin{columns}[c]
            %\begin{column}{\textwidth}
                %\begin{figure}[ht]
                    %\begin{center}
                        %\includegraphics[width=1\columnwidth,keepaspectratio]{graphics/language-expressivity.png}
                    %\end{center}
                %\end{figure}
            %\end{column}
        %\end{columns}
    %\end{frame}
    \begin{frame}
        \frametitle{Language Differences \cite{hwsw-codesign-book}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=.9\columnwidth,keepaspectratio]{graphics/axes-of-language.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{A More Modern Classification \cite{nane2016}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/nane2016-classification.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        %\frametitle{A More Modern Classification \cite{nane2016}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=\columnwidth,height=.89\textheight,keepaspectratio]{graphics/nane2016-table.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Defining System-Level Design Languages}
        \begin{itemize}
            \item{What is a \textit{system-level design language}?}
        \end{itemize}
        Toward a definition: a \textit{system-level design language} is a language used to specify a \textit{system-level design}
        \newline
        \newline
        \begin{itemize}
            \item{What is \textit{system-level design}?}
        \end{itemize}
        Defined in \cite{esl-book} as ``the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner, while meeting necessary constraints.''
    \end{frame}
    \begin{frame}
        \frametitle{Defining System-Level Design Languages}
        \begin{itemize}
            \item{a related cousin: \textit{high-level synthesis}}
        \end{itemize}
        As described in \cite{nane2016}: ``HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality.''
    \end{frame}
    \begin{frame}
        \frametitle{Compilers}
        \begin{itemize}
            \item{languages for \textit{system-level design} and \textit{high-level synthesis} are analogous to their respective \textit{tools}}
            \item{the \textit{tools} consist of compilers}
            \begin{itemize}
                \item{built using custom/new compilers}
                \item{built by extending existing compilers (e.g. targeting GCC, LLVM, ...)}
            \end{itemize}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{1 | Operation Chaining}
        \begin{itemize}
            \item{eliminating registers by scheduling combinatorial operators within the same cycle}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{2 | Bitwidth Analysis}
        \begin{itemize}
            \item{reducing the number of bits required by datapath operators}
            \item{significant optimization, impacts all non-functional requirements (performance, area and power!)}
            \item{important note: can not always be automated (requires specific knowledge)}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{3 | Memory Space Allocation}
        \begin{itemize}
            \item{exploiting distributed block RAMs}
            \item{example: partitioning and mapping data structures onto dedicated BRAMs for low cost memory access}
            \item{note: a scheduler could schedule multiple memory operations in a single cycle}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{4 | Loop Optimizations}
        \begin{itemize}
            \item{exploiting loop-level parallelism: loop pipelining}
            \item{allow loop iterations to start before the completion of its predecessor}
            \item{significant optimization for compute-intensive loops}
            \item{note: limited by data dependencies}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{5 | Hardware Resource Library}
        \begin{itemize}
            \item{optimize for target hardware}
            \begin{itemize}
                \item{using dedicated resources like DSP elements}
                \item{using specific optimizations (like shifts for multiplications/divisions)}
            \end{itemize}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{6 | Speculation and Code Motion}
        \begin{itemize}
            \item{execute operations in anticipation of conditions that control their execution}
            \item{useful if functional units are available and otherwise unused}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{7 | Exploiting Spatial Parallelism}
        \begin{itemize}
            \item{instantiate units that run concurrently by analyzing data dependencies and loop-level parallelism}
            \item{important note: difficult to automatically extract coarse-grained parallelism}
            \item{some tools use OpenMP (C parallelization framework) for better support}
        \end{itemize}
    \end{frame}
    \begin{frame}
        \frametitle{Optimization techniques \cite{nane2016}}
        \ruleline{8 | If-Conversion}
        \begin{itemize}
            \item{schedule in parallel disjoin execution paths created by selective statements (e.g. \texttt{if})}
            \item{better pipelining because control dependencies are removed}
            \item{note: balanced number of cycles for execution paths necessary (otherwise harmful!)}
            \item{note: automated use of this optimization becomes a decision problem (to use or not to use), but some promising results}
        \end{itemize}
    \end{frame}
    \begin{frame}{Language dimensions | Usability}
        \begin{itemize}
            \item[-] learning a new language / new concepts
            \item[-] documentation
            \item[+] often based on usually known languages (e.g. C++)
            \item[+] faster than other methods
            \item[+] higher productivity for developer
        \end{itemize}
    \end{frame}
    \begin{frame}{Why even bother with System-Level Design Languages?}
        \begin{itemize}
            \item faster development time
            \item shorter time to market
            \item higher possible productivity
        \end{itemize}
    \end{frame}
    \begin{frame}{Why even bother with System-Level Design Languages? | Time \cite{lahti2019}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/HLS_time_comparison.JPG}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}{Why even bother with System-Level Design Languages? | Time \cite{lahti2019}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/Developement_Time.JPG}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}{Why even bother with System-Level Design Languages? | Performance \cite{lahti2019}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=0.8\columnwidth,keepaspectratio]{graphics/performance_comparison.JPG}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}{SW/HW Automatic Partitioning}
        \begin{itemize}
            \item no automatic partitioning of SW and HW directly in the design languages
            \item tools which can be used separately
        \end{itemize}
    \end{frame}
    \begin{frame}{Evaluation}
        \begin{itemize}
            \item faster development time
            \item shorter time to market
            \item verification
            \item everything is combined in one language
            \item for highly optimised system RTL design is recommended
        \end{itemize}
    \end{frame}
    \begin{frame}{Use in the Industry}
        \begin{itemize}
            \item Intel/AMD
            \item ``viable method for prototyping and designs with short time to market''
        \end{itemize}
    \end{frame}
    \begin{frame}
        %\frametitle{A More Modern Classification \cite{nane2016}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=\columnwidth,height=.89\textheight,keepaspectratio]{graphics/nane2016-table.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{SystemC \cite{systemc}}
        \begin{itemize}
            \item based on C++
            \item class libraries
            \item design, automatic partitioning and verification on different abstraction levels
            \item even allows for analog and mixed signal uses
        \end{itemize}
    \end{frame}
    \begin{frame}{SystemC | Structure \cite{systemc}}
        \begin{columns}[c]
            \begin{column}{\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/systemc.JPG}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR header}
        \begin{minted}{c++}
#include "systemc.h"

SC_MODULE(FIR16)
{
 // port definition
 sc_in <bool> clk;
 sc_in <bool> rst; 
 sc_in <sc_uint<32>> x;
 sc_out<sc_uint<32>> y;
        \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR header}
        \begin{minted}{c++}
 // data and function members
 void fir16();
 sc_uint<32> input, output;
 
 sc_signal<sc_uint<32>> d1, d2, ..., d14, d15;
 
 sc_uint<32> b0, b1, ..., b14, b15;
        \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR header}
        \begin{minted}{c++}
 // constructor
 SC_CTOR(FIR16)
 {
  // sensitivity list
  SC_CTHREAD(fir16, clk.pos());
  // positive edge trigger clock 
  reset_signal_is(rst, false); 
  // synchronous active-low
 }
        \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR reset}
        \begin{minted}{c++}
#include "FIR16.h"

void FIR16::fir16()
{
 // reset
 b0  = 0x00000F0F;
        ...
 b15 = 0x00000F0F;
 
 d1  = 0;
 ...
 d15  = 0;
        \end{minted}
    \end{frame}
\begin{frame}[containsverbatim]{SystemC | Example FIR shift}
        \begin{minted}{c++}

 //computation
 while(1)
 {
  wait();
  input = x.read();
  
  d1  = input;
  d2  = d1;
  ...
  d14 = d13;
  d15 = d14;
  \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR output}
        \begin{minted}{c++}
output = b0  * input 
+ b1  * d1.read()
+ b2  * d2.read()
+ b3  * d3.read()
...
+ b13 * d13.read()
+ b14 * d14.read()
+ b15 * d15.read();
  
y.write(output);
  \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{SystemC | Example FIR output}
        \begin{minted}{c++}
sc_time clkPrd(5, SC_NS); // 200MHz
sc_time clkDly( 0, SC_NS);
sc_clock clk("clk", clkPrd, 0.50, clkDly, true);

// instantiation
FIR16 fir16_1("fir16_1");
fir16_1.clk(clk);
fir16_1.rst(rst);
fir16_1.x(x);
fir16_1.y(y);
  \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{C | Example FIR shift}
        \begin{minted}{c}
float fir_filter(float input) {
    float output = 0.0;

    // shift input samples in the buffer
    for (int i = NUM_TAPS - 1; i > 0; i--) {
        input_signal[i] = input_signal[i - 1];
    }
 \end{minted}
    \end{frame}
    \begin{frame}[containsverbatim]{C | Example FIR convolution}
        \begin{minted}{c}
    // store the latest input sample in the buffer
    input_signal[0] = input;

    // perform the convolution
    for (int i = 0; i < NUM_TAPS; i++) {
        output += fir_coeffs[i] * input_signal[i];
    }

    return output;
}
  \end{minted}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-use-model.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    %\begin{frame}
        %\frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        %\begin{columns}[c]
            %\begin{column}{1.18\textwidth}
                %\begin{figure}[ht]
                    %\begin{center}
                        %\includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-compiler.png}
                    %\end{center}
                %\end{figure}
            %\end{column}
        %\end{columns}
    %\end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-compiler-usage.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-procedure.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-fir-filter-example.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-optimizations-loops.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-mem-1-double-pump.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-mem-2-local-replication.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-mem-3-coalescing.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-mem-4-banking.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}
        \frametitle{Intel HLS \cite{intel-hls-course}\cite{intel-hls-videos}}
        \begin{columns}[c]
            \begin{column}{1.18\textwidth}
                \begin{figure}[ht]
                    \begin{center}
                        \includegraphics[width=1\columnwidth,keepaspectratio]{graphics/hls-mem-5-port-sharing.png}
                    \end{center}
                \end{figure}
            \end{column}
        \end{columns}
    \end{frame}
    \begin{frame}[allowframebreaks]
        \frametitle{Bibliography}
        \printbibliography
    \end{frame}
    \begin{frame}[c]
        \ruleline{\textbf{Thank you!}}
        \newline
        \ruleline{Further questions?}
    \end{frame}
\end{document}
