-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


library lpm;
use lpm.lpm_components.all;

entity ci_mul is
	port (
		clk   : in std_logic;
		clk_en : in std_logic;
		reset : in std_logic;
		
		dataa : in std_logic_vector(31 downto 0); 
		datab : in std_logic_vector(31 downto 0);
		result : out std_logic_vector(31 downto 0)
	);
end entity;


architecture arch of ci_mul is 

	constant ZERO : std_logic_vector(31 downto 0) := (others => '0');

	signal reg_result      : std_logic_vector(31 downto 0) := ZERO;
	signal reg_next_result : std_logic_vector(31 downto 0);

	signal mul : std_logic_vector(63 downto 0) := (others => '0');

begin

        mul <= std_logic_vector(signed(dataa) * signed(datab));
	reg_next_result <= mul(47 downto 16);
	result <= reg_result;

	sync : process(clk, clk_en, reset)
	begin
		if reset = '1' then
			-- reset values
			reg_result <= ZERO;
		elsif clk_en = '1' and rising_edge(clk) then
			-- register transfer
			reg_result <= reg_next_result;
		end if;
	end process;

end architecture;
