# TCL File Generated by Component Editor 22.1
# Wed Oct 18 13:47:01 CEST 2023
# DO NOT MODIFY


# 
# ci_div "ci_div" v1.0
#  2023.10.18.13:47:01
# custom instruction divider
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module ci_div
# 
set_module_property DESCRIPTION "custom instruction divider"
set_module_property NAME ci_div
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME ci_div
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ci_div
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file ci_div.vhd VHDL PATH ../vhdl/div/ci_div.vhd TOP_LEVEL_FILE


# 
# parameters
# 


# 
# display items
# 


# 
# connection point ci_div
# 
add_interface ci_div nios_custom_instruction end
set_interface_property ci_div clockCycle 0
set_interface_property ci_div operands 2
set_interface_property ci_div ENABLED true
set_interface_property ci_div EXPORT_OF ""
set_interface_property ci_div PORT_NAME_MAP ""
set_interface_property ci_div CMSIS_SVD_VARIABLES ""
set_interface_property ci_div SVD_ADDRESS_GROUP ""

add_interface_port ci_div clk_en clk_en Input 1
add_interface_port ci_div dataa dataa Input 32
add_interface_port ci_div datab datab Input 32
add_interface_port ci_div result result Output 32
add_interface_port ci_div start start Input 1
add_interface_port ci_div done done Output 1
add_interface_port ci_div n n Input 1
add_interface_port ci_div reset reset Input 1
add_interface_port ci_div clk clk Input 1

