
# HW/SW Codesign - Get-To-Know Task Assignment

The following file/directory structure shows how the template is organized and where you are expected to place your files.

```
template
  |- quartus
     |- Makefile
     |- .qpf .qsf              Quartus project files
     |- .qsys                  The Platform Designer system
     |- .sdc                   Timing constraint file
     |- .tcl                   Platform Designer custom components (not created yet)
  |- software
     |- Makefile
     |- settings.bsp           board support package (BSP) specification (not created yet)
     |- src                    Your C code goes here
     |- bsp                    The BSP (automatically created)
     |- build                  Object/ELF file(s) of your appliaction (automatically created)
     |- checker                Scripts to check your solution
  |- vhdl                      Your VHDL code goes here
  |- gettoknow.pdf             The assignment document
  |- coding_guidelines.pdf     The VHDL coding and design guidelines used in this course
  |- Makefile                  Master Makefile (for the submission)
  |- rpa_shell.py              Python tool to access the Remote-Lab.
  |- README.md                 This file
```

## Hardware Project

The Quaruts project and related files are located in the `quartus` directory.
The makefile in this directory provides the following targets:

| Target | Description |
|--|--|
| `all` (default) | Runs the Quartus synthesis (which also includes the Platform Designer system generation) without starting the GUI|
| `download` | Downloads the SOF file to the board |
| `quartus_gui` | Starts the Quartus GUI and loads the Quartus project |
| `qsys_gui` | Starts the Platform Designer GUI and loads the Platform Designer project |
| `clean` | Deletes all files which are generated during the build process. REMEMBER to clean your project before submission!! |

Hence, to e.g., download the generated SOF file to the FPGA board, run the following command inside the `quartus` folder.

```
make download
```

Note that you can also start the synthesis and download process using the Quartus GUI.

The VHDL code of your submission MUST be placed in the `vhdl` directory. 
Don't rename any of the existing files!

## Software Project

The software project is located in the `software` directory.
The makefile in this folder builds the BSP- and application project and provides the following targets:

| Target | Description |
|--|--|
| `all` (default) | Creates the BSP and application makefiles (if necessary) and builds the ELF file. No download is performed. |
| `edit_bsp` | Opens the BSP settings GUI editor (for settings.bsp) |
| `download` | Downloads the ELF file to the Nios II processor |
| `term` | Starts the nios2-terminal (JTAG UART) and connects to the Nios II processor |
| `run` | Builds and downloads the ELF file and starts nios2-terminal (JTAG UART). Combination of `download` and `term`. |
| `clean` | Deletes all files, which are generated during the build process. REMEMBER to clean your project before submission!! |
| `check` | Tests your implementation (correctness and speed)|

In order to make it easier to work with the Remote-Lab the makefile also provides special targets prefixed with the term `remote_`.

| Target | Description |
|--|--|
| `remote_check` | Automatically checks out a computer in the Remote-Lab, uploads the necessary files and runs the checks. |
| `remote_download` | Downloads the ELF file to the Nios system running in the remote lab (i.e., the FPGA must already by programmed, use make `remote_download_sof` for that purpose) |
| `remote_download_sof` | Downloads the SOF file generated by the Quartus synthesis to an FPGA board in the Remote-Lab |
| `remote_term` | Starts the nios2-terminal (JTAG UART) and connects to the Nios II processor running in the Remote-Lab|
| `remote_run` | Combination of `remote_download` and `remote_run` |

For all `remote_*` targets except `remote_check` you must already have an active connection to the Remote-Lab, i.e., `rpa_shell.py` must be running in another shell.

All your C source/header files MUST be placed in the `software/src` directory.
Note that, for the Get-To-Know task you are NOT allowed to create new source files!

## Submission
To create an archive for submission use the master makefile located in the root directory of the repository and use the `submission` target.
This creates a file called `submission.tar.gz`, which you can upload in TUWEL. 

