ddca-ss2021/dd/report_exercise1/report.tex

\documentclass[10pt,a4paper,titlepage,oneside]{article}
\usepackage{LabProtocol}

\exercise{Exercise I}

% enter your data here
\authors{
	Norbert Tremurici, Matr. Nr. 11907086 \par
	{\small e11907086@student.tuwien.ac.at} \par
}


\begin{document}

\maketitle


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\Task{Structural modeling}

\begin{qa}{Create a screenshot showing the top level design in the RTL netlist viewer!}
	\begin{figure}[h!]
		\centering
		\includegraphics[width=1.0\linewidth]{img/netlist.pdf}
		\caption{RTL netlist viewer screenshot}
	\end{figure}
\end{qa}
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\Task{Seven Segment Display I}

\begin{qa}{Are the \textsf{hex*} signals high or low-active? Explain what that means!}
When choosing how to represent logical high and logical low values, signals can be defined to be active low or active high. For active high signals, a '1' encodes a logical high and a '0' encodes a logical low. For active low signals, the opposite applies, a '0' encodes a logical high and a '1' encodes a logial low.

It can be inferred from the manual of the specific device used in our lab course that the seven segment display is low-active. This means that only segments that have a '0' signal will light up. This is also why the "empty" seven segment display is assigned a bit vector "1111111".
\end{qa}
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\Task{Behavioral Simulation}

\begin{qa}{SRAM write access}

\begin{center}
\begin{tabular}{lc}
	\hline
	Question & Answer \\
	\hline\hline
	Absoulte (simulation) time of the first write access$^{*}$ & 1710 ns \\
	Accessed SRAM addresses (first 4 write operations)         & 0x00 0x01 0x02 0x02 \\
	Measure the SRAM timing parameter $t_{WC}$ (see datasheet) & 60 ns\\\hline
\end{tabular}

\footnotesize{$^{*}$ Take the point in time where the address for the write operation is applied.}
\end{center}

\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/timing-parameter.png}
	\caption{Simulation showing the first 4 write operations to the SRAM with markers indicating the SRAM timing parameter $t_{WC}$}
\end{figure}

\end{qa}
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\begin{qa}{Serial port interface of the LCD driver IC (Consult the LCD manual to answer the following questions)}

\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/sclk-signal.png}
	\caption{Screenshot showing the data transmission on the serial port interface of the LCD driver IC with markers indicating the period of the $sclk$ signal.}
\end{figure}

\begin{center}
\begin{tabular}{lc}
	\hline
	Question                                               & Answer \\\hline\hline
	What frequency did you measure for the $sclk$ signal?  & 1.3 MHz \\
	What is the maximum allowed frequency?                 & 2 MHz \\\hline
\end{tabular}
\end{center}

Hint: Should your simulation show ``zero-width spikes'' on some signal traces, you can simply ignore them.
\end{qa}
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\begin{qa}{What is the purpose of the transmission on the serial interface to the LCD? Explain what is transmitted and why!}
	The serial interface is used to transmit image values in order to make image data accessible to the FPGA.
\end{qa}
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\Task{Postlayout Simulation}
\begin{qa}{Use a postlayout simualtion to measure the different delays on the \textsf{hex\{6-7\}} signals.}

\begin{center}
\begin{tabular}{lc}
	\hline
	Interval                                                  & Time \\ \hline\hline
	Duration between the first and the last bit toggling      & 3121 ps \\
	Time between the last active clock edge and stabilization & 13170 ps \\\hline
\end{tabular}
\end{center}

\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/hex6to7.png}
	\caption{Screenshot showing the interval measurements with markers}
\end{figure}

\end{qa}
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\Task{Testbench Design}

\begin{qa}{PRNG simulation}

\begin{center}
\begin{tabular}{ll}
\hline\hline
My matriculation number             & 11907086 \\
My matriculation number modulo $15$ & 11 \\
$n_a$                               & 192 \\
$n_b$                               & 207 \\
Minimum period                      & 7 \\
Maximum period                      & 64897 \\\hline
\end{tabular}
\end{center}

\end{qa}
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\begin{qa}{Bonus Task: SRAM reads}
\begin{figure}[h!]
	\centering
	%\includegraphics[width=1.0\linewidth]{path}
	\dummyimage
	\caption{Simulation showing a read operation performed by the \textsf{lcd\_graphics\_controller}}
\end{figure}
\end{qa}
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\Task{N64 Controller}

\begin{qa}{Simulation of two complete button state transmission frames}

\begin{center}
\begin{tabular}{ll}
\hline\hline
My matriculation number                   &  11907086 \\
My matriculation number modulo $2^{16}$   & 0xB00E \\
$b_0$: hex, ({A},{B},{Select},{Start},{$\uparrow$},{$\downarrow$},{$\leftarrow$},{$\rightarrow$})  & 0xB0 (1,0,1,1,0,0,0,0) \\
$b_1$: hex, ({A},{B},{Select},{Start},{$\uparrow$},{$\downarrow$},{$\leftarrow$},{$\rightarrow$})  & 0x0E (0,0,0,0,1,1,1,0) \\\hline
\end{tabular}
\end{center}

\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/nes-transmissions.png}
	\caption{Screenshot(s) showing both the transmissions with markers showing the clock period of $nes\_clk$}
\end{figure}

\end{qa}
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\begin{qa}{Analyse the resource usage of your \textsf{nes\_controller}!}
\centering
\begin{tabular}{l|ll}
	\hline
		                   & LC Combinationals & LC Registers        \\ \hline\hline 
	Absolute number            & 54                & 32                  \\
	\% of whole design         & 1.26              & 1.33                \\ 
	\% of whole FPGA resources & 0.05              & 0.03                \\ \hline
\end{tabular}
\end{qa}
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\Task{Seven Segment Display II}

\begin{qa}{Include the state graph of the state machine you designed and briefly explain how it works.}

The FSM starts at state \texttt{IDLE}. During this state it is determined (by comparing the \texttt{player\_points} and \texttt{points\_lock} signals) whether a point jump of 25 of more points occured and this value is propagated via the signal high-active \texttt{blink}. Besides determining the value of \texttt{blink}, the signal \texttt{player\_points} is monitored for change, so long as \texttt{player\_points} does not change the state does not change. Once it does however, the next state is determined by how many \texttt{player\_points} there are: if our four segments cannot display the current score, we automatically visit state \texttt{DISPLAY\_OVERFLOW}, which renders a special sequence \texttt{----} upon returning to \texttt{IDLE} unconditionally. Note that from the task description it is not clear whether a blink should be possible in this special overflow state, so it was specified that there is no blinking when overflowing.

If there was no overflow, we enter a sequence of counting states \texttt{DISPLAY\_\{0-3\}} that count the digits via subtraction. At the end, depending on the signal \texttt{blink} we choose whether to proceed with state \texttt{WAIT\_NOBLINK} or \texttt{WAIT\_INTERVAL}. The former is an intermediary state to copy the results of the counting process to the seven-segment displays (as the values aren't ready yet during state \texttt{DISPLAY\_1}), the latter initiates a blinking protocol defined by two constants. A cycle count \texttt{BLINK\_INTERVAL} specifies how many clock cycles to wait until blinking and a count \texttt{BLINK\_COUNT} specifies how often to repeat this process. Once this protocol is over, the digits are copied to the seven-segment display one last time before we return to \texttt{IDLE}.

\begin{figure}[h!]
	\centering
	\includegraphics[width=0.75\linewidth]{img/fsm-task7.png}
	\caption{FSM state graph}
\end{figure}

\end{qa}
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\begin{qa}{Seven Segment Display Simulation Screenshot}

\begin{center}
\begin{tabular}{ll}
\hline\hline
My matriculation number                          & 11907086 \\ 
My matriculation number modulo $500$             & 86 \\ 
\textsf{player\_points} value for the testbench  & 1320 \\ \hline
\end{tabular}
\end{center}

\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/ssd-conversion.png}
	\caption{Simulation showing the conversion}
\end{figure}

\end{qa}
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\begin{qa}{Bonus Task: Animation Simulation}
\begin{figure}[h!]
	\centering
	\includegraphics[width=1.0\linewidth]{img/animation.png}
	\caption{Simulation showing all animation steps}
\end{figure}
\end{qa}
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\end{document}