ddca-ss2021/ca/report_exercise4/task3.tex

\begin{table}[htb]
\centering
\caption{Resource usage by entity, including resources used by sub-entities.}
\begin{tabular}{llll}
	\toprule
	                     & LC Combinationals & LC Registers & Memory Bits \\
	\midrule
	Fetch Stage          &78            &16         &     0       \\
	Decode Stage         &1557          &1040       &     0       \\
	-- Register File     &1425          &992        &     0       \\
	Execute Stage        &1234          &153        &     0       \\
	-- ALU               &759           &0          &     0       \\
	Memory Stage         &297           &147        &     0       \\
	-- Memory Unit       &134           &0          &     0       \\
	Write-Back Stage     &105           &89         &     0       \\
	Forwarding Unit      &13            &0          &     0       \\
	Control Unit         &8             &1          &     0       \\
	\cmidrule{1-4}
	Sum                  &5610          &2438       &     0       \\
\bottomrule
\end{tabular}
\end{table}

\begin{qa}
	\question{What is the maximum frequency of your design?}
	\answer{80.59MHz for Slow 1200mV 85C Model}
	\question{Where is the critical path of your design?}
	\answer{WB-stage old\_PC\_register - execute - fwd - alu - aluresult\_mem\_register}
\end{qa}