ddca-ss2021/ca/report_exercise4/task1.tex

\begin{figure}[ht!]
	%\dummyimage
	\includegraphics[width=1.0\linewidth]{./task1-wave.png}
	\caption{Simulation screenshot for Listing~\ref{lst:asmfwd}.}
	\label{fig:sim1}
\end{figure}

Make sure that at least the following signals are visible in
Figure~\ref{fig:sim1}: the program counter in the fetch stage, the
instruction being fetched, the content of registers \texttt{x1} 
and \texttt{x2} as well as the signals \texttt{wraddr},
\texttt{wrdata} and \texttt{regwrite} of the register file.

\begin{lstlisting}[language=,mathescape=false,float=ht,caption={Assembler example with forwarding},label=lst:asmfwd]
        addi x1, x0, 7
        addi x2, x0, 5
        and x1, x2, x1
        nop
        nop
\end{lstlisting}