library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.mem_pkg.all;
use work.core_pkg.all;
use work.op_pkg.all;

entity bp is
	port (
            pc_fetch     : in pc_type;
            instr_packet : in mem_data_type;
            pred_result  : in std_logic;
            pred_valid   : in std_logic;
            
            pc_predicted : out pc_type
	);
end bp;

architecture rtl of bp is
begin
        -- decode instr imm (B type)
	
	opcomp : process(all) 
	begin
            -- 2-bit predictor FSM
            -- output static prediction according to state
            -- take pred results and change state (state update)
	end process;
end architecture;
