library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.mem_pkg.all;
use work.core_pkg.all;
use work.op_pkg.all;

entity muldiv is
	port (
		op   : in  muldiv_op_type;
		A, B : in  data_type;
		R    : out data_type := (others => '0');
	);
end muldiv;

architecture rtl of muldiv is
begin
	
	opcomp : process(all) 
	begin
		Z <= '-';
		case op is
			when MULDIV_NOP =>
			when MULDIV_MUL =>
			when MULDIV_MULH =>
			when MULDIV_MULHSU =>
			when MULDIV_MULHU =>
			when MULDIV_DIV =>
			when MULDIV_DIVU =>
			when MULDIV_REM =>
			when MULDIV_REMU =>
		end case;
	end process;
end architecture;
