# run `make help` for explanation of the important targets!
VCOM_ARGS=-2008 -work work -explicit
VSIM_ARGS=-msgmode both

# The order is important!
VHDL_FILES1 = \
	../math/src/math_pkg.vhd\
	../ram/src/ram_pkg.vhd\
	../ram/src/dp_ram_1c1r1w.vhd\
	../ram/src/fifo_1c1r1w.vhd\
	../lcd_graphics_controller/src/gfx_if_pkg.vhd\
	../gfx_util/src/gfx_util_pkg.vhd\
	../gfx_util/src/gfx_circle.vhd\
	../gfx_util/src/gfx_line.vhd\
	../gfx_util/src/gfx_rect.vhd\
	./src/rasterizer.vhd
VHDL_FILES2 = \
	../math/src/math_pkg.vhd\
	../lcd_graphics_controller/src/gfx_if_pkg.vhd\
	./src/tpg.vhd\
	./src/vbs_graphics_controller_pkg.vhd\
	./src/dac.vhd

TB_FILES1 = \
	./tb/rasterizer_tb.vhd
TB_FILES2 = \
	./tb/dac_tb.vhd

TIME_RESOLUTION = 1ps
TB1 = rasterizer_tb
TB2 = dac_tb

# For the simulation time -all can also be selected. Questa then simulates until no more singal changes occour.
SIM_TIME = -all
WAVE_FILE1 = scripts/wave-rasterizer.do
WAVE_FILE2 = scripts/wave-dac.do

compile1: log1
compile2: log2

log1: $(VHDL_FILES1) $(TB_FILES1)
	rm -f log
	vlib work | tee log
	for i in $(VHDL_FILES1); do \
		vcom $(VCOM_ARGS) $$i | tee -a log;\
	done;
	for i in $(TB_FILES1); do \
		vcom $(VCOM_ARGS) $$i | tee -a log;\
	done;
	@echo "--------------------------------------------------------------"
	@echo "--              Error and Warning Summary                   --"
	@echo "--------------------------------------------------------------"
	@cat log | grep 'Warning\|Error'
	@if [[ $$(grep "Error:" -m 1 log) ]]; then \
		echo "Compilation had errors!" \
		exit 1; \
	fi;

log2: $(VHDL_FILES2) $(TB_FILES2)
	rm -f log
	vlib work | tee log
	for i in $(VHDL_FILES2); do \
		vcom $(VCOM_ARGS) $$i | tee -a log;\
	done;
	for i in $(TB_FILES2); do \
		vcom $(VCOM_ARGS) $$i | tee -a log;\
	done;
	@echo "--------------------------------------------------------------"
	@echo "--              Error and Warning Summary                   --"
	@echo "--------------------------------------------------------------"
	@cat log | grep 'Warning\|Error'
	@if [[ $$(grep "Error:" -m 1 log) ]]; then \
		echo "Compilation had errors!" \
		exit 1; \
	fi;

list_sources1:
	@for i in $(VHDL_FILES1) $(TB_FILES1); do \
		echo $$i;\
	done;

list_sources2:
	@for i in $(VHDL_FILES2) $(TB_FILES2); do \
		echo $$i;\
	done;

sim1: compile1
	vsim -c -do "vsim $(TB1) -t $(TIME_RESOLUTION) $(VSIM_ARGS); run $(SIM_TIME)"

sim2: compile2
	vsim -c -do "vsim $(TB2) -t $(TIME_RESOLUTION) $(VSIM_ARGS); run $(SIM_TIME)"

sim_gui1: compile1
	vsim -do "vsim $(TB1) -t $(TIME_RESOLUTION) $(VSIM_ARGS); do $(WAVE_FILE1); run $(SIM_TIME)"

sim_gui2: compile2
	vsim -do "vsim $(TB2) -t $(TIME_RESOLUTION) $(VSIM_ARGS); do $(WAVE_FILE2); run $(SIM_TIME)"

clean:
	rm -f transcript
	rm -f vsim.wlf
	rm -f log
	rm -fr work

help:
	# available commands are:
	#   make (clean|compile1|compile2|sim1|sim2|sim_gui1|sim_gui2|help)"
	#
	# targets suffixed with 1 target the rasterizer module
	# targets suffixed with 2 target the rasterizer module

.PHONY: clean
.PHONY: compile1
.PHONY: compile2
.PHONY: sim1
.PHONY: sim2
.PHONY: sim_gui1
.PHONY: sim_gui2
.PHONY: help
