altera-freeze-bridge.c 7.0 KB

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  1. /*
  2. * FPGA Freeze Bridge Controller
  3. *
  4. * Copyright (C) 2016 Altera Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/delay.h>
  19. #include <linux/io.h>
  20. #include <linux/kernel.h>
  21. #include <linux/of_device.h>
  22. #include <linux/module.h>
  23. #include <linux/fpga/fpga-bridge.h>
  24. #define FREEZE_CSR_STATUS_OFFSET 0
  25. #define FREEZE_CSR_CTRL_OFFSET 4
  26. #define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
  27. #define FREEZE_CSR_REG_VERSION 12
  28. #define FREEZE_CSR_SUPPORTED_VERSION 2
  29. #define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
  30. #define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
  31. #define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
  32. #define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
  33. #define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
  34. #define FREEZE_BRIDGE_NAME "freeze"
  35. struct altera_freeze_br_data {
  36. struct device *dev;
  37. void __iomem *base_addr;
  38. bool enable;
  39. };
  40. /*
  41. * Poll status until status bit is set or we have a timeout.
  42. */
  43. static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
  44. u32 timeout, u32 req_ack)
  45. {
  46. struct device *dev = priv->dev;
  47. void __iomem *csr_illegal_req_addr = priv->base_addr +
  48. FREEZE_CSR_ILLEGAL_REQ_OFFSET;
  49. u32 status, illegal, ctrl;
  50. int ret = -ETIMEDOUT;
  51. do {
  52. illegal = readl(csr_illegal_req_addr);
  53. if (illegal) {
  54. dev_err(dev, "illegal request detected 0x%x", illegal);
  55. writel(1, csr_illegal_req_addr);
  56. illegal = readl(csr_illegal_req_addr);
  57. if (illegal)
  58. dev_err(dev, "illegal request not cleared 0x%x",
  59. illegal);
  60. ret = -EINVAL;
  61. break;
  62. }
  63. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  64. dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
  65. status &= req_ack;
  66. if (status) {
  67. ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
  68. dev_dbg(dev, "%s request %x acknowledged %x %x\n",
  69. __func__, req_ack, status, ctrl);
  70. ret = 0;
  71. break;
  72. }
  73. udelay(1);
  74. } while (timeout--);
  75. if (ret == -ETIMEDOUT)
  76. dev_err(dev, "%s timeout waiting for 0x%x\n",
  77. __func__, req_ack);
  78. return ret;
  79. }
  80. static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
  81. u32 timeout)
  82. {
  83. struct device *dev = priv->dev;
  84. void __iomem *csr_ctrl_addr = priv->base_addr +
  85. FREEZE_CSR_CTRL_OFFSET;
  86. u32 status;
  87. int ret;
  88. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  89. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  90. if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
  91. dev_dbg(dev, "%s bridge already disabled %d\n",
  92. __func__, status);
  93. return 0;
  94. } else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
  95. dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
  96. return -EINVAL;
  97. }
  98. writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
  99. ret = altera_freeze_br_req_ack(priv, timeout,
  100. FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
  101. if (ret)
  102. writel(0, csr_ctrl_addr);
  103. else
  104. writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
  105. return ret;
  106. }
  107. static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
  108. u32 timeout)
  109. {
  110. struct device *dev = priv->dev;
  111. void __iomem *csr_ctrl_addr = priv->base_addr +
  112. FREEZE_CSR_CTRL_OFFSET;
  113. u32 status;
  114. int ret;
  115. writel(0, csr_ctrl_addr);
  116. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  117. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  118. if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
  119. dev_dbg(dev, "%s bridge already enabled %d\n",
  120. __func__, status);
  121. return 0;
  122. } else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
  123. dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
  124. return -EINVAL;
  125. }
  126. writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
  127. ret = altera_freeze_br_req_ack(priv, timeout,
  128. FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
  129. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  130. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  131. writel(0, csr_ctrl_addr);
  132. return ret;
  133. }
  134. /*
  135. * enable = 1 : allow traffic through the bridge
  136. * enable = 0 : disable traffic through the bridge
  137. */
  138. static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
  139. bool enable)
  140. {
  141. struct altera_freeze_br_data *priv = bridge->priv;
  142. struct fpga_image_info *info = bridge->info;
  143. u32 timeout = 0;
  144. int ret;
  145. if (enable) {
  146. if (info)
  147. timeout = info->enable_timeout_us;
  148. ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
  149. } else {
  150. if (info)
  151. timeout = info->disable_timeout_us;
  152. ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
  153. }
  154. if (!ret)
  155. priv->enable = enable;
  156. return ret;
  157. }
  158. static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
  159. {
  160. struct altera_freeze_br_data *priv = bridge->priv;
  161. return priv->enable;
  162. }
  163. static struct fpga_bridge_ops altera_freeze_br_br_ops = {
  164. .enable_set = altera_freeze_br_enable_set,
  165. .enable_show = altera_freeze_br_enable_show,
  166. };
  167. static const struct of_device_id altera_freeze_br_of_match[] = {
  168. { .compatible = "altr,freeze-bridge-controller", },
  169. {},
  170. };
  171. MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
  172. static int altera_freeze_br_probe(struct platform_device *pdev)
  173. {
  174. struct device *dev = &pdev->dev;
  175. struct device_node *np = pdev->dev.of_node;
  176. struct altera_freeze_br_data *priv;
  177. struct resource *res;
  178. u32 status, revision;
  179. if (!np)
  180. return -ENODEV;
  181. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  182. if (!priv)
  183. return -ENOMEM;
  184. priv->dev = dev;
  185. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  186. priv->base_addr = devm_ioremap_resource(dev, res);
  187. if (IS_ERR(priv->base_addr))
  188. return PTR_ERR(priv->base_addr);
  189. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  190. if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
  191. priv->enable = 1;
  192. revision = readl(priv->base_addr + FREEZE_CSR_REG_VERSION);
  193. if (revision != FREEZE_CSR_SUPPORTED_VERSION)
  194. dev_warn(dev,
  195. "%s Freeze Controller unexpected revision %d != %d\n",
  196. __func__, revision, FREEZE_CSR_SUPPORTED_VERSION);
  197. return fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
  198. &altera_freeze_br_br_ops, priv);
  199. }
  200. static int altera_freeze_br_remove(struct platform_device *pdev)
  201. {
  202. fpga_bridge_unregister(&pdev->dev);
  203. return 0;
  204. }
  205. static struct platform_driver altera_freeze_br_driver = {
  206. .probe = altera_freeze_br_probe,
  207. .remove = altera_freeze_br_remove,
  208. .driver = {
  209. .name = "altera_freeze_br",
  210. .of_match_table = of_match_ptr(altera_freeze_br_of_match),
  211. },
  212. };
  213. module_platform_driver(altera_freeze_br_driver);
  214. MODULE_DESCRIPTION("Altera Freeze Bridge");
  215. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  216. MODULE_LICENSE("GPL v2");