dsp_spos.c 56 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <linux/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/init.h>
  24. #include <linux/slab.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/asoundef.h>
  31. #include "cs46xx.h"
  32. #include "cs46xx_lib.h"
  33. #include "dsp_spos.h"
  34. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  35. struct dsp_scb_descriptor * fg_entry);
  36. static enum wide_opcode wide_opcodes[] = {
  37. WIDE_FOR_BEGIN_LOOP,
  38. WIDE_FOR_BEGIN_LOOP2,
  39. WIDE_COND_GOTO_ADDR,
  40. WIDE_COND_GOTO_CALL,
  41. WIDE_TBEQ_COND_GOTO_ADDR,
  42. WIDE_TBEQ_COND_CALL_ADDR,
  43. WIDE_TBEQ_NCOND_GOTO_ADDR,
  44. WIDE_TBEQ_NCOND_CALL_ADDR,
  45. WIDE_TBEQ_COND_GOTO1_ADDR,
  46. WIDE_TBEQ_COND_CALL1_ADDR,
  47. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  48. WIDE_TBEQ_NCOND_CALL1_ADDR
  49. };
  50. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  51. u32 overlay_begin_address)
  52. {
  53. unsigned int i = 0, j, nreallocated = 0;
  54. u32 hival,loval,address;
  55. u32 mop_operands,mop_type,wide_op;
  56. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  57. if (snd_BUG_ON(size %2))
  58. return -EINVAL;
  59. while (i < size) {
  60. loval = data[i++];
  61. hival = data[i++];
  62. if (ins->code.offset > 0) {
  63. mop_operands = (hival >> 6) & 0x03fff;
  64. mop_type = mop_operands >> 10;
  65. /* check for wide type instruction */
  66. if (mop_type == 0 &&
  67. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  68. (mop_operands & WIDE_INSTR_MASK) != 0) {
  69. wide_op = loval & 0x7f;
  70. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  71. if (wide_opcodes[j] == wide_op) {
  72. /* need to reallocate instruction */
  73. address = (hival & 0x00FFF) << 5;
  74. address |= loval >> 15;
  75. dev_dbg(chip->card->dev,
  76. "handle_wideop[1]: %05x:%05x addr %04x\n",
  77. hival, loval, address);
  78. if ( !(address & 0x8000) ) {
  79. address += (ins->code.offset / 2) - overlay_begin_address;
  80. } else {
  81. dev_dbg(chip->card->dev,
  82. "handle_wideop[1]: ROM symbol not reallocated\n");
  83. }
  84. hival &= 0xFF000;
  85. loval &= 0x07FFF;
  86. hival |= ( (address >> 5) & 0x00FFF);
  87. loval |= ( (address << 15) & 0xF8000);
  88. address = (hival & 0x00FFF) << 5;
  89. address |= loval >> 15;
  90. dev_dbg(chip->card->dev,
  91. "handle_wideop:[2] %05x:%05x addr %04x\n",
  92. hival, loval, address);
  93. nreallocated++;
  94. } /* wide_opcodes[j] == wide_op */
  95. } /* for */
  96. } /* mod_type == 0 ... */
  97. } /* ins->code.offset > 0 */
  98. ins->code.data[ins->code.size++] = loval;
  99. ins->code.data[ins->code.size++] = hival;
  100. }
  101. dev_dbg(chip->card->dev,
  102. "dsp_spos: %d instructions reallocated\n", nreallocated);
  103. return nreallocated;
  104. }
  105. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  106. {
  107. int i;
  108. for (i = 0;i < module->nsegments; ++i) {
  109. if (module->segments[i].segment_type == seg_type) {
  110. return (module->segments + i);
  111. }
  112. }
  113. return NULL;
  114. };
  115. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  116. {
  117. int index = ins->symbol_table.nsymbols,i;
  118. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  119. if (ins->symbol_table.symbols[i].deleted) {
  120. index = i;
  121. break;
  122. }
  123. }
  124. return index;
  125. }
  126. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  127. {
  128. int i;
  129. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  130. if (module->symbol_table.nsymbols > 0) {
  131. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  132. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  133. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  134. }
  135. }
  136. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  137. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  138. dev_err(chip->card->dev,
  139. "dsp_spos: symbol table is full\n");
  140. return -ENOMEM;
  141. }
  142. if (cs46xx_dsp_lookup_symbol(chip,
  143. module->symbol_table.symbols[i].symbol_name,
  144. module->symbol_table.symbols[i].symbol_type) == NULL) {
  145. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  146. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  147. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  148. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  149. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  150. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  151. ins->symbol_table.nsymbols++;
  152. } else {
  153. #if 0
  154. dev_dbg(chip->card->dev,
  155. "dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  156. module->symbol_table.symbols[i].symbol_name); */
  157. #endif
  158. }
  159. }
  160. return 0;
  161. }
  162. static struct dsp_symbol_entry *
  163. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  164. {
  165. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  166. struct dsp_symbol_entry * symbol = NULL;
  167. int index;
  168. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  169. dev_err(chip->card->dev, "dsp_spos: symbol table is full\n");
  170. return NULL;
  171. }
  172. if (cs46xx_dsp_lookup_symbol(chip,
  173. symbol_name,
  174. type) != NULL) {
  175. dev_err(chip->card->dev,
  176. "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  177. return NULL;
  178. }
  179. index = find_free_symbol_index (ins);
  180. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  181. ins->symbol_table.symbols[index].address = address;
  182. ins->symbol_table.symbols[index].symbol_type = type;
  183. ins->symbol_table.symbols[index].module = NULL;
  184. ins->symbol_table.symbols[index].deleted = 0;
  185. symbol = (ins->symbol_table.symbols + index);
  186. if (index > ins->symbol_table.highest_frag_index)
  187. ins->symbol_table.highest_frag_index = index;
  188. if (index == ins->symbol_table.nsymbols)
  189. ins->symbol_table.nsymbols++; /* no frag. in list */
  190. return symbol;
  191. }
  192. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  193. {
  194. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  195. if (ins == NULL)
  196. return NULL;
  197. /* better to use vmalloc for this big table */
  198. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  199. DSP_MAX_SYMBOLS);
  200. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  201. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  202. if (!ins->symbol_table.symbols || !ins->code.data || !ins->modules) {
  203. cs46xx_dsp_spos_destroy(chip);
  204. goto error;
  205. }
  206. ins->symbol_table.nsymbols = 0;
  207. ins->symbol_table.highest_frag_index = 0;
  208. ins->code.offset = 0;
  209. ins->code.size = 0;
  210. ins->nscb = 0;
  211. ins->ntask = 0;
  212. ins->nmodules = 0;
  213. /* default SPDIF input sample rate
  214. to 48000 khz */
  215. ins->spdif_in_sample_rate = 48000;
  216. /* maximize volume */
  217. ins->dac_volume_right = 0x8000;
  218. ins->dac_volume_left = 0x8000;
  219. ins->spdif_input_volume_right = 0x8000;
  220. ins->spdif_input_volume_left = 0x8000;
  221. /* set left and right validity bits and
  222. default channel status */
  223. ins->spdif_csuv_default =
  224. ins->spdif_csuv_stream =
  225. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  226. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  227. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  228. /* left and right validity bits */ (1 << 13) | (1 << 12);
  229. return ins;
  230. error:
  231. kfree(ins->modules);
  232. kfree(ins->code.data);
  233. vfree(ins->symbol_table.symbols);
  234. kfree(ins);
  235. return NULL;
  236. }
  237. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  238. {
  239. int i;
  240. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  241. if (snd_BUG_ON(!ins))
  242. return;
  243. mutex_lock(&chip->spos_mutex);
  244. for (i = 0; i < ins->nscb; ++i) {
  245. if (ins->scbs[i].deleted) continue;
  246. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  247. #ifdef CONFIG_PM_SLEEP
  248. kfree(ins->scbs[i].data);
  249. #endif
  250. }
  251. kfree(ins->code.data);
  252. vfree(ins->symbol_table.symbols);
  253. kfree(ins->modules);
  254. kfree(ins);
  255. mutex_unlock(&chip->spos_mutex);
  256. }
  257. static int dsp_load_parameter(struct snd_cs46xx *chip,
  258. struct dsp_segment_desc *parameter)
  259. {
  260. u32 doffset, dsize;
  261. if (!parameter) {
  262. dev_dbg(chip->card->dev,
  263. "dsp_spos: module got no parameter segment\n");
  264. return 0;
  265. }
  266. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  267. dsize = parameter->size * 4;
  268. dev_dbg(chip->card->dev,
  269. "dsp_spos: downloading parameter data to chip (%08x-%08x)\n",
  270. doffset,doffset + dsize);
  271. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  272. dev_err(chip->card->dev,
  273. "dsp_spos: failed to download parameter data to DSP\n");
  274. return -EINVAL;
  275. }
  276. return 0;
  277. }
  278. static int dsp_load_sample(struct snd_cs46xx *chip,
  279. struct dsp_segment_desc *sample)
  280. {
  281. u32 doffset, dsize;
  282. if (!sample) {
  283. dev_dbg(chip->card->dev,
  284. "dsp_spos: module got no sample segment\n");
  285. return 0;
  286. }
  287. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  288. dsize = sample->size * 4;
  289. dev_dbg(chip->card->dev,
  290. "dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  291. doffset,doffset + dsize);
  292. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  293. dev_err(chip->card->dev,
  294. "dsp_spos: failed to sample data to DSP\n");
  295. return -EINVAL;
  296. }
  297. return 0;
  298. }
  299. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  300. {
  301. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  302. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  303. u32 doffset, dsize;
  304. int err;
  305. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  306. dev_err(chip->card->dev,
  307. "dsp_spos: to many modules loaded into DSP\n");
  308. return -ENOMEM;
  309. }
  310. dev_dbg(chip->card->dev,
  311. "dsp_spos: loading module %s into DSP\n", module->module_name);
  312. if (ins->nmodules == 0) {
  313. dev_dbg(chip->card->dev, "dsp_spos: clearing parameter area\n");
  314. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  315. }
  316. err = dsp_load_parameter(chip, get_segment_desc(module,
  317. SEGTYPE_SP_PARAMETER));
  318. if (err < 0)
  319. return err;
  320. if (ins->nmodules == 0) {
  321. dev_dbg(chip->card->dev, "dsp_spos: clearing sample area\n");
  322. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  323. }
  324. err = dsp_load_sample(chip, get_segment_desc(module,
  325. SEGTYPE_SP_SAMPLE));
  326. if (err < 0)
  327. return err;
  328. if (ins->nmodules == 0) {
  329. dev_dbg(chip->card->dev, "dsp_spos: clearing code area\n");
  330. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  331. }
  332. if (code == NULL) {
  333. dev_dbg(chip->card->dev,
  334. "dsp_spos: module got no code segment\n");
  335. } else {
  336. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  337. dev_err(chip->card->dev,
  338. "dsp_spos: no space available in DSP\n");
  339. return -ENOMEM;
  340. }
  341. module->load_address = ins->code.offset;
  342. module->overlay_begin_address = 0x000;
  343. /* if module has a code segment it must have
  344. symbol table */
  345. if (snd_BUG_ON(!module->symbol_table.symbols))
  346. return -ENOMEM;
  347. if (add_symbols(chip,module)) {
  348. dev_err(chip->card->dev,
  349. "dsp_spos: failed to load symbol table\n");
  350. return -ENOMEM;
  351. }
  352. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  353. dsize = code->size * 4;
  354. dev_dbg(chip->card->dev,
  355. "dsp_spos: downloading code to chip (%08x-%08x)\n",
  356. doffset,doffset + dsize);
  357. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  358. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  359. dev_err(chip->card->dev,
  360. "dsp_spos: failed to download code to DSP\n");
  361. return -EINVAL;
  362. }
  363. ins->code.offset += code->size;
  364. }
  365. /* NOTE: module segments and symbol table must be
  366. statically allocated. Case that module data is
  367. not generated by the ospparser */
  368. ins->modules[ins->nmodules] = *module;
  369. ins->nmodules++;
  370. return 0;
  371. }
  372. struct dsp_symbol_entry *
  373. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  374. {
  375. int i;
  376. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  377. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  378. if (ins->symbol_table.symbols[i].deleted)
  379. continue;
  380. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  381. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  382. return (ins->symbol_table.symbols + i);
  383. }
  384. }
  385. #if 0
  386. dev_err(chip->card->dev, "dsp_spos: symbol <%s> type %02x not found\n",
  387. symbol_name,symbol_type);
  388. #endif
  389. return NULL;
  390. }
  391. #ifdef CONFIG_SND_PROC_FS
  392. static struct dsp_symbol_entry *
  393. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  394. {
  395. int i;
  396. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  397. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  398. if (ins->symbol_table.symbols[i].deleted)
  399. continue;
  400. if (ins->symbol_table.symbols[i].address == address &&
  401. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  402. return (ins->symbol_table.symbols + i);
  403. }
  404. }
  405. return NULL;
  406. }
  407. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  408. struct snd_info_buffer *buffer)
  409. {
  410. struct snd_cs46xx *chip = entry->private_data;
  411. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  412. int i;
  413. snd_iprintf(buffer, "SYMBOLS:\n");
  414. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  415. char *module_str = "system";
  416. if (ins->symbol_table.symbols[i].deleted)
  417. continue;
  418. if (ins->symbol_table.symbols[i].module != NULL) {
  419. module_str = ins->symbol_table.symbols[i].module->module_name;
  420. }
  421. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  422. ins->symbol_table.symbols[i].address,
  423. ins->symbol_table.symbols[i].symbol_type,
  424. ins->symbol_table.symbols[i].symbol_name,
  425. module_str);
  426. }
  427. }
  428. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  429. struct snd_info_buffer *buffer)
  430. {
  431. struct snd_cs46xx *chip = entry->private_data;
  432. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  433. int i,j;
  434. mutex_lock(&chip->spos_mutex);
  435. snd_iprintf(buffer, "MODULES:\n");
  436. for ( i = 0; i < ins->nmodules; ++i ) {
  437. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  438. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  439. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  440. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  441. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  442. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  443. desc->segment_type,desc->offset, desc->size);
  444. }
  445. }
  446. mutex_unlock(&chip->spos_mutex);
  447. }
  448. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  449. struct snd_info_buffer *buffer)
  450. {
  451. struct snd_cs46xx *chip = entry->private_data;
  452. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  453. int i, j, col;
  454. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  455. mutex_lock(&chip->spos_mutex);
  456. snd_iprintf(buffer, "TASK TREES:\n");
  457. for ( i = 0; i < ins->ntask; ++i) {
  458. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  459. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  460. u32 val;
  461. if (col == 4) {
  462. snd_iprintf(buffer,"\n");
  463. col = 0;
  464. }
  465. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  466. snd_iprintf(buffer,"%08x ",val);
  467. }
  468. }
  469. snd_iprintf(buffer,"\n");
  470. mutex_unlock(&chip->spos_mutex);
  471. }
  472. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  473. struct snd_info_buffer *buffer)
  474. {
  475. struct snd_cs46xx *chip = entry->private_data;
  476. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  477. int i;
  478. mutex_lock(&chip->spos_mutex);
  479. snd_iprintf(buffer, "SCB's:\n");
  480. for ( i = 0; i < ins->nscb; ++i) {
  481. if (ins->scbs[i].deleted)
  482. continue;
  483. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  484. if (ins->scbs[i].parent_scb_ptr != NULL) {
  485. snd_iprintf(buffer,"parent [%s:%04x] ",
  486. ins->scbs[i].parent_scb_ptr->scb_name,
  487. ins->scbs[i].parent_scb_ptr->address);
  488. } else snd_iprintf(buffer,"parent [none] ");
  489. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  490. ins->scbs[i].sub_list_ptr->scb_name,
  491. ins->scbs[i].sub_list_ptr->address,
  492. ins->scbs[i].next_scb_ptr->scb_name,
  493. ins->scbs[i].next_scb_ptr->address,
  494. ins->scbs[i].task_entry->symbol_name,
  495. ins->scbs[i].task_entry->address);
  496. }
  497. snd_iprintf(buffer,"\n");
  498. mutex_unlock(&chip->spos_mutex);
  499. }
  500. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  501. struct snd_info_buffer *buffer)
  502. {
  503. struct snd_cs46xx *chip = entry->private_data;
  504. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  505. unsigned int i, col = 0;
  506. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  507. struct dsp_symbol_entry * symbol;
  508. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  509. if (col == 4) {
  510. snd_iprintf(buffer,"\n");
  511. col = 0;
  512. }
  513. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  514. col = 0;
  515. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  516. }
  517. if (col == 0) {
  518. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  519. }
  520. snd_iprintf(buffer,"%08X ",readl(dst + i));
  521. }
  522. }
  523. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  524. struct snd_info_buffer *buffer)
  525. {
  526. struct snd_cs46xx *chip = entry->private_data;
  527. int i,col = 0;
  528. void __iomem *dst = chip->region.idx[2].remap_addr;
  529. snd_iprintf(buffer,"PCMREADER:\n");
  530. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  531. if (col == 4) {
  532. snd_iprintf(buffer,"\n");
  533. col = 0;
  534. }
  535. if (col == 0) {
  536. snd_iprintf(buffer, "%04X ",i);
  537. }
  538. snd_iprintf(buffer,"%08X ",readl(dst + i));
  539. }
  540. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  541. col = 0;
  542. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  543. if (col == 4) {
  544. snd_iprintf(buffer,"\n");
  545. col = 0;
  546. }
  547. if (col == 0) {
  548. snd_iprintf(buffer, "%04X ",i);
  549. }
  550. snd_iprintf(buffer,"%08X ",readl(dst + i));
  551. }
  552. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  553. col = 0;
  554. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  555. if (col == 4) {
  556. snd_iprintf(buffer,"\n");
  557. col = 0;
  558. }
  559. if (col == 0) {
  560. snd_iprintf(buffer, "%04X ",i);
  561. }
  562. snd_iprintf(buffer,"%08X ",readl(dst + i));
  563. }
  564. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  565. col = 0;
  566. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  567. if (col == 4) {
  568. snd_iprintf(buffer,"\n");
  569. col = 0;
  570. }
  571. if (col == 0) {
  572. snd_iprintf(buffer, "%04X ",i);
  573. }
  574. snd_iprintf(buffer,"%08X ",readl(dst + i));
  575. }
  576. snd_iprintf(buffer,"\n...\n");
  577. col = 0;
  578. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  579. if (col == 4) {
  580. snd_iprintf(buffer,"\n");
  581. col = 0;
  582. }
  583. if (col == 0) {
  584. snd_iprintf(buffer, "%04X ",i);
  585. }
  586. snd_iprintf(buffer,"%08X ",readl(dst + i));
  587. }
  588. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  589. col = 0;
  590. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  591. if (col == 4) {
  592. snd_iprintf(buffer,"\n");
  593. col = 0;
  594. }
  595. if (col == 0) {
  596. snd_iprintf(buffer, "%04X ",i);
  597. }
  598. snd_iprintf(buffer,"%08X ",readl(dst + i));
  599. }
  600. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  601. col = 0;
  602. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  603. if (col == 4) {
  604. snd_iprintf(buffer,"\n");
  605. col = 0;
  606. }
  607. if (col == 0) {
  608. snd_iprintf(buffer, "%04X ",i);
  609. }
  610. snd_iprintf(buffer,"%08X ",readl(dst + i));
  611. }
  612. #if 0
  613. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  614. col = 0;
  615. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  616. if (col == 4) {
  617. snd_iprintf(buffer,"\n");
  618. col = 0;
  619. }
  620. if (col == 0) {
  621. snd_iprintf(buffer, "%04X ",i);
  622. }
  623. snd_iprintf(buffer,"%08X ",readl(dst + i));
  624. }
  625. #endif
  626. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  627. col = 0;
  628. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  629. if (col == 4) {
  630. snd_iprintf(buffer,"\n");
  631. col = 0;
  632. }
  633. if (col == 0) {
  634. snd_iprintf(buffer, "%04X ",i);
  635. }
  636. snd_iprintf(buffer,"%08X ",readl(dst + i));
  637. }
  638. snd_iprintf(buffer,"\n");
  639. }
  640. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  641. {
  642. struct snd_info_entry *entry;
  643. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  644. int i;
  645. ins->snd_card = card;
  646. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  647. entry->content = SNDRV_INFO_CONTENT_TEXT;
  648. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  649. if (snd_info_register(entry) < 0) {
  650. snd_info_free_entry(entry);
  651. entry = NULL;
  652. }
  653. }
  654. ins->proc_dsp_dir = entry;
  655. if (!ins->proc_dsp_dir)
  656. return -ENOMEM;
  657. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  658. entry->content = SNDRV_INFO_CONTENT_TEXT;
  659. entry->private_data = chip;
  660. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  661. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  662. if (snd_info_register(entry) < 0) {
  663. snd_info_free_entry(entry);
  664. entry = NULL;
  665. }
  666. }
  667. ins->proc_sym_info_entry = entry;
  668. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  669. entry->content = SNDRV_INFO_CONTENT_TEXT;
  670. entry->private_data = chip;
  671. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  672. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  673. if (snd_info_register(entry) < 0) {
  674. snd_info_free_entry(entry);
  675. entry = NULL;
  676. }
  677. }
  678. ins->proc_modules_info_entry = entry;
  679. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  680. entry->content = SNDRV_INFO_CONTENT_TEXT;
  681. entry->private_data = chip;
  682. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  683. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  684. if (snd_info_register(entry) < 0) {
  685. snd_info_free_entry(entry);
  686. entry = NULL;
  687. }
  688. }
  689. ins->proc_parameter_dump_info_entry = entry;
  690. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  691. entry->content = SNDRV_INFO_CONTENT_TEXT;
  692. entry->private_data = chip;
  693. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  694. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  695. if (snd_info_register(entry) < 0) {
  696. snd_info_free_entry(entry);
  697. entry = NULL;
  698. }
  699. }
  700. ins->proc_sample_dump_info_entry = entry;
  701. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  702. entry->content = SNDRV_INFO_CONTENT_TEXT;
  703. entry->private_data = chip;
  704. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  705. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  706. if (snd_info_register(entry) < 0) {
  707. snd_info_free_entry(entry);
  708. entry = NULL;
  709. }
  710. }
  711. ins->proc_task_info_entry = entry;
  712. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  713. entry->content = SNDRV_INFO_CONTENT_TEXT;
  714. entry->private_data = chip;
  715. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  716. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  717. if (snd_info_register(entry) < 0) {
  718. snd_info_free_entry(entry);
  719. entry = NULL;
  720. }
  721. }
  722. ins->proc_scb_info_entry = entry;
  723. mutex_lock(&chip->spos_mutex);
  724. /* register/update SCB's entries on proc */
  725. for (i = 0; i < ins->nscb; ++i) {
  726. if (ins->scbs[i].deleted) continue;
  727. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  728. }
  729. mutex_unlock(&chip->spos_mutex);
  730. return 0;
  731. }
  732. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  733. {
  734. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  735. int i;
  736. if (!ins)
  737. return 0;
  738. snd_info_free_entry(ins->proc_sym_info_entry);
  739. ins->proc_sym_info_entry = NULL;
  740. snd_info_free_entry(ins->proc_modules_info_entry);
  741. ins->proc_modules_info_entry = NULL;
  742. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  743. ins->proc_parameter_dump_info_entry = NULL;
  744. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  745. ins->proc_sample_dump_info_entry = NULL;
  746. snd_info_free_entry(ins->proc_scb_info_entry);
  747. ins->proc_scb_info_entry = NULL;
  748. snd_info_free_entry(ins->proc_task_info_entry);
  749. ins->proc_task_info_entry = NULL;
  750. mutex_lock(&chip->spos_mutex);
  751. for (i = 0; i < ins->nscb; ++i) {
  752. if (ins->scbs[i].deleted) continue;
  753. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  754. }
  755. mutex_unlock(&chip->spos_mutex);
  756. snd_info_free_entry(ins->proc_dsp_dir);
  757. ins->proc_dsp_dir = NULL;
  758. return 0;
  759. }
  760. #endif /* CONFIG_SND_PROC_FS */
  761. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  762. u32 dest, int size)
  763. {
  764. void __iomem *spdst = chip->region.idx[1].remap_addr +
  765. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  766. int i;
  767. for (i = 0; i < size; ++i) {
  768. dev_dbg(chip->card->dev, "addr %p, val %08x\n",
  769. spdst, task_data[i]);
  770. writel(task_data[i],spdst);
  771. spdst += sizeof(u32);
  772. }
  773. }
  774. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  775. {
  776. void __iomem *spdst = chip->region.idx[1].remap_addr +
  777. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  778. int i;
  779. for (i = 0; i < 0x10; ++i) {
  780. dev_dbg(chip->card->dev, "addr %p, val %08x\n",
  781. spdst, scb_data[i]);
  782. writel(scb_data[i],spdst);
  783. spdst += sizeof(u32);
  784. }
  785. }
  786. static int find_free_scb_index (struct dsp_spos_instance * ins)
  787. {
  788. int index = ins->nscb, i;
  789. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  790. if (ins->scbs[i].deleted) {
  791. index = i;
  792. break;
  793. }
  794. }
  795. return index;
  796. }
  797. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  798. {
  799. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  800. struct dsp_scb_descriptor * desc = NULL;
  801. int index;
  802. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  803. dev_err(chip->card->dev,
  804. "dsp_spos: got no place for other SCB\n");
  805. return NULL;
  806. }
  807. index = find_free_scb_index (ins);
  808. memset(&ins->scbs[index], 0, sizeof(ins->scbs[index]));
  809. strcpy(ins->scbs[index].scb_name, name);
  810. ins->scbs[index].address = dest;
  811. ins->scbs[index].index = index;
  812. ins->scbs[index].ref_count = 1;
  813. desc = (ins->scbs + index);
  814. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  815. if (index > ins->scb_highest_frag_index)
  816. ins->scb_highest_frag_index = index;
  817. if (index == ins->nscb)
  818. ins->nscb++;
  819. return desc;
  820. }
  821. static struct dsp_task_descriptor *
  822. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  823. {
  824. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  825. struct dsp_task_descriptor * desc = NULL;
  826. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  827. dev_err(chip->card->dev,
  828. "dsp_spos: got no place for other TASK\n");
  829. return NULL;
  830. }
  831. if (name)
  832. strcpy(ins->tasks[ins->ntask].task_name, name);
  833. else
  834. strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
  835. ins->tasks[ins->ntask].address = dest;
  836. ins->tasks[ins->ntask].size = size;
  837. /* quick find in list */
  838. ins->tasks[ins->ntask].index = ins->ntask;
  839. desc = (ins->tasks + ins->ntask);
  840. ins->ntask++;
  841. if (name)
  842. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  843. return desc;
  844. }
  845. #define SCB_BYTES (0x10 * 4)
  846. struct dsp_scb_descriptor *
  847. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  848. {
  849. struct dsp_scb_descriptor * desc;
  850. #ifdef CONFIG_PM_SLEEP
  851. /* copy the data for resume */
  852. scb_data = kmemdup(scb_data, SCB_BYTES, GFP_KERNEL);
  853. if (!scb_data)
  854. return NULL;
  855. #endif
  856. desc = _map_scb (chip,name,dest);
  857. if (desc) {
  858. desc->data = scb_data;
  859. _dsp_create_scb(chip,scb_data,dest);
  860. } else {
  861. dev_err(chip->card->dev, "dsp_spos: failed to map SCB\n");
  862. #ifdef CONFIG_PM_SLEEP
  863. kfree(scb_data);
  864. #endif
  865. }
  866. return desc;
  867. }
  868. static struct dsp_task_descriptor *
  869. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  870. u32 dest, int size)
  871. {
  872. struct dsp_task_descriptor * desc;
  873. desc = _map_task_tree (chip,name,dest,size);
  874. if (desc) {
  875. desc->data = task_data;
  876. _dsp_create_task_tree(chip,task_data,dest,size);
  877. } else {
  878. dev_err(chip->card->dev, "dsp_spos: failed to map TASK\n");
  879. }
  880. return desc;
  881. }
  882. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  883. {
  884. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  885. struct dsp_symbol_entry * fg_task_tree_header_code;
  886. struct dsp_symbol_entry * task_tree_header_code;
  887. struct dsp_symbol_entry * task_tree_thread;
  888. struct dsp_symbol_entry * null_algorithm;
  889. struct dsp_symbol_entry * magic_snoop_task;
  890. struct dsp_scb_descriptor * timing_master_scb;
  891. struct dsp_scb_descriptor * codec_out_scb;
  892. struct dsp_scb_descriptor * codec_in_scb;
  893. struct dsp_scb_descriptor * src_task_scb;
  894. struct dsp_scb_descriptor * master_mix_scb;
  895. struct dsp_scb_descriptor * rear_mix_scb;
  896. struct dsp_scb_descriptor * record_mix_scb;
  897. struct dsp_scb_descriptor * write_back_scb;
  898. struct dsp_scb_descriptor * vari_decimate_scb;
  899. struct dsp_scb_descriptor * rear_codec_out_scb;
  900. struct dsp_scb_descriptor * clfe_codec_out_scb;
  901. struct dsp_scb_descriptor * magic_snoop_scb;
  902. int fifo_addr, fifo_span, valid_slots;
  903. static struct dsp_spos_control_block sposcb = {
  904. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  905. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  906. /* 2 */ DSP_SPOS_DC,0,
  907. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  908. /* 4 */ 0,0,
  909. /* 5 */ DSP_SPOS_UU,0,
  910. /* 6 */ FG_TASK_HEADER_ADDR,0,
  911. /* 7 */ 0,0,
  912. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  913. /* 9 */ 0,
  914. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  915. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  916. /* C */ DSP_SPOS_DC_DC,
  917. /* D */ DSP_SPOS_DC_DC,
  918. /* E */ DSP_SPOS_DC_DC,
  919. /* F */ DSP_SPOS_DC_DC
  920. };
  921. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  922. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  923. if (null_algorithm == NULL) {
  924. dev_err(chip->card->dev,
  925. "dsp_spos: symbol NULLALGORITHM not found\n");
  926. return -EIO;
  927. }
  928. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  929. if (fg_task_tree_header_code == NULL) {
  930. dev_err(chip->card->dev,
  931. "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  932. return -EIO;
  933. }
  934. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  935. if (task_tree_header_code == NULL) {
  936. dev_err(chip->card->dev,
  937. "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  938. return -EIO;
  939. }
  940. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  941. if (task_tree_thread == NULL) {
  942. dev_err(chip->card->dev,
  943. "dsp_spos: symbol TASKTREETHREAD not found\n");
  944. return -EIO;
  945. }
  946. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  947. if (magic_snoop_task == NULL) {
  948. dev_err(chip->card->dev,
  949. "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  950. return -EIO;
  951. }
  952. {
  953. /* create the null SCB */
  954. static struct dsp_generic_scb null_scb = {
  955. { 0, 0, 0, 0 },
  956. { 0, 0, 0, 0, 0 },
  957. NULL_SCB_ADDR, NULL_SCB_ADDR,
  958. 0, 0, 0, 0, 0,
  959. {
  960. 0,0,
  961. 0,0,
  962. }
  963. };
  964. null_scb.entry_point = null_algorithm->address;
  965. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  966. ins->the_null_scb->task_entry = null_algorithm;
  967. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  968. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  969. ins->the_null_scb->parent_scb_ptr = NULL;
  970. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  971. }
  972. {
  973. /* setup foreground task tree */
  974. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  975. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  976. DSP_SPOS_DC_DC,
  977. DSP_SPOS_DC_DC,
  978. 0x0000,DSP_SPOS_DC,
  979. DSP_SPOS_DC, DSP_SPOS_DC,
  980. DSP_SPOS_DC_DC,
  981. DSP_SPOS_DC_DC,
  982. DSP_SPOS_DC_DC,
  983. DSP_SPOS_DC,DSP_SPOS_DC },
  984. {
  985. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  986. 0,
  987. FG_TASK_HEADER_ADDR + TCBData,
  988. },
  989. {
  990. 4,0,
  991. 1,0,
  992. 2,SPOSCB_ADDR + HFGFlags,
  993. 0,0,
  994. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  995. },
  996. {
  997. DSP_SPOS_DC,0,
  998. DSP_SPOS_DC,DSP_SPOS_DC,
  999. DSP_SPOS_DC,DSP_SPOS_DC,
  1000. DSP_SPOS_DC,DSP_SPOS_DC,
  1001. DSP_SPOS_DC,DSP_SPOS_DC,
  1002. DSP_SPOS_DCDC,
  1003. DSP_SPOS_UU,1,
  1004. DSP_SPOS_DCDC,
  1005. DSP_SPOS_DCDC,
  1006. DSP_SPOS_DCDC,
  1007. DSP_SPOS_DCDC,
  1008. DSP_SPOS_DCDC,
  1009. DSP_SPOS_DCDC,
  1010. DSP_SPOS_DCDC,
  1011. DSP_SPOS_DCDC,
  1012. DSP_SPOS_DCDC,
  1013. DSP_SPOS_DCDC,
  1014. DSP_SPOS_DCDC,
  1015. DSP_SPOS_DCDC,
  1016. DSP_SPOS_DCDC,
  1017. DSP_SPOS_DCDC,
  1018. DSP_SPOS_DCDC,
  1019. DSP_SPOS_DCDC,
  1020. DSP_SPOS_DCDC,
  1021. DSP_SPOS_DCDC,
  1022. DSP_SPOS_DCDC,
  1023. DSP_SPOS_DCDC,
  1024. DSP_SPOS_DCDC,
  1025. DSP_SPOS_DCDC,
  1026. DSP_SPOS_DCDC,
  1027. DSP_SPOS_DCDC,
  1028. DSP_SPOS_DCDC,
  1029. DSP_SPOS_DCDC,
  1030. DSP_SPOS_DCDC,
  1031. DSP_SPOS_DCDC
  1032. },
  1033. {
  1034. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1035. 0,0
  1036. }
  1037. };
  1038. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  1039. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1040. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  1041. }
  1042. {
  1043. /* setup foreground task tree */
  1044. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  1045. { DSP_SPOS_DC_DC,
  1046. DSP_SPOS_DC_DC,
  1047. DSP_SPOS_DC_DC,
  1048. DSP_SPOS_DC, DSP_SPOS_DC,
  1049. DSP_SPOS_DC, DSP_SPOS_DC,
  1050. DSP_SPOS_DC_DC,
  1051. DSP_SPOS_DC_DC,
  1052. DSP_SPOS_DC_DC,
  1053. DSP_SPOS_DC,DSP_SPOS_DC },
  1054. {
  1055. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  1056. 0,
  1057. BG_TREE_SCB_ADDR + TCBData,
  1058. },
  1059. {
  1060. 9999,0,
  1061. 0,1,
  1062. 0,SPOSCB_ADDR + HFGFlags,
  1063. 0,0,
  1064. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1065. },
  1066. {
  1067. DSP_SPOS_DC,0,
  1068. DSP_SPOS_DC,DSP_SPOS_DC,
  1069. DSP_SPOS_DC,DSP_SPOS_DC,
  1070. DSP_SPOS_DC,DSP_SPOS_DC,
  1071. DSP_SPOS_DC,DSP_SPOS_DC,
  1072. DSP_SPOS_DCDC,
  1073. DSP_SPOS_UU,1,
  1074. DSP_SPOS_DCDC,
  1075. DSP_SPOS_DCDC,
  1076. DSP_SPOS_DCDC,
  1077. DSP_SPOS_DCDC,
  1078. DSP_SPOS_DCDC,
  1079. DSP_SPOS_DCDC,
  1080. DSP_SPOS_DCDC,
  1081. DSP_SPOS_DCDC,
  1082. DSP_SPOS_DCDC,
  1083. DSP_SPOS_DCDC,
  1084. DSP_SPOS_DCDC,
  1085. DSP_SPOS_DCDC,
  1086. DSP_SPOS_DCDC,
  1087. DSP_SPOS_DCDC,
  1088. DSP_SPOS_DCDC,
  1089. DSP_SPOS_DCDC,
  1090. DSP_SPOS_DCDC,
  1091. DSP_SPOS_DCDC,
  1092. DSP_SPOS_DCDC,
  1093. DSP_SPOS_DCDC,
  1094. DSP_SPOS_DCDC,
  1095. DSP_SPOS_DCDC,
  1096. DSP_SPOS_DCDC,
  1097. DSP_SPOS_DCDC,
  1098. DSP_SPOS_DCDC,
  1099. DSP_SPOS_DCDC,
  1100. DSP_SPOS_DCDC,
  1101. DSP_SPOS_DCDC
  1102. },
  1103. {
  1104. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1105. 0,0
  1106. }
  1107. };
  1108. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1109. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1110. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1111. }
  1112. /* create timing master SCB */
  1113. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1114. /* create the CODEC output task */
  1115. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1116. MASTERMIX_SCB_ADDR,
  1117. CODECOUT_SCB_ADDR,timing_master_scb,
  1118. SCB_ON_PARENT_SUBLIST_SCB);
  1119. if (!codec_out_scb) goto _fail_end;
  1120. /* create the master mix SCB */
  1121. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1122. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1123. codec_out_scb,
  1124. SCB_ON_PARENT_SUBLIST_SCB);
  1125. ins->master_mix_scb = master_mix_scb;
  1126. if (!master_mix_scb) goto _fail_end;
  1127. /* create codec in */
  1128. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1129. CODEC_INPUT_BUF1,
  1130. CODECIN_SCB_ADDR,codec_out_scb,
  1131. SCB_ON_PARENT_NEXT_SCB);
  1132. if (!codec_in_scb) goto _fail_end;
  1133. ins->codec_in_scb = codec_in_scb;
  1134. /* create write back scb */
  1135. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1136. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1137. WRITEBACK_SCB_ADDR,
  1138. timing_master_scb,
  1139. SCB_ON_PARENT_NEXT_SCB);
  1140. if (!write_back_scb) goto _fail_end;
  1141. {
  1142. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1143. 0x00020000,
  1144. 0x0000ffff
  1145. };
  1146. if (!cs46xx_dsp_create_task_tree(chip, NULL,
  1147. (u32 *)&mix2_ostream_spb,
  1148. WRITE_BACK_SPB, 2))
  1149. goto _fail_end;
  1150. }
  1151. /* input sample converter */
  1152. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1153. VARI_DECIMATE_BUF0,
  1154. VARI_DECIMATE_BUF1,
  1155. VARIDECIMATE_SCB_ADDR,
  1156. write_back_scb,
  1157. SCB_ON_PARENT_SUBLIST_SCB);
  1158. if (!vari_decimate_scb) goto _fail_end;
  1159. /* create the record mixer SCB */
  1160. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1161. MIX_SAMPLE_BUF2,
  1162. RECORD_MIXER_SCB_ADDR,
  1163. vari_decimate_scb,
  1164. SCB_ON_PARENT_SUBLIST_SCB);
  1165. ins->record_mixer_scb = record_mix_scb;
  1166. if (!record_mix_scb) goto _fail_end;
  1167. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1168. if (snd_BUG_ON(chip->nr_ac97_codecs != 1 && chip->nr_ac97_codecs != 2))
  1169. goto _fail_end;
  1170. if (chip->nr_ac97_codecs == 1) {
  1171. /* output on slot 5 and 11
  1172. on primary CODEC */
  1173. fifo_addr = 0x20;
  1174. fifo_span = 0x60;
  1175. /* enable slot 5 and 11 */
  1176. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1177. } else {
  1178. /* output on slot 7 and 8
  1179. on secondary CODEC */
  1180. fifo_addr = 0x40;
  1181. fifo_span = 0x10;
  1182. /* enable slot 7 and 8 */
  1183. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1184. }
  1185. /* create CODEC tasklet for rear speakers output*/
  1186. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1187. REAR_MIXER_SCB_ADDR,
  1188. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1189. SCB_ON_PARENT_NEXT_SCB);
  1190. if (!rear_codec_out_scb) goto _fail_end;
  1191. /* create the rear PCM channel mixer SCB */
  1192. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1193. MIX_SAMPLE_BUF3,
  1194. REAR_MIXER_SCB_ADDR,
  1195. rear_codec_out_scb,
  1196. SCB_ON_PARENT_SUBLIST_SCB);
  1197. ins->rear_mix_scb = rear_mix_scb;
  1198. if (!rear_mix_scb) goto _fail_end;
  1199. if (chip->nr_ac97_codecs == 2) {
  1200. /* create CODEC tasklet for rear Center/LFE output
  1201. slot 6 and 9 on secondary CODEC */
  1202. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1203. CLFE_MIXER_SCB_ADDR,
  1204. CLFE_CODEC_SCB_ADDR,
  1205. rear_codec_out_scb,
  1206. SCB_ON_PARENT_NEXT_SCB);
  1207. if (!clfe_codec_out_scb) goto _fail_end;
  1208. /* create the rear PCM channel mixer SCB */
  1209. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1210. MIX_SAMPLE_BUF4,
  1211. CLFE_MIXER_SCB_ADDR,
  1212. clfe_codec_out_scb,
  1213. SCB_ON_PARENT_SUBLIST_SCB);
  1214. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1215. /* enable slot 6 and 9 */
  1216. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1217. } else {
  1218. clfe_codec_out_scb = rear_codec_out_scb;
  1219. ins->center_lfe_mix_scb = rear_mix_scb;
  1220. }
  1221. /* enable slots depending on CODEC configuration */
  1222. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1223. /* the magic snooper */
  1224. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1225. OUTPUT_SNOOP_BUFFER,
  1226. codec_out_scb,
  1227. clfe_codec_out_scb,
  1228. SCB_ON_PARENT_NEXT_SCB);
  1229. if (!magic_snoop_scb) goto _fail_end;
  1230. ins->ref_snoop_scb = magic_snoop_scb;
  1231. /* SP IO access */
  1232. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1233. magic_snoop_scb,
  1234. SCB_ON_PARENT_NEXT_SCB))
  1235. goto _fail_end;
  1236. /* SPDIF input sampel rate converter */
  1237. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1238. ins->spdif_in_sample_rate,
  1239. SRC_OUTPUT_BUF1,
  1240. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1241. master_mix_scb,
  1242. SCB_ON_PARENT_SUBLIST_SCB,1);
  1243. if (!src_task_scb) goto _fail_end;
  1244. cs46xx_src_unlink(chip,src_task_scb);
  1245. /* NOTE: when we now how to detect the SPDIF input
  1246. sample rate we will use this SRC to adjust it */
  1247. ins->spdif_in_src = src_task_scb;
  1248. cs46xx_dsp_async_init(chip,timing_master_scb);
  1249. return 0;
  1250. _fail_end:
  1251. dev_err(chip->card->dev, "dsp_spos: failed to setup SCB's in DSP\n");
  1252. return -EINVAL;
  1253. }
  1254. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1255. struct dsp_scb_descriptor * fg_entry)
  1256. {
  1257. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1258. struct dsp_symbol_entry * s16_async_codec_input_task;
  1259. struct dsp_symbol_entry * spdifo_task;
  1260. struct dsp_symbol_entry * spdifi_task;
  1261. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1262. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1263. if (s16_async_codec_input_task == NULL) {
  1264. dev_err(chip->card->dev,
  1265. "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1266. return -EIO;
  1267. }
  1268. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1269. if (spdifo_task == NULL) {
  1270. dev_err(chip->card->dev,
  1271. "dsp_spos: symbol SPDIFOTASK not found\n");
  1272. return -EIO;
  1273. }
  1274. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1275. if (spdifi_task == NULL) {
  1276. dev_err(chip->card->dev,
  1277. "dsp_spos: symbol SPDIFITASK not found\n");
  1278. return -EIO;
  1279. }
  1280. {
  1281. /* 0xBC0 */
  1282. struct dsp_spdifoscb spdifo_scb = {
  1283. /* 0 */ DSP_SPOS_UUUU,
  1284. {
  1285. /* 1 */ 0xb0,
  1286. /* 2 */ 0,
  1287. /* 3 */ 0,
  1288. /* 4 */ 0,
  1289. },
  1290. /* NOTE: the SPDIF output task read samples in mono
  1291. format, the AsynchFGTxSCB task writes to buffer
  1292. in stereo format
  1293. */
  1294. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1295. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1296. /* 7 */ 0,0,
  1297. /* 8 */ 0,
  1298. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1299. /* A */ spdifo_task->address,
  1300. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1301. {
  1302. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1303. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1304. },
  1305. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1306. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1307. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1308. };
  1309. /* 0xBB0 */
  1310. struct dsp_spdifiscb spdifi_scb = {
  1311. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1312. /* 1 */ 0,
  1313. /* 2 */ 0,
  1314. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1315. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1316. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1317. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1318. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1319. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1320. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1321. /* A */ spdifi_task->address,
  1322. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1323. /* NOTE: The SPDIF input task write the sample in mono
  1324. format from the HW FIFO, the AsynchFGRxSCB task reads
  1325. them in stereo
  1326. */
  1327. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1328. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1329. /* D */ 0x8048,0,
  1330. /* E */ 0x01f0,0x0001,
  1331. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1332. };
  1333. /* 0xBA0 */
  1334. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1335. /* 0 */ DSP_SPOS_UUUU,
  1336. /* 1 */ 0,
  1337. /* 2 */ 0,
  1338. /* 3 */ 1,4000,
  1339. /* 4 */ 0x0118,0x0001,
  1340. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1341. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1342. /* 7 */ DSP_SPOS_UU,0x3,
  1343. /* 8 */ DSP_SPOS_UUUU,
  1344. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1345. /* A */ s16_async_codec_input_task->address,
  1346. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1347. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1348. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1349. #ifdef UseASER1Input
  1350. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1351. Init. 0000:8042: for ASER1
  1352. 0000:8044: for ASER2 */
  1353. /* D */ 0x8042,0,
  1354. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1355. Init 1 stero:8050 ASER1
  1356. Init 0 mono:8070 ASER2
  1357. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1358. /* E */ 0x0100,0x0001,
  1359. #endif
  1360. #ifdef UseASER2Input
  1361. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1362. Init. 0000:8042: for ASER1
  1363. 0000:8044: for ASER2 */
  1364. /* D */ 0x8044,0,
  1365. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1366. Init 1 stero:8050 ASER1
  1367. Init 0 mono:8070 ASER2
  1368. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1369. /* E */ 0x0110,0x0001,
  1370. #endif
  1371. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1372. AsyncCIOutputBufModulo: The modulo size for
  1373. the output buffer of this task */
  1374. /* F */ 0, /* DSP_SPOS_UUUU */
  1375. };
  1376. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1377. if (snd_BUG_ON(!spdifo_scb_desc))
  1378. return -EIO;
  1379. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1380. if (snd_BUG_ON(!spdifi_scb_desc))
  1381. return -EIO;
  1382. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1383. if (snd_BUG_ON(!async_codec_scb_desc))
  1384. return -EIO;
  1385. async_codec_scb_desc->parent_scb_ptr = NULL;
  1386. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1387. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1388. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1389. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1390. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1391. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1392. spdifi_scb_desc->task_entry = spdifi_task;
  1393. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1394. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1395. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1396. spdifo_scb_desc->task_entry = spdifo_task;
  1397. /* this one is faked, as the parnet of SPDIFO task
  1398. is the FG task tree */
  1399. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1400. /* for proc fs */
  1401. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1402. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1403. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1404. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1405. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1406. }
  1407. return 0;
  1408. }
  1409. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1410. {
  1411. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1412. /* set SPDIF output FIFO slot */
  1413. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1414. /* SPDIF output MASTER ENABLE */
  1415. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1416. /* right and left validate bit */
  1417. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1418. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1419. /* clear fifo pointer */
  1420. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1421. /* monitor state */
  1422. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1423. }
  1424. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1425. {
  1426. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1427. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1428. cs46xx_dsp_disable_spdif_hw (chip);
  1429. udelay(50);
  1430. /* set SPDIF output FIFO slot */
  1431. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1432. /* SPDIF output MASTER ENABLE */
  1433. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1434. /* right and left validate bit */
  1435. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1436. /* monitor state */
  1437. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1438. return 0;
  1439. }
  1440. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1441. {
  1442. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1443. /* turn on amplifier */
  1444. chip->active_ctrl(chip, 1);
  1445. chip->amplifier_ctrl(chip, 1);
  1446. if (snd_BUG_ON(ins->asynch_rx_scb))
  1447. return -EINVAL;
  1448. if (snd_BUG_ON(!ins->spdif_in_src))
  1449. return -EINVAL;
  1450. mutex_lock(&chip->spos_mutex);
  1451. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1452. /* time countdown enable */
  1453. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1454. /* NOTE: 80000005 value is just magic. With all values
  1455. that I've tested this one seem to give the best result.
  1456. Got no explication why. (Benny) */
  1457. /* SPDIF input MASTER ENABLE */
  1458. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1459. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1460. }
  1461. /* create and start the asynchronous receiver SCB */
  1462. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1463. ASYNCRX_SCB_ADDR,
  1464. SPDIFI_SCB_INST,
  1465. SPDIFI_IP_OUTPUT_BUFFER1,
  1466. ins->spdif_in_src,
  1467. SCB_ON_PARENT_SUBLIST_SCB);
  1468. spin_lock_irq(&chip->reg_lock);
  1469. /* reset SPDIF input sample buffer pointer */
  1470. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1471. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1472. /* reset FIFO ptr */
  1473. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1474. cs46xx_src_link(chip,ins->spdif_in_src);
  1475. /* unmute SRC volume */
  1476. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1477. spin_unlock_irq(&chip->reg_lock);
  1478. /* set SPDIF input sample rate and unmute
  1479. NOTE: only 48khz support for SPDIF input this time */
  1480. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1481. /* monitor state */
  1482. ins->spdif_status_in = 1;
  1483. mutex_unlock(&chip->spos_mutex);
  1484. return 0;
  1485. }
  1486. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1487. {
  1488. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1489. if (snd_BUG_ON(!ins->asynch_rx_scb))
  1490. return -EINVAL;
  1491. if (snd_BUG_ON(!ins->spdif_in_src))
  1492. return -EINVAL;
  1493. mutex_lock(&chip->spos_mutex);
  1494. /* Remove the asynchronous receiver SCB */
  1495. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1496. ins->asynch_rx_scb = NULL;
  1497. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1498. /* monitor state */
  1499. ins->spdif_status_in = 0;
  1500. mutex_unlock(&chip->spos_mutex);
  1501. /* restore amplifier */
  1502. chip->active_ctrl(chip, -1);
  1503. chip->amplifier_ctrl(chip, -1);
  1504. return 0;
  1505. }
  1506. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1507. {
  1508. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1509. if (snd_BUG_ON(ins->pcm_input))
  1510. return -EINVAL;
  1511. if (snd_BUG_ON(!ins->ref_snoop_scb))
  1512. return -EINVAL;
  1513. mutex_lock(&chip->spos_mutex);
  1514. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1515. "PCMSerialInput_Wave");
  1516. mutex_unlock(&chip->spos_mutex);
  1517. return 0;
  1518. }
  1519. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1520. {
  1521. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1522. if (snd_BUG_ON(!ins->pcm_input))
  1523. return -EINVAL;
  1524. mutex_lock(&chip->spos_mutex);
  1525. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1526. ins->pcm_input = NULL;
  1527. mutex_unlock(&chip->spos_mutex);
  1528. return 0;
  1529. }
  1530. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1531. {
  1532. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1533. if (snd_BUG_ON(ins->adc_input))
  1534. return -EINVAL;
  1535. if (snd_BUG_ON(!ins->codec_in_scb))
  1536. return -EINVAL;
  1537. mutex_lock(&chip->spos_mutex);
  1538. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1539. "PCMSerialInput_ADC");
  1540. mutex_unlock(&chip->spos_mutex);
  1541. return 0;
  1542. }
  1543. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1544. {
  1545. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1546. if (snd_BUG_ON(!ins->adc_input))
  1547. return -EINVAL;
  1548. mutex_lock(&chip->spos_mutex);
  1549. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1550. ins->adc_input = NULL;
  1551. mutex_unlock(&chip->spos_mutex);
  1552. return 0;
  1553. }
  1554. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1555. {
  1556. u32 temp;
  1557. int i;
  1558. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1559. a rough guess from looking at the controller spec.) */
  1560. if (address < 0x8000 || address >= 0x9000)
  1561. return -EINVAL;
  1562. /* initialize the SP_IO_WRITE SCB with the data. */
  1563. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1564. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1565. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1566. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1567. /* Poke this location to tell the task to start */
  1568. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1569. /* Verify that the task ran */
  1570. for (i=0; i<25; i++) {
  1571. udelay(125);
  1572. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1573. if (temp == 0x00000000)
  1574. break;
  1575. }
  1576. if (i == 25) {
  1577. dev_err(chip->card->dev,
  1578. "dsp_spos: SPIOWriteTask not responding\n");
  1579. return -EBUSY;
  1580. }
  1581. return 0;
  1582. }
  1583. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1584. {
  1585. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1586. struct dsp_scb_descriptor * scb;
  1587. mutex_lock(&chip->spos_mutex);
  1588. /* main output */
  1589. scb = ins->master_mix_scb->sub_list_ptr;
  1590. while (scb != ins->the_null_scb) {
  1591. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1592. scb = scb->next_scb_ptr;
  1593. }
  1594. /* rear output */
  1595. scb = ins->rear_mix_scb->sub_list_ptr;
  1596. while (scb != ins->the_null_scb) {
  1597. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1598. scb = scb->next_scb_ptr;
  1599. }
  1600. ins->dac_volume_left = left;
  1601. ins->dac_volume_right = right;
  1602. mutex_unlock(&chip->spos_mutex);
  1603. return 0;
  1604. }
  1605. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1606. {
  1607. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1608. mutex_lock(&chip->spos_mutex);
  1609. if (ins->asynch_rx_scb != NULL)
  1610. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1611. left,right);
  1612. ins->spdif_input_volume_left = left;
  1613. ins->spdif_input_volume_right = right;
  1614. mutex_unlock(&chip->spos_mutex);
  1615. return 0;
  1616. }
  1617. #ifdef CONFIG_PM_SLEEP
  1618. int cs46xx_dsp_resume(struct snd_cs46xx * chip)
  1619. {
  1620. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1621. int i, err;
  1622. /* clear parameter, sample and code areas */
  1623. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
  1624. DSP_PARAMETER_BYTE_SIZE);
  1625. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
  1626. DSP_SAMPLE_BYTE_SIZE);
  1627. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  1628. for (i = 0; i < ins->nmodules; i++) {
  1629. struct dsp_module_desc *module = &ins->modules[i];
  1630. struct dsp_segment_desc *seg;
  1631. u32 doffset, dsize;
  1632. seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
  1633. err = dsp_load_parameter(chip, seg);
  1634. if (err < 0)
  1635. return err;
  1636. seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
  1637. err = dsp_load_sample(chip, seg);
  1638. if (err < 0)
  1639. return err;
  1640. seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
  1641. if (!seg)
  1642. continue;
  1643. doffset = seg->offset * 4 + module->load_address * 4
  1644. + DSP_CODE_BYTE_OFFSET;
  1645. dsize = seg->size * 4;
  1646. err = snd_cs46xx_download(chip,
  1647. ins->code.data + module->load_address,
  1648. doffset, dsize);
  1649. if (err < 0)
  1650. return err;
  1651. }
  1652. for (i = 0; i < ins->ntask; i++) {
  1653. struct dsp_task_descriptor *t = &ins->tasks[i];
  1654. _dsp_create_task_tree(chip, t->data, t->address, t->size);
  1655. }
  1656. for (i = 0; i < ins->nscb; i++) {
  1657. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1658. if (s->deleted)
  1659. continue;
  1660. _dsp_create_scb(chip, s->data, s->address);
  1661. }
  1662. for (i = 0; i < ins->nscb; i++) {
  1663. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1664. if (s->deleted)
  1665. continue;
  1666. if (s->updated)
  1667. cs46xx_dsp_spos_update_scb(chip, s);
  1668. if (s->volume_set)
  1669. cs46xx_dsp_scb_set_volume(chip, s,
  1670. s->volume[0], s->volume[1]);
  1671. }
  1672. if (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) {
  1673. cs46xx_dsp_enable_spdif_hw(chip);
  1674. snd_cs46xx_poke(chip, (ins->ref_snoop_scb->address + 2) << 2,
  1675. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10);
  1676. if (ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN)
  1677. cs46xx_poke_via_dsp(chip, SP_SPDOUT_CSUV,
  1678. ins->spdif_csuv_stream);
  1679. }
  1680. if (chip->dsp_spos_instance->spdif_status_in) {
  1681. cs46xx_poke_via_dsp(chip, SP_ASER_COUNTDOWN, 0x80000005);
  1682. cs46xx_poke_via_dsp(chip, SP_SPDIN_CONTROL, 0x800003ff);
  1683. }
  1684. return 0;
  1685. }
  1686. #endif