chip.c 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457
  1. /*
  2. * linux/kernel/irq/chip.c
  3. *
  4. * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  5. * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  6. *
  7. * This file contains the core interrupt handling code, for irq-chip
  8. * based architectures.
  9. *
  10. * Detailed information is available in Documentation/core-api/genericirq.rst
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/msi.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/wakeup_reason.h>
  19. #include <trace/events/irq.h>
  20. #include "internals.h"
  21. static irqreturn_t bad_chained_irq(int irq, void *dev_id)
  22. {
  23. WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
  24. return IRQ_NONE;
  25. }
  26. /*
  27. * Chained handlers should never call action on their IRQ. This default
  28. * action will emit warning if such thing happens.
  29. */
  30. struct irqaction chained_action = {
  31. .handler = bad_chained_irq,
  32. };
  33. /**
  34. * irq_set_chip - set the irq chip for an irq
  35. * @irq: irq number
  36. * @chip: pointer to irq chip description structure
  37. */
  38. int irq_set_chip(unsigned int irq, struct irq_chip *chip)
  39. {
  40. unsigned long flags;
  41. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  42. if (!desc)
  43. return -EINVAL;
  44. if (!chip)
  45. chip = &no_irq_chip;
  46. desc->irq_data.chip = chip;
  47. irq_put_desc_unlock(desc, flags);
  48. /*
  49. * For !CONFIG_SPARSE_IRQ make the irq show up in
  50. * allocated_irqs.
  51. */
  52. irq_mark_irq(irq);
  53. return 0;
  54. }
  55. EXPORT_SYMBOL(irq_set_chip);
  56. /**
  57. * irq_set_type - set the irq trigger type for an irq
  58. * @irq: irq number
  59. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  60. */
  61. int irq_set_irq_type(unsigned int irq, unsigned int type)
  62. {
  63. unsigned long flags;
  64. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  65. int ret = 0;
  66. if (!desc)
  67. return -EINVAL;
  68. ret = __irq_set_trigger(desc, type);
  69. irq_put_desc_busunlock(desc, flags);
  70. return ret;
  71. }
  72. EXPORT_SYMBOL(irq_set_irq_type);
  73. /**
  74. * irq_set_handler_data - set irq handler data for an irq
  75. * @irq: Interrupt number
  76. * @data: Pointer to interrupt specific data
  77. *
  78. * Set the hardware irq controller data for an irq
  79. */
  80. int irq_set_handler_data(unsigned int irq, void *data)
  81. {
  82. unsigned long flags;
  83. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  84. if (!desc)
  85. return -EINVAL;
  86. desc->irq_common_data.handler_data = data;
  87. irq_put_desc_unlock(desc, flags);
  88. return 0;
  89. }
  90. EXPORT_SYMBOL(irq_set_handler_data);
  91. /**
  92. * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
  93. * @irq_base: Interrupt number base
  94. * @irq_offset: Interrupt number offset
  95. * @entry: Pointer to MSI descriptor data
  96. *
  97. * Set the MSI descriptor entry for an irq at offset
  98. */
  99. int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  100. struct msi_desc *entry)
  101. {
  102. unsigned long flags;
  103. struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  104. if (!desc)
  105. return -EINVAL;
  106. desc->irq_common_data.msi_desc = entry;
  107. if (entry && !irq_offset)
  108. entry->irq = irq_base;
  109. irq_put_desc_unlock(desc, flags);
  110. return 0;
  111. }
  112. /**
  113. * irq_set_msi_desc - set MSI descriptor data for an irq
  114. * @irq: Interrupt number
  115. * @entry: Pointer to MSI descriptor data
  116. *
  117. * Set the MSI descriptor entry for an irq
  118. */
  119. int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
  120. {
  121. return irq_set_msi_desc_off(irq, 0, entry);
  122. }
  123. /**
  124. * irq_set_chip_data - set irq chip data for an irq
  125. * @irq: Interrupt number
  126. * @data: Pointer to chip specific data
  127. *
  128. * Set the hardware irq chip data for an irq
  129. */
  130. int irq_set_chip_data(unsigned int irq, void *data)
  131. {
  132. unsigned long flags;
  133. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  134. if (!desc)
  135. return -EINVAL;
  136. desc->irq_data.chip_data = data;
  137. irq_put_desc_unlock(desc, flags);
  138. return 0;
  139. }
  140. EXPORT_SYMBOL(irq_set_chip_data);
  141. struct irq_data *irq_get_irq_data(unsigned int irq)
  142. {
  143. struct irq_desc *desc = irq_to_desc(irq);
  144. return desc ? &desc->irq_data : NULL;
  145. }
  146. EXPORT_SYMBOL_GPL(irq_get_irq_data);
  147. static void irq_state_clr_disabled(struct irq_desc *desc)
  148. {
  149. irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
  150. }
  151. static void irq_state_clr_masked(struct irq_desc *desc)
  152. {
  153. irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
  154. }
  155. static void irq_state_clr_started(struct irq_desc *desc)
  156. {
  157. irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
  158. }
  159. static void irq_state_set_started(struct irq_desc *desc)
  160. {
  161. irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
  162. }
  163. enum {
  164. IRQ_STARTUP_NORMAL,
  165. IRQ_STARTUP_MANAGED,
  166. IRQ_STARTUP_ABORT,
  167. };
  168. #ifdef CONFIG_SMP
  169. static int
  170. __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
  171. {
  172. struct irq_data *d = irq_desc_get_irq_data(desc);
  173. if (!irqd_affinity_is_managed(d))
  174. return IRQ_STARTUP_NORMAL;
  175. irqd_clr_managed_shutdown(d);
  176. if (cpumask_any_and(aff, cpu_online_mask) >= nr_cpu_ids) {
  177. /*
  178. * Catch code which fiddles with enable_irq() on a managed
  179. * and potentially shutdown IRQ. Chained interrupt
  180. * installment or irq auto probing should not happen on
  181. * managed irqs either. Emit a warning, break the affinity
  182. * and start it up as a normal interrupt.
  183. */
  184. if (WARN_ON_ONCE(force))
  185. return IRQ_STARTUP_NORMAL;
  186. /*
  187. * The interrupt was requested, but there is no online CPU
  188. * in it's affinity mask. Put it into managed shutdown
  189. * state and let the cpu hotplug mechanism start it up once
  190. * a CPU in the mask becomes available.
  191. */
  192. irqd_set_managed_shutdown(d);
  193. return IRQ_STARTUP_ABORT;
  194. }
  195. return IRQ_STARTUP_MANAGED;
  196. }
  197. #else
  198. static __always_inline int
  199. __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
  200. {
  201. return IRQ_STARTUP_NORMAL;
  202. }
  203. #endif
  204. static int __irq_startup(struct irq_desc *desc)
  205. {
  206. struct irq_data *d = irq_desc_get_irq_data(desc);
  207. int ret = 0;
  208. irq_domain_activate_irq(d);
  209. if (d->chip->irq_startup) {
  210. ret = d->chip->irq_startup(d);
  211. irq_state_clr_disabled(desc);
  212. irq_state_clr_masked(desc);
  213. } else {
  214. irq_enable(desc);
  215. }
  216. irq_state_set_started(desc);
  217. return ret;
  218. }
  219. int irq_startup(struct irq_desc *desc, bool resend, bool force)
  220. {
  221. struct irq_data *d = irq_desc_get_irq_data(desc);
  222. struct cpumask *aff = irq_data_get_affinity_mask(d);
  223. int ret = 0;
  224. desc->depth = 0;
  225. if (irqd_is_started(d)) {
  226. irq_enable(desc);
  227. } else {
  228. switch (__irq_startup_managed(desc, aff, force)) {
  229. case IRQ_STARTUP_NORMAL:
  230. ret = __irq_startup(desc);
  231. irq_setup_affinity(desc);
  232. break;
  233. case IRQ_STARTUP_MANAGED:
  234. irq_do_set_affinity(d, aff, false);
  235. ret = __irq_startup(desc);
  236. break;
  237. case IRQ_STARTUP_ABORT:
  238. return 0;
  239. }
  240. }
  241. if (resend)
  242. check_irq_resend(desc);
  243. return ret;
  244. }
  245. static void __irq_disable(struct irq_desc *desc, bool mask);
  246. void irq_shutdown(struct irq_desc *desc)
  247. {
  248. if (irqd_is_started(&desc->irq_data)) {
  249. desc->depth = 1;
  250. if (desc->irq_data.chip->irq_shutdown) {
  251. desc->irq_data.chip->irq_shutdown(&desc->irq_data);
  252. irq_state_set_disabled(desc);
  253. irq_state_set_masked(desc);
  254. } else {
  255. __irq_disable(desc, true);
  256. }
  257. irq_state_clr_started(desc);
  258. }
  259. /*
  260. * This must be called even if the interrupt was never started up,
  261. * because the activation can happen before the interrupt is
  262. * available for request/startup. It has it's own state tracking so
  263. * it's safe to call it unconditionally.
  264. */
  265. irq_domain_deactivate_irq(&desc->irq_data);
  266. }
  267. void irq_enable(struct irq_desc *desc)
  268. {
  269. if (!irqd_irq_disabled(&desc->irq_data)) {
  270. unmask_irq(desc);
  271. } else {
  272. irq_state_clr_disabled(desc);
  273. if (desc->irq_data.chip->irq_enable) {
  274. desc->irq_data.chip->irq_enable(&desc->irq_data);
  275. irq_state_clr_masked(desc);
  276. } else {
  277. unmask_irq(desc);
  278. }
  279. }
  280. }
  281. static void __irq_disable(struct irq_desc *desc, bool mask)
  282. {
  283. if (irqd_irq_disabled(&desc->irq_data)) {
  284. if (mask)
  285. mask_irq(desc);
  286. } else {
  287. irq_state_set_disabled(desc);
  288. if (desc->irq_data.chip->irq_disable) {
  289. desc->irq_data.chip->irq_disable(&desc->irq_data);
  290. irq_state_set_masked(desc);
  291. } else if (mask) {
  292. mask_irq(desc);
  293. }
  294. }
  295. }
  296. /**
  297. * irq_disable - Mark interrupt disabled
  298. * @desc: irq descriptor which should be disabled
  299. *
  300. * If the chip does not implement the irq_disable callback, we
  301. * use a lazy disable approach. That means we mark the interrupt
  302. * disabled, but leave the hardware unmasked. That's an
  303. * optimization because we avoid the hardware access for the
  304. * common case where no interrupt happens after we marked it
  305. * disabled. If an interrupt happens, then the interrupt flow
  306. * handler masks the line at the hardware level and marks it
  307. * pending.
  308. *
  309. * If the interrupt chip does not implement the irq_disable callback,
  310. * a driver can disable the lazy approach for a particular irq line by
  311. * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
  312. * be used for devices which cannot disable the interrupt at the
  313. * device level under certain circumstances and have to use
  314. * disable_irq[_nosync] instead.
  315. */
  316. void irq_disable(struct irq_desc *desc)
  317. {
  318. __irq_disable(desc, irq_settings_disable_unlazy(desc));
  319. }
  320. void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
  321. {
  322. if (desc->irq_data.chip->irq_enable)
  323. desc->irq_data.chip->irq_enable(&desc->irq_data);
  324. else
  325. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  326. cpumask_set_cpu(cpu, desc->percpu_enabled);
  327. }
  328. void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
  329. {
  330. if (desc->irq_data.chip->irq_disable)
  331. desc->irq_data.chip->irq_disable(&desc->irq_data);
  332. else
  333. desc->irq_data.chip->irq_mask(&desc->irq_data);
  334. cpumask_clear_cpu(cpu, desc->percpu_enabled);
  335. }
  336. static inline void mask_ack_irq(struct irq_desc *desc)
  337. {
  338. if (desc->irq_data.chip->irq_mask_ack) {
  339. desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
  340. irq_state_set_masked(desc);
  341. } else {
  342. mask_irq(desc);
  343. if (desc->irq_data.chip->irq_ack)
  344. desc->irq_data.chip->irq_ack(&desc->irq_data);
  345. }
  346. }
  347. void mask_irq(struct irq_desc *desc)
  348. {
  349. if (irqd_irq_masked(&desc->irq_data))
  350. return;
  351. if (desc->irq_data.chip->irq_mask) {
  352. desc->irq_data.chip->irq_mask(&desc->irq_data);
  353. irq_state_set_masked(desc);
  354. }
  355. }
  356. void unmask_irq(struct irq_desc *desc)
  357. {
  358. if (!irqd_irq_masked(&desc->irq_data))
  359. return;
  360. if (desc->irq_data.chip->irq_unmask) {
  361. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  362. irq_state_clr_masked(desc);
  363. }
  364. }
  365. void unmask_threaded_irq(struct irq_desc *desc)
  366. {
  367. struct irq_chip *chip = desc->irq_data.chip;
  368. if (chip->flags & IRQCHIP_EOI_THREADED)
  369. chip->irq_eoi(&desc->irq_data);
  370. unmask_irq(desc);
  371. }
  372. /*
  373. * handle_nested_irq - Handle a nested irq from a irq thread
  374. * @irq: the interrupt number
  375. *
  376. * Handle interrupts which are nested into a threaded interrupt
  377. * handler. The handler function is called inside the calling
  378. * threads context.
  379. */
  380. void handle_nested_irq(unsigned int irq)
  381. {
  382. struct irq_desc *desc = irq_to_desc(irq);
  383. struct irqaction *action;
  384. irqreturn_t action_ret;
  385. might_sleep();
  386. raw_spin_lock_irq(&desc->lock);
  387. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  388. action = desc->action;
  389. if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
  390. desc->istate |= IRQS_PENDING;
  391. goto out_unlock;
  392. }
  393. kstat_incr_irqs_this_cpu(desc);
  394. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  395. raw_spin_unlock_irq(&desc->lock);
  396. action_ret = IRQ_NONE;
  397. for_each_action_of_desc(desc, action)
  398. action_ret |= action->thread_fn(action->irq, action->dev_id);
  399. if (!noirqdebug)
  400. note_interrupt(desc, action_ret);
  401. raw_spin_lock_irq(&desc->lock);
  402. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  403. out_unlock:
  404. raw_spin_unlock_irq(&desc->lock);
  405. }
  406. EXPORT_SYMBOL_GPL(handle_nested_irq);
  407. static bool irq_check_poll(struct irq_desc *desc)
  408. {
  409. if (!(desc->istate & IRQS_POLL_INPROGRESS))
  410. return false;
  411. return irq_wait_for_poll(desc);
  412. }
  413. static bool irq_may_run(struct irq_desc *desc)
  414. {
  415. unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
  416. /*
  417. * If the interrupt is not in progress and is not an armed
  418. * wakeup interrupt, proceed.
  419. */
  420. if (!irqd_has_set(&desc->irq_data, mask)) {
  421. #ifdef CONFIG_PM_SLEEP
  422. if (unlikely(desc->no_suspend_depth &&
  423. irqd_is_wakeup_set(&desc->irq_data))) {
  424. unsigned int irq = irq_desc_get_irq(desc);
  425. const char *name = "(unnamed)";
  426. if (desc->action && desc->action->name)
  427. name = desc->action->name;
  428. log_abnormal_wakeup_reason("misconfigured IRQ %u %s",
  429. irq, name);
  430. }
  431. #endif
  432. return true;
  433. }
  434. /*
  435. * If the interrupt is an armed wakeup source, mark it pending
  436. * and suspended, disable it and notify the pm core about the
  437. * event.
  438. */
  439. if (irq_pm_check_wakeup(desc))
  440. return false;
  441. /*
  442. * Handle a potential concurrent poll on a different core.
  443. */
  444. return irq_check_poll(desc);
  445. }
  446. /**
  447. * handle_simple_irq - Simple and software-decoded IRQs.
  448. * @desc: the interrupt description structure for this irq
  449. *
  450. * Simple interrupts are either sent from a demultiplexing interrupt
  451. * handler or come from hardware, where no interrupt hardware control
  452. * is necessary.
  453. *
  454. * Note: The caller is expected to handle the ack, clear, mask and
  455. * unmask issues if necessary.
  456. */
  457. void handle_simple_irq(struct irq_desc *desc)
  458. {
  459. raw_spin_lock(&desc->lock);
  460. if (!irq_may_run(desc))
  461. goto out_unlock;
  462. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  463. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  464. desc->istate |= IRQS_PENDING;
  465. goto out_unlock;
  466. }
  467. kstat_incr_irqs_this_cpu(desc);
  468. handle_irq_event(desc);
  469. out_unlock:
  470. raw_spin_unlock(&desc->lock);
  471. }
  472. EXPORT_SYMBOL_GPL(handle_simple_irq);
  473. /**
  474. * handle_untracked_irq - Simple and software-decoded IRQs.
  475. * @desc: the interrupt description structure for this irq
  476. *
  477. * Untracked interrupts are sent from a demultiplexing interrupt
  478. * handler when the demultiplexer does not know which device it its
  479. * multiplexed irq domain generated the interrupt. IRQ's handled
  480. * through here are not subjected to stats tracking, randomness, or
  481. * spurious interrupt detection.
  482. *
  483. * Note: Like handle_simple_irq, the caller is expected to handle
  484. * the ack, clear, mask and unmask issues if necessary.
  485. */
  486. void handle_untracked_irq(struct irq_desc *desc)
  487. {
  488. unsigned int flags = 0;
  489. raw_spin_lock(&desc->lock);
  490. if (!irq_may_run(desc))
  491. goto out_unlock;
  492. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  493. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  494. desc->istate |= IRQS_PENDING;
  495. goto out_unlock;
  496. }
  497. desc->istate &= ~IRQS_PENDING;
  498. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  499. raw_spin_unlock(&desc->lock);
  500. __handle_irq_event_percpu(desc, &flags);
  501. raw_spin_lock(&desc->lock);
  502. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  503. out_unlock:
  504. raw_spin_unlock(&desc->lock);
  505. }
  506. EXPORT_SYMBOL_GPL(handle_untracked_irq);
  507. /*
  508. * Called unconditionally from handle_level_irq() and only for oneshot
  509. * interrupts from handle_fasteoi_irq()
  510. */
  511. static void cond_unmask_irq(struct irq_desc *desc)
  512. {
  513. /*
  514. * We need to unmask in the following cases:
  515. * - Standard level irq (IRQF_ONESHOT is not set)
  516. * - Oneshot irq which did not wake the thread (caused by a
  517. * spurious interrupt or a primary handler handling it
  518. * completely).
  519. */
  520. if (!irqd_irq_disabled(&desc->irq_data) &&
  521. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  522. unmask_irq(desc);
  523. }
  524. /**
  525. * handle_level_irq - Level type irq handler
  526. * @desc: the interrupt description structure for this irq
  527. *
  528. * Level type interrupts are active as long as the hardware line has
  529. * the active level. This may require to mask the interrupt and unmask
  530. * it after the associated handler has acknowledged the device, so the
  531. * interrupt line is back to inactive.
  532. */
  533. void handle_level_irq(struct irq_desc *desc)
  534. {
  535. raw_spin_lock(&desc->lock);
  536. mask_ack_irq(desc);
  537. if (!irq_may_run(desc))
  538. goto out_unlock;
  539. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  540. /*
  541. * If its disabled or no action available
  542. * keep it masked and get out of here
  543. */
  544. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  545. desc->istate |= IRQS_PENDING;
  546. goto out_unlock;
  547. }
  548. kstat_incr_irqs_this_cpu(desc);
  549. handle_irq_event(desc);
  550. cond_unmask_irq(desc);
  551. out_unlock:
  552. raw_spin_unlock(&desc->lock);
  553. }
  554. EXPORT_SYMBOL_GPL(handle_level_irq);
  555. #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
  556. static inline void preflow_handler(struct irq_desc *desc)
  557. {
  558. if (desc->preflow_handler)
  559. desc->preflow_handler(&desc->irq_data);
  560. }
  561. #else
  562. static inline void preflow_handler(struct irq_desc *desc) { }
  563. #endif
  564. static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
  565. {
  566. if (!(desc->istate & IRQS_ONESHOT)) {
  567. chip->irq_eoi(&desc->irq_data);
  568. return;
  569. }
  570. /*
  571. * We need to unmask in the following cases:
  572. * - Oneshot irq which did not wake the thread (caused by a
  573. * spurious interrupt or a primary handler handling it
  574. * completely).
  575. */
  576. if (!irqd_irq_disabled(&desc->irq_data) &&
  577. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
  578. chip->irq_eoi(&desc->irq_data);
  579. unmask_irq(desc);
  580. } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
  581. chip->irq_eoi(&desc->irq_data);
  582. }
  583. }
  584. /**
  585. * handle_fasteoi_irq - irq handler for transparent controllers
  586. * @desc: the interrupt description structure for this irq
  587. *
  588. * Only a single callback will be issued to the chip: an ->eoi()
  589. * call when the interrupt has been serviced. This enables support
  590. * for modern forms of interrupt handlers, which handle the flow
  591. * details in hardware, transparently.
  592. */
  593. void handle_fasteoi_irq(struct irq_desc *desc)
  594. {
  595. struct irq_chip *chip = desc->irq_data.chip;
  596. raw_spin_lock(&desc->lock);
  597. if (!irq_may_run(desc))
  598. goto out;
  599. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  600. /*
  601. * If its disabled or no action available
  602. * then mask it and get out of here:
  603. */
  604. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  605. desc->istate |= IRQS_PENDING;
  606. mask_irq(desc);
  607. goto out;
  608. }
  609. kstat_incr_irqs_this_cpu(desc);
  610. if (desc->istate & IRQS_ONESHOT)
  611. mask_irq(desc);
  612. preflow_handler(desc);
  613. handle_irq_event(desc);
  614. cond_unmask_eoi_irq(desc, chip);
  615. raw_spin_unlock(&desc->lock);
  616. return;
  617. out:
  618. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  619. chip->irq_eoi(&desc->irq_data);
  620. raw_spin_unlock(&desc->lock);
  621. }
  622. EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
  623. /**
  624. * handle_edge_irq - edge type IRQ handler
  625. * @desc: the interrupt description structure for this irq
  626. *
  627. * Interrupt occures on the falling and/or rising edge of a hardware
  628. * signal. The occurrence is latched into the irq controller hardware
  629. * and must be acked in order to be reenabled. After the ack another
  630. * interrupt can happen on the same source even before the first one
  631. * is handled by the associated event handler. If this happens it
  632. * might be necessary to disable (mask) the interrupt depending on the
  633. * controller hardware. This requires to reenable the interrupt inside
  634. * of the loop which handles the interrupts which have arrived while
  635. * the handler was running. If all pending interrupts are handled, the
  636. * loop is left.
  637. */
  638. void handle_edge_irq(struct irq_desc *desc)
  639. {
  640. raw_spin_lock(&desc->lock);
  641. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  642. if (!irq_may_run(desc)) {
  643. desc->istate |= IRQS_PENDING;
  644. mask_ack_irq(desc);
  645. goto out_unlock;
  646. }
  647. /*
  648. * If its disabled or no action available then mask it and get
  649. * out of here.
  650. */
  651. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  652. desc->istate |= IRQS_PENDING;
  653. mask_ack_irq(desc);
  654. goto out_unlock;
  655. }
  656. kstat_incr_irqs_this_cpu(desc);
  657. /* Start handling the irq */
  658. desc->irq_data.chip->irq_ack(&desc->irq_data);
  659. do {
  660. if (unlikely(!desc->action)) {
  661. mask_irq(desc);
  662. goto out_unlock;
  663. }
  664. /*
  665. * When another irq arrived while we were handling
  666. * one, we could have masked the irq.
  667. * Renable it, if it was not disabled in meantime.
  668. */
  669. if (unlikely(desc->istate & IRQS_PENDING)) {
  670. if (!irqd_irq_disabled(&desc->irq_data) &&
  671. irqd_irq_masked(&desc->irq_data))
  672. unmask_irq(desc);
  673. }
  674. handle_irq_event(desc);
  675. } while ((desc->istate & IRQS_PENDING) &&
  676. !irqd_irq_disabled(&desc->irq_data));
  677. out_unlock:
  678. raw_spin_unlock(&desc->lock);
  679. }
  680. EXPORT_SYMBOL(handle_edge_irq);
  681. #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  682. /**
  683. * handle_edge_eoi_irq - edge eoi type IRQ handler
  684. * @desc: the interrupt description structure for this irq
  685. *
  686. * Similar as the above handle_edge_irq, but using eoi and w/o the
  687. * mask/unmask logic.
  688. */
  689. void handle_edge_eoi_irq(struct irq_desc *desc)
  690. {
  691. struct irq_chip *chip = irq_desc_get_chip(desc);
  692. raw_spin_lock(&desc->lock);
  693. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  694. if (!irq_may_run(desc)) {
  695. desc->istate |= IRQS_PENDING;
  696. goto out_eoi;
  697. }
  698. /*
  699. * If its disabled or no action available then mask it and get
  700. * out of here.
  701. */
  702. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  703. desc->istate |= IRQS_PENDING;
  704. goto out_eoi;
  705. }
  706. kstat_incr_irqs_this_cpu(desc);
  707. do {
  708. if (unlikely(!desc->action))
  709. goto out_eoi;
  710. handle_irq_event(desc);
  711. } while ((desc->istate & IRQS_PENDING) &&
  712. !irqd_irq_disabled(&desc->irq_data));
  713. out_eoi:
  714. chip->irq_eoi(&desc->irq_data);
  715. raw_spin_unlock(&desc->lock);
  716. }
  717. #endif
  718. /**
  719. * handle_percpu_irq - Per CPU local irq handler
  720. * @desc: the interrupt description structure for this irq
  721. *
  722. * Per CPU interrupts on SMP machines without locking requirements
  723. */
  724. void handle_percpu_irq(struct irq_desc *desc)
  725. {
  726. struct irq_chip *chip = irq_desc_get_chip(desc);
  727. /*
  728. * PER CPU interrupts are not serialized. Do not touch
  729. * desc->tot_count.
  730. */
  731. __kstat_incr_irqs_this_cpu(desc);
  732. if (chip->irq_ack)
  733. chip->irq_ack(&desc->irq_data);
  734. handle_irq_event_percpu(desc);
  735. if (chip->irq_eoi)
  736. chip->irq_eoi(&desc->irq_data);
  737. }
  738. /**
  739. * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
  740. * @desc: the interrupt description structure for this irq
  741. *
  742. * Per CPU interrupts on SMP machines without locking requirements. Same as
  743. * handle_percpu_irq() above but with the following extras:
  744. *
  745. * action->percpu_dev_id is a pointer to percpu variables which
  746. * contain the real device id for the cpu on which this handler is
  747. * called
  748. */
  749. void handle_percpu_devid_irq(struct irq_desc *desc)
  750. {
  751. struct irq_chip *chip = irq_desc_get_chip(desc);
  752. struct irqaction *action = desc->action;
  753. unsigned int irq = irq_desc_get_irq(desc);
  754. irqreturn_t res;
  755. /*
  756. * PER CPU interrupts are not serialized. Do not touch
  757. * desc->tot_count.
  758. */
  759. __kstat_incr_irqs_this_cpu(desc);
  760. if (chip->irq_ack)
  761. chip->irq_ack(&desc->irq_data);
  762. if (likely(action)) {
  763. trace_irq_handler_entry(irq, action);
  764. res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
  765. trace_irq_handler_exit(irq, action, res);
  766. } else {
  767. unsigned int cpu = smp_processor_id();
  768. bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
  769. if (enabled)
  770. irq_percpu_disable(desc, cpu);
  771. pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
  772. enabled ? " and unmasked" : "", irq, cpu);
  773. }
  774. if (chip->irq_eoi)
  775. chip->irq_eoi(&desc->irq_data);
  776. }
  777. static void
  778. __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
  779. int is_chained, const char *name)
  780. {
  781. if (!handle) {
  782. handle = handle_bad_irq;
  783. } else {
  784. struct irq_data *irq_data = &desc->irq_data;
  785. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  786. /*
  787. * With hierarchical domains we might run into a
  788. * situation where the outermost chip is not yet set
  789. * up, but the inner chips are there. Instead of
  790. * bailing we install the handler, but obviously we
  791. * cannot enable/startup the interrupt at this point.
  792. */
  793. while (irq_data) {
  794. if (irq_data->chip != &no_irq_chip)
  795. break;
  796. /*
  797. * Bail out if the outer chip is not set up
  798. * and the interrrupt supposed to be started
  799. * right away.
  800. */
  801. if (WARN_ON(is_chained))
  802. return;
  803. /* Try the parent */
  804. irq_data = irq_data->parent_data;
  805. }
  806. #endif
  807. if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
  808. return;
  809. }
  810. /* Uninstall? */
  811. if (handle == handle_bad_irq) {
  812. if (desc->irq_data.chip != &no_irq_chip)
  813. mask_ack_irq(desc);
  814. irq_state_set_disabled(desc);
  815. if (is_chained)
  816. desc->action = NULL;
  817. desc->depth = 1;
  818. }
  819. desc->handle_irq = handle;
  820. desc->name = name;
  821. if (handle != handle_bad_irq && is_chained) {
  822. unsigned int type = irqd_get_trigger_type(&desc->irq_data);
  823. /*
  824. * We're about to start this interrupt immediately,
  825. * hence the need to set the trigger configuration.
  826. * But the .set_type callback may have overridden the
  827. * flow handler, ignoring that we're dealing with a
  828. * chained interrupt. Reset it immediately because we
  829. * do know better.
  830. */
  831. if (type != IRQ_TYPE_NONE) {
  832. __irq_set_trigger(desc, type);
  833. desc->handle_irq = handle;
  834. }
  835. irq_settings_set_noprobe(desc);
  836. irq_settings_set_norequest(desc);
  837. irq_settings_set_nothread(desc);
  838. desc->action = &chained_action;
  839. irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE);
  840. }
  841. }
  842. void
  843. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  844. const char *name)
  845. {
  846. unsigned long flags;
  847. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  848. if (!desc)
  849. return;
  850. __irq_do_set_handler(desc, handle, is_chained, name);
  851. irq_put_desc_busunlock(desc, flags);
  852. }
  853. EXPORT_SYMBOL_GPL(__irq_set_handler);
  854. void
  855. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  856. void *data)
  857. {
  858. unsigned long flags;
  859. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  860. if (!desc)
  861. return;
  862. desc->irq_common_data.handler_data = data;
  863. __irq_do_set_handler(desc, handle, 1, NULL);
  864. irq_put_desc_busunlock(desc, flags);
  865. }
  866. EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
  867. void
  868. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  869. irq_flow_handler_t handle, const char *name)
  870. {
  871. irq_set_chip(irq, chip);
  872. __irq_set_handler(irq, handle, 0, name);
  873. }
  874. EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
  875. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
  876. {
  877. unsigned long flags, trigger, tmp;
  878. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  879. if (!desc)
  880. return;
  881. /*
  882. * Warn when a driver sets the no autoenable flag on an already
  883. * active interrupt.
  884. */
  885. WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
  886. irq_settings_clr_and_set(desc, clr, set);
  887. trigger = irqd_get_trigger_type(&desc->irq_data);
  888. irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
  889. IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
  890. if (irq_settings_has_no_balance_set(desc))
  891. irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
  892. if (irq_settings_is_per_cpu(desc))
  893. irqd_set(&desc->irq_data, IRQD_PER_CPU);
  894. if (irq_settings_can_move_pcntxt(desc))
  895. irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
  896. if (irq_settings_is_level(desc))
  897. irqd_set(&desc->irq_data, IRQD_LEVEL);
  898. tmp = irq_settings_get_trigger_mask(desc);
  899. if (tmp != IRQ_TYPE_NONE)
  900. trigger = tmp;
  901. irqd_set(&desc->irq_data, trigger);
  902. irq_put_desc_unlock(desc, flags);
  903. }
  904. EXPORT_SYMBOL_GPL(irq_modify_status);
  905. /**
  906. * irq_cpu_online - Invoke all irq_cpu_online functions.
  907. *
  908. * Iterate through all irqs and invoke the chip.irq_cpu_online()
  909. * for each.
  910. */
  911. void irq_cpu_online(void)
  912. {
  913. struct irq_desc *desc;
  914. struct irq_chip *chip;
  915. unsigned long flags;
  916. unsigned int irq;
  917. for_each_active_irq(irq) {
  918. desc = irq_to_desc(irq);
  919. if (!desc)
  920. continue;
  921. raw_spin_lock_irqsave(&desc->lock, flags);
  922. chip = irq_data_get_irq_chip(&desc->irq_data);
  923. if (chip && chip->irq_cpu_online &&
  924. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  925. !irqd_irq_disabled(&desc->irq_data)))
  926. chip->irq_cpu_online(&desc->irq_data);
  927. raw_spin_unlock_irqrestore(&desc->lock, flags);
  928. }
  929. }
  930. /**
  931. * irq_cpu_offline - Invoke all irq_cpu_offline functions.
  932. *
  933. * Iterate through all irqs and invoke the chip.irq_cpu_offline()
  934. * for each.
  935. */
  936. void irq_cpu_offline(void)
  937. {
  938. struct irq_desc *desc;
  939. struct irq_chip *chip;
  940. unsigned long flags;
  941. unsigned int irq;
  942. for_each_active_irq(irq) {
  943. desc = irq_to_desc(irq);
  944. if (!desc)
  945. continue;
  946. raw_spin_lock_irqsave(&desc->lock, flags);
  947. chip = irq_data_get_irq_chip(&desc->irq_data);
  948. if (chip && chip->irq_cpu_offline &&
  949. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  950. !irqd_irq_disabled(&desc->irq_data)))
  951. chip->irq_cpu_offline(&desc->irq_data);
  952. raw_spin_unlock_irqrestore(&desc->lock, flags);
  953. }
  954. }
  955. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  956. #ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
  957. /**
  958. * handle_fasteoi_ack_irq - irq handler for edge hierarchy
  959. * stacked on transparent controllers
  960. *
  961. * @desc: the interrupt description structure for this irq
  962. *
  963. * Like handle_fasteoi_irq(), but for use with hierarchy where
  964. * the irq_chip also needs to have its ->irq_ack() function
  965. * called.
  966. */
  967. void handle_fasteoi_ack_irq(struct irq_desc *desc)
  968. {
  969. struct irq_chip *chip = desc->irq_data.chip;
  970. raw_spin_lock(&desc->lock);
  971. if (!irq_may_run(desc))
  972. goto out;
  973. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  974. /*
  975. * If its disabled or no action available
  976. * then mask it and get out of here:
  977. */
  978. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  979. desc->istate |= IRQS_PENDING;
  980. mask_irq(desc);
  981. goto out;
  982. }
  983. kstat_incr_irqs_this_cpu(desc);
  984. if (desc->istate & IRQS_ONESHOT)
  985. mask_irq(desc);
  986. /* Start handling the irq */
  987. desc->irq_data.chip->irq_ack(&desc->irq_data);
  988. preflow_handler(desc);
  989. handle_irq_event(desc);
  990. cond_unmask_eoi_irq(desc, chip);
  991. raw_spin_unlock(&desc->lock);
  992. return;
  993. out:
  994. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  995. chip->irq_eoi(&desc->irq_data);
  996. raw_spin_unlock(&desc->lock);
  997. }
  998. EXPORT_SYMBOL_GPL(handle_fasteoi_ack_irq);
  999. /**
  1000. * handle_fasteoi_mask_irq - irq handler for level hierarchy
  1001. * stacked on transparent controllers
  1002. *
  1003. * @desc: the interrupt description structure for this irq
  1004. *
  1005. * Like handle_fasteoi_irq(), but for use with hierarchy where
  1006. * the irq_chip also needs to have its ->irq_mask_ack() function
  1007. * called.
  1008. */
  1009. void handle_fasteoi_mask_irq(struct irq_desc *desc)
  1010. {
  1011. struct irq_chip *chip = desc->irq_data.chip;
  1012. raw_spin_lock(&desc->lock);
  1013. mask_ack_irq(desc);
  1014. if (!irq_may_run(desc))
  1015. goto out;
  1016. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  1017. /*
  1018. * If its disabled or no action available
  1019. * then mask it and get out of here:
  1020. */
  1021. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  1022. desc->istate |= IRQS_PENDING;
  1023. mask_irq(desc);
  1024. goto out;
  1025. }
  1026. kstat_incr_irqs_this_cpu(desc);
  1027. if (desc->istate & IRQS_ONESHOT)
  1028. mask_irq(desc);
  1029. preflow_handler(desc);
  1030. handle_irq_event(desc);
  1031. cond_unmask_eoi_irq(desc, chip);
  1032. raw_spin_unlock(&desc->lock);
  1033. return;
  1034. out:
  1035. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  1036. chip->irq_eoi(&desc->irq_data);
  1037. raw_spin_unlock(&desc->lock);
  1038. }
  1039. EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
  1040. #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
  1041. /**
  1042. * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  1043. * NULL)
  1044. * @data: Pointer to interrupt specific data
  1045. */
  1046. void irq_chip_enable_parent(struct irq_data *data)
  1047. {
  1048. data = data->parent_data;
  1049. if (data->chip->irq_enable)
  1050. data->chip->irq_enable(data);
  1051. else
  1052. data->chip->irq_unmask(data);
  1053. }
  1054. EXPORT_SYMBOL_GPL(irq_chip_enable_parent);
  1055. /**
  1056. * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
  1057. * NULL)
  1058. * @data: Pointer to interrupt specific data
  1059. */
  1060. void irq_chip_disable_parent(struct irq_data *data)
  1061. {
  1062. data = data->parent_data;
  1063. if (data->chip->irq_disable)
  1064. data->chip->irq_disable(data);
  1065. else
  1066. data->chip->irq_mask(data);
  1067. }
  1068. EXPORT_SYMBOL_GPL(irq_chip_disable_parent);
  1069. /**
  1070. * irq_chip_ack_parent - Acknowledge the parent interrupt
  1071. * @data: Pointer to interrupt specific data
  1072. */
  1073. void irq_chip_ack_parent(struct irq_data *data)
  1074. {
  1075. data = data->parent_data;
  1076. data->chip->irq_ack(data);
  1077. }
  1078. EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
  1079. /**
  1080. * irq_chip_mask_parent - Mask the parent interrupt
  1081. * @data: Pointer to interrupt specific data
  1082. */
  1083. void irq_chip_mask_parent(struct irq_data *data)
  1084. {
  1085. data = data->parent_data;
  1086. data->chip->irq_mask(data);
  1087. }
  1088. EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
  1089. /**
  1090. * irq_chip_unmask_parent - Unmask the parent interrupt
  1091. * @data: Pointer to interrupt specific data
  1092. */
  1093. void irq_chip_unmask_parent(struct irq_data *data)
  1094. {
  1095. data = data->parent_data;
  1096. data->chip->irq_unmask(data);
  1097. }
  1098. EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
  1099. /**
  1100. * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
  1101. * @data: Pointer to interrupt specific data
  1102. */
  1103. void irq_chip_eoi_parent(struct irq_data *data)
  1104. {
  1105. data = data->parent_data;
  1106. data->chip->irq_eoi(data);
  1107. }
  1108. EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
  1109. /**
  1110. * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
  1111. * @data: Pointer to interrupt specific data
  1112. * @dest: The affinity mask to set
  1113. * @force: Flag to enforce setting (disable online checks)
  1114. *
  1115. * Conditinal, as the underlying parent chip might not implement it.
  1116. */
  1117. int irq_chip_set_affinity_parent(struct irq_data *data,
  1118. const struct cpumask *dest, bool force)
  1119. {
  1120. data = data->parent_data;
  1121. if (data->chip->irq_set_affinity)
  1122. return data->chip->irq_set_affinity(data, dest, force);
  1123. return -ENOSYS;
  1124. }
  1125. EXPORT_SYMBOL_GPL(irq_chip_set_affinity_parent);
  1126. /**
  1127. * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
  1128. * @data: Pointer to interrupt specific data
  1129. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  1130. *
  1131. * Conditional, as the underlying parent chip might not implement it.
  1132. */
  1133. int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
  1134. {
  1135. data = data->parent_data;
  1136. if (data->chip->irq_set_type)
  1137. return data->chip->irq_set_type(data, type);
  1138. return -ENOSYS;
  1139. }
  1140. EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
  1141. /**
  1142. * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
  1143. * @data: Pointer to interrupt specific data
  1144. *
  1145. * Iterate through the domain hierarchy of the interrupt and check
  1146. * whether a hw retrigger function exists. If yes, invoke it.
  1147. */
  1148. int irq_chip_retrigger_hierarchy(struct irq_data *data)
  1149. {
  1150. for (data = data->parent_data; data; data = data->parent_data)
  1151. if (data->chip && data->chip->irq_retrigger)
  1152. return data->chip->irq_retrigger(data);
  1153. return 0;
  1154. }
  1155. /**
  1156. * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
  1157. * @data: Pointer to interrupt specific data
  1158. * @vcpu_info: The vcpu affinity information
  1159. */
  1160. int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
  1161. {
  1162. data = data->parent_data;
  1163. if (data->chip->irq_set_vcpu_affinity)
  1164. return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
  1165. return -ENOSYS;
  1166. }
  1167. /**
  1168. * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
  1169. * @data: Pointer to interrupt specific data
  1170. * @on: Whether to set or reset the wake-up capability of this irq
  1171. *
  1172. * Conditional, as the underlying parent chip might not implement it.
  1173. */
  1174. int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  1175. {
  1176. data = data->parent_data;
  1177. if (data->chip->flags & IRQCHIP_SKIP_SET_WAKE)
  1178. return 0;
  1179. if (data->chip->irq_set_wake)
  1180. return data->chip->irq_set_wake(data, on);
  1181. return -ENOSYS;
  1182. }
  1183. #endif
  1184. /**
  1185. * irq_chip_compose_msi_msg - Componse msi message for a irq chip
  1186. * @data: Pointer to interrupt specific data
  1187. * @msg: Pointer to the MSI message
  1188. *
  1189. * For hierarchical domains we find the first chip in the hierarchy
  1190. * which implements the irq_compose_msi_msg callback. For non
  1191. * hierarchical we use the top level chip.
  1192. */
  1193. int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  1194. {
  1195. struct irq_data *pos = NULL;
  1196. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  1197. for (; data; data = data->parent_data)
  1198. #endif
  1199. if (data->chip && data->chip->irq_compose_msi_msg)
  1200. pos = data;
  1201. if (!pos)
  1202. return -ENOSYS;
  1203. pos->chip->irq_compose_msi_msg(pos, msg);
  1204. return 0;
  1205. }
  1206. /**
  1207. * irq_chip_pm_get - Enable power for an IRQ chip
  1208. * @data: Pointer to interrupt specific data
  1209. *
  1210. * Enable the power to the IRQ chip referenced by the interrupt data
  1211. * structure.
  1212. */
  1213. int irq_chip_pm_get(struct irq_data *data)
  1214. {
  1215. int retval;
  1216. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
  1217. retval = pm_runtime_get_sync(data->chip->parent_device);
  1218. if (retval < 0) {
  1219. pm_runtime_put_noidle(data->chip->parent_device);
  1220. return retval;
  1221. }
  1222. }
  1223. return 0;
  1224. }
  1225. /**
  1226. * irq_chip_pm_put - Disable power for an IRQ chip
  1227. * @data: Pointer to interrupt specific data
  1228. *
  1229. * Disable the power to the IRQ chip referenced by the interrupt data
  1230. * structure, belongs. Note that power will only be disabled, once this
  1231. * function has been called for all IRQs that have called irq_chip_pm_get().
  1232. */
  1233. int irq_chip_pm_put(struct irq_data *data)
  1234. {
  1235. int retval = 0;
  1236. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
  1237. retval = pm_runtime_put(data->chip->parent_device);
  1238. return (retval < 0) ? retval : 0;
  1239. }