dw_wdt.c 8.4 KB

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  1. /*
  2. * Copyright 2010-2011 Picochip Ltd., Jamie Iles
  3. * http://www.picochip.com
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. * This file implements a driver for the Synopsys DesignWare watchdog device
  11. * in the many subsystems. The watchdog has 16 different timeout periods
  12. * and these are a function of the input clock frequency.
  13. *
  14. * The DesignWare watchdog cannot be stopped once it has been started so we
  15. * do not implement a stop function. The watchdog core will continue to send
  16. * heartbeat requests after the watchdog device has been closed.
  17. */
  18. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19. #include <linux/bitops.h>
  20. #include <linux/clk.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/io.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/of.h>
  28. #include <linux/pm.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/reset.h>
  31. #include <linux/watchdog.h>
  32. #define WDOG_CONTROL_REG_OFFSET 0x00
  33. #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
  34. #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
  35. #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
  36. #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
  37. #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
  38. #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
  39. #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
  40. /* The maximum TOP (timeout period) value that can be set in the watchdog. */
  41. #define DW_WDT_MAX_TOP 15
  42. #define DW_WDT_DEFAULT_SECONDS 30
  43. static bool nowayout = WATCHDOG_NOWAYOUT;
  44. module_param(nowayout, bool, 0);
  45. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  46. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  47. struct dw_wdt {
  48. void __iomem *regs;
  49. struct clk *clk;
  50. unsigned long rate;
  51. struct watchdog_device wdd;
  52. struct reset_control *rst;
  53. };
  54. #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
  55. static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
  56. {
  57. return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
  58. WDOG_CONTROL_REG_WDT_EN_MASK;
  59. }
  60. static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
  61. {
  62. /*
  63. * There are 16 possible timeout values in 0..15 where the number of
  64. * cycles is 2 ^ (16 + i) and the watchdog counts down.
  65. */
  66. return (1U << (16 + top)) / dw_wdt->rate;
  67. }
  68. static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
  69. {
  70. int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
  71. return dw_wdt_top_in_seconds(dw_wdt, top);
  72. }
  73. static int dw_wdt_ping(struct watchdog_device *wdd)
  74. {
  75. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  76. writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
  77. WDOG_COUNTER_RESTART_REG_OFFSET);
  78. return 0;
  79. }
  80. static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
  81. {
  82. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  83. int i, top_val = DW_WDT_MAX_TOP;
  84. /*
  85. * Iterate over the timeout values until we find the closest match. We
  86. * always look for >=.
  87. */
  88. for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
  89. if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
  90. top_val = i;
  91. break;
  92. }
  93. /*
  94. * Set the new value in the watchdog. Some versions of dw_wdt
  95. * have have TOPINIT in the TIMEOUT_RANGE register (as per
  96. * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
  97. * effectively get a pat of the watchdog right here.
  98. */
  99. writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
  100. dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  101. wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
  102. return 0;
  103. }
  104. static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
  105. {
  106. u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  107. /* Disable interrupt mode; always perform system reset. */
  108. val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
  109. /* Enable watchdog. */
  110. val |= WDOG_CONTROL_REG_WDT_EN_MASK;
  111. writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  112. }
  113. static int dw_wdt_start(struct watchdog_device *wdd)
  114. {
  115. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  116. dw_wdt_set_timeout(wdd, wdd->timeout);
  117. dw_wdt_arm_system_reset(dw_wdt);
  118. return 0;
  119. }
  120. static int dw_wdt_stop(struct watchdog_device *wdd)
  121. {
  122. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  123. if (!dw_wdt->rst) {
  124. set_bit(WDOG_HW_RUNNING, &wdd->status);
  125. return 0;
  126. }
  127. reset_control_assert(dw_wdt->rst);
  128. reset_control_deassert(dw_wdt->rst);
  129. return 0;
  130. }
  131. static int dw_wdt_restart(struct watchdog_device *wdd,
  132. unsigned long action, void *data)
  133. {
  134. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  135. writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  136. if (dw_wdt_is_enabled(dw_wdt))
  137. writel(WDOG_COUNTER_RESTART_KICK_VALUE,
  138. dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
  139. else
  140. dw_wdt_arm_system_reset(dw_wdt);
  141. /* wait for reset to assert... */
  142. mdelay(500);
  143. return 0;
  144. }
  145. static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
  146. {
  147. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  148. return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
  149. dw_wdt->rate;
  150. }
  151. static const struct watchdog_info dw_wdt_ident = {
  152. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
  153. WDIOF_MAGICCLOSE,
  154. .identity = "Synopsys DesignWare Watchdog",
  155. };
  156. static const struct watchdog_ops dw_wdt_ops = {
  157. .owner = THIS_MODULE,
  158. .start = dw_wdt_start,
  159. .stop = dw_wdt_stop,
  160. .ping = dw_wdt_ping,
  161. .set_timeout = dw_wdt_set_timeout,
  162. .get_timeleft = dw_wdt_get_timeleft,
  163. .restart = dw_wdt_restart,
  164. };
  165. #ifdef CONFIG_PM_SLEEP
  166. static int dw_wdt_suspend(struct device *dev)
  167. {
  168. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  169. clk_disable_unprepare(dw_wdt->clk);
  170. return 0;
  171. }
  172. static int dw_wdt_resume(struct device *dev)
  173. {
  174. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  175. int err = clk_prepare_enable(dw_wdt->clk);
  176. if (err)
  177. return err;
  178. dw_wdt_ping(&dw_wdt->wdd);
  179. return 0;
  180. }
  181. #endif /* CONFIG_PM_SLEEP */
  182. static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
  183. static int dw_wdt_drv_probe(struct platform_device *pdev)
  184. {
  185. struct device *dev = &pdev->dev;
  186. struct watchdog_device *wdd;
  187. struct dw_wdt *dw_wdt;
  188. struct resource *mem;
  189. int ret;
  190. dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
  191. if (!dw_wdt)
  192. return -ENOMEM;
  193. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  194. dw_wdt->regs = devm_ioremap_resource(dev, mem);
  195. if (IS_ERR(dw_wdt->regs))
  196. return PTR_ERR(dw_wdt->regs);
  197. dw_wdt->clk = devm_clk_get(dev, NULL);
  198. if (IS_ERR(dw_wdt->clk))
  199. return PTR_ERR(dw_wdt->clk);
  200. ret = clk_prepare_enable(dw_wdt->clk);
  201. if (ret)
  202. return ret;
  203. dw_wdt->rate = clk_get_rate(dw_wdt->clk);
  204. if (dw_wdt->rate == 0) {
  205. ret = -EINVAL;
  206. goto out_disable_clk;
  207. }
  208. dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  209. if (IS_ERR(dw_wdt->rst)) {
  210. ret = PTR_ERR(dw_wdt->rst);
  211. goto out_disable_clk;
  212. }
  213. reset_control_deassert(dw_wdt->rst);
  214. wdd = &dw_wdt->wdd;
  215. wdd->info = &dw_wdt_ident;
  216. wdd->ops = &dw_wdt_ops;
  217. wdd->min_timeout = 1;
  218. wdd->max_hw_heartbeat_ms =
  219. dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
  220. wdd->parent = dev;
  221. watchdog_set_drvdata(wdd, dw_wdt);
  222. watchdog_set_nowayout(wdd, nowayout);
  223. watchdog_init_timeout(wdd, 0, dev);
  224. /*
  225. * If the watchdog is already running, use its already configured
  226. * timeout. Otherwise use the default or the value provided through
  227. * devicetree.
  228. */
  229. if (dw_wdt_is_enabled(dw_wdt)) {
  230. wdd->timeout = dw_wdt_get_top(dw_wdt);
  231. set_bit(WDOG_HW_RUNNING, &wdd->status);
  232. } else {
  233. wdd->timeout = DW_WDT_DEFAULT_SECONDS;
  234. watchdog_init_timeout(wdd, 0, dev);
  235. }
  236. platform_set_drvdata(pdev, dw_wdt);
  237. watchdog_set_restart_priority(wdd, 128);
  238. ret = watchdog_register_device(wdd);
  239. if (ret)
  240. goto out_disable_clk;
  241. return 0;
  242. out_disable_clk:
  243. clk_disable_unprepare(dw_wdt->clk);
  244. return ret;
  245. }
  246. static int dw_wdt_drv_remove(struct platform_device *pdev)
  247. {
  248. struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
  249. watchdog_unregister_device(&dw_wdt->wdd);
  250. reset_control_assert(dw_wdt->rst);
  251. clk_disable_unprepare(dw_wdt->clk);
  252. return 0;
  253. }
  254. #ifdef CONFIG_OF
  255. static const struct of_device_id dw_wdt_of_match[] = {
  256. { .compatible = "snps,dw-wdt", },
  257. { /* sentinel */ }
  258. };
  259. MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
  260. #endif
  261. static struct platform_driver dw_wdt_driver = {
  262. .probe = dw_wdt_drv_probe,
  263. .remove = dw_wdt_drv_remove,
  264. .driver = {
  265. .name = "dw_wdt",
  266. .of_match_table = of_match_ptr(dw_wdt_of_match),
  267. .pm = &dw_wdt_pm_ops,
  268. },
  269. };
  270. module_platform_driver(dw_wdt_driver);
  271. MODULE_AUTHOR("Jamie Iles");
  272. MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
  273. MODULE_LICENSE("GPL");