spi-pxa2xx-pci.c 7.5 KB

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  1. /*
  2. * CE4100's SPI device is more or less the same one as found on PXA
  3. *
  4. * Copyright (C) 2016, Intel Corporation
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/pci.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/spi/pxa2xx_spi.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/platform_data/dma-dw.h>
  14. enum {
  15. PORT_QUARK_X1000,
  16. PORT_BYT,
  17. PORT_MRFLD,
  18. PORT_BSW0,
  19. PORT_BSW1,
  20. PORT_BSW2,
  21. PORT_CE4100,
  22. PORT_LPT0,
  23. PORT_LPT1,
  24. };
  25. struct pxa_spi_info {
  26. enum pxa_ssp_type type;
  27. int port_id;
  28. int num_chipselect;
  29. unsigned long max_clk_rate;
  30. /* DMA channel request parameters */
  31. bool (*dma_filter)(struct dma_chan *chan, void *param);
  32. void *tx_param;
  33. void *rx_param;
  34. int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c);
  35. };
  36. static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
  37. static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
  38. static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
  39. static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
  40. static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
  41. static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
  42. static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
  43. static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
  44. static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
  45. static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
  46. static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
  47. static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
  48. static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
  49. static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
  50. static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
  51. static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
  52. static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
  53. static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
  54. static bool lpss_dma_filter(struct dma_chan *chan, void *param)
  55. {
  56. struct dw_dma_slave *dws = param;
  57. if (dws->dma_dev != chan->device->dev)
  58. return false;
  59. chan->private = dws;
  60. return true;
  61. }
  62. static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
  63. {
  64. struct pci_dev *dma_dev;
  65. c->num_chipselect = 1;
  66. c->max_clk_rate = 50000000;
  67. dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  68. if (c->tx_param) {
  69. struct dw_dma_slave *slave = c->tx_param;
  70. slave->dma_dev = &dma_dev->dev;
  71. slave->m_master = 0;
  72. slave->p_master = 1;
  73. }
  74. if (c->rx_param) {
  75. struct dw_dma_slave *slave = c->rx_param;
  76. slave->dma_dev = &dma_dev->dev;
  77. slave->m_master = 0;
  78. slave->p_master = 1;
  79. }
  80. c->dma_filter = lpss_dma_filter;
  81. return 0;
  82. }
  83. static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
  84. {
  85. struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
  86. struct dw_dma_slave *tx, *rx;
  87. switch (PCI_FUNC(dev->devfn)) {
  88. case 0:
  89. c->port_id = 3;
  90. c->num_chipselect = 1;
  91. c->tx_param = &mrfld3_tx_param;
  92. c->rx_param = &mrfld3_rx_param;
  93. break;
  94. case 1:
  95. c->port_id = 5;
  96. c->num_chipselect = 4;
  97. c->tx_param = &mrfld5_tx_param;
  98. c->rx_param = &mrfld5_rx_param;
  99. break;
  100. case 2:
  101. c->port_id = 6;
  102. c->num_chipselect = 1;
  103. c->tx_param = &mrfld6_tx_param;
  104. c->rx_param = &mrfld6_rx_param;
  105. break;
  106. default:
  107. return -ENODEV;
  108. }
  109. tx = c->tx_param;
  110. tx->dma_dev = &dma_dev->dev;
  111. rx = c->rx_param;
  112. rx->dma_dev = &dma_dev->dev;
  113. c->dma_filter = lpss_dma_filter;
  114. return 0;
  115. }
  116. static struct pxa_spi_info spi_info_configs[] = {
  117. [PORT_CE4100] = {
  118. .type = PXA25x_SSP,
  119. .port_id = -1,
  120. .num_chipselect = -1,
  121. .max_clk_rate = 3686400,
  122. },
  123. [PORT_BYT] = {
  124. .type = LPSS_BYT_SSP,
  125. .port_id = 0,
  126. .setup = lpss_spi_setup,
  127. .tx_param = &byt_tx_param,
  128. .rx_param = &byt_rx_param,
  129. },
  130. [PORT_BSW0] = {
  131. .type = LPSS_BSW_SSP,
  132. .port_id = 0,
  133. .setup = lpss_spi_setup,
  134. .tx_param = &bsw0_tx_param,
  135. .rx_param = &bsw0_rx_param,
  136. },
  137. [PORT_BSW1] = {
  138. .type = LPSS_BSW_SSP,
  139. .port_id = 1,
  140. .setup = lpss_spi_setup,
  141. .tx_param = &bsw1_tx_param,
  142. .rx_param = &bsw1_rx_param,
  143. },
  144. [PORT_BSW2] = {
  145. .type = LPSS_BSW_SSP,
  146. .port_id = 2,
  147. .setup = lpss_spi_setup,
  148. .tx_param = &bsw2_tx_param,
  149. .rx_param = &bsw2_rx_param,
  150. },
  151. [PORT_MRFLD] = {
  152. .type = PXA27x_SSP,
  153. .max_clk_rate = 25000000,
  154. .setup = mrfld_spi_setup,
  155. },
  156. [PORT_QUARK_X1000] = {
  157. .type = QUARK_X1000_SSP,
  158. .port_id = -1,
  159. .num_chipselect = 1,
  160. .max_clk_rate = 50000000,
  161. },
  162. [PORT_LPT0] = {
  163. .type = LPSS_LPT_SSP,
  164. .port_id = 0,
  165. .setup = lpss_spi_setup,
  166. .tx_param = &lpt0_tx_param,
  167. .rx_param = &lpt0_rx_param,
  168. },
  169. [PORT_LPT1] = {
  170. .type = LPSS_LPT_SSP,
  171. .port_id = 1,
  172. .setup = lpss_spi_setup,
  173. .tx_param = &lpt1_tx_param,
  174. .rx_param = &lpt1_rx_param,
  175. },
  176. };
  177. static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
  178. const struct pci_device_id *ent)
  179. {
  180. struct platform_device_info pi;
  181. int ret;
  182. struct platform_device *pdev;
  183. struct pxa2xx_spi_master spi_pdata;
  184. struct ssp_device *ssp;
  185. struct pxa_spi_info *c;
  186. char buf[40];
  187. ret = pcim_enable_device(dev);
  188. if (ret)
  189. return ret;
  190. ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
  191. if (ret)
  192. return ret;
  193. c = &spi_info_configs[ent->driver_data];
  194. if (c->setup) {
  195. ret = c->setup(dev, c);
  196. if (ret)
  197. return ret;
  198. }
  199. memset(&spi_pdata, 0, sizeof(spi_pdata));
  200. spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn;
  201. spi_pdata.dma_filter = c->dma_filter;
  202. spi_pdata.tx_param = c->tx_param;
  203. spi_pdata.rx_param = c->rx_param;
  204. spi_pdata.enable_dma = c->rx_param && c->tx_param;
  205. ssp = &spi_pdata.ssp;
  206. ssp->phys_base = pci_resource_start(dev, 0);
  207. ssp->mmio_base = pcim_iomap_table(dev)[0];
  208. ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
  209. ssp->type = c->type;
  210. pci_set_master(dev);
  211. ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
  212. if (ret < 0)
  213. return ret;
  214. ssp->irq = pci_irq_vector(dev, 0);
  215. snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
  216. ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0,
  217. c->max_clk_rate);
  218. if (IS_ERR(ssp->clk))
  219. return PTR_ERR(ssp->clk);
  220. memset(&pi, 0, sizeof(pi));
  221. pi.fwnode = dev->dev.fwnode;
  222. pi.parent = &dev->dev;
  223. pi.name = "pxa2xx-spi";
  224. pi.id = ssp->port_id;
  225. pi.data = &spi_pdata;
  226. pi.size_data = sizeof(spi_pdata);
  227. pdev = platform_device_register_full(&pi);
  228. if (IS_ERR(pdev)) {
  229. clk_unregister(ssp->clk);
  230. return PTR_ERR(pdev);
  231. }
  232. pci_set_drvdata(dev, pdev);
  233. return 0;
  234. }
  235. static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
  236. {
  237. struct platform_device *pdev = pci_get_drvdata(dev);
  238. struct pxa2xx_spi_master *spi_pdata;
  239. spi_pdata = dev_get_platdata(&pdev->dev);
  240. platform_device_unregister(pdev);
  241. clk_unregister(spi_pdata->ssp.clk);
  242. }
  243. static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
  244. { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
  245. { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
  246. { PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
  247. { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
  248. { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
  249. { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
  250. { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
  251. { PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
  252. { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
  253. { }
  254. };
  255. MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
  256. static struct pci_driver pxa2xx_spi_pci_driver = {
  257. .name = "pxa2xx_spi_pci",
  258. .id_table = pxa2xx_spi_pci_devices,
  259. .probe = pxa2xx_spi_pci_probe,
  260. .remove = pxa2xx_spi_pci_remove,
  261. };
  262. module_pci_driver(pxa2xx_spi_pci_driver);
  263. MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
  264. MODULE_LICENSE("GPL v2");
  265. MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");