qla_tmpl.c 27 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_tmpl.h"
  9. /* note default template is in big endian */
  10. static const uint32_t ql27xx_fwdt_default_template[] = {
  11. 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
  12. 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
  13. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  14. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  15. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  16. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  17. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  18. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  19. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  20. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  21. 0x00000000, 0x04010000, 0x14000000, 0x00000000,
  22. 0x02000000, 0x44000000, 0x09010000, 0x10000000,
  23. 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
  24. 0x00000000, 0x02000000, 0x00600000, 0x00000000,
  25. 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
  26. 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
  27. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  28. 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
  29. 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
  30. 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
  31. 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
  32. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  33. 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
  34. 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
  35. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  36. 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
  37. 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
  38. 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
  39. 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
  40. 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
  41. 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
  42. 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
  43. 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
  44. 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
  45. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  46. 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
  47. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  48. 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
  49. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  50. 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
  51. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  52. 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
  53. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  54. 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
  55. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  56. 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
  57. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  58. 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
  59. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  60. 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
  61. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  62. 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
  63. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  64. 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
  65. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  66. 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
  67. 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
  68. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  69. 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
  70. 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
  71. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  72. 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
  73. 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
  74. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  75. 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
  76. 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
  77. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  78. 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
  79. 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
  80. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  81. 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
  82. 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
  83. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  84. 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
  85. 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
  86. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  87. 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
  88. 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
  89. 0x00000000, 0x02000000, 0x01000000, 0x00000200,
  90. 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
  91. 0x02000000, 0x02000000, 0x00001000, 0x00000000,
  92. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  93. 0x00000000, 0x01000000, 0x07010000, 0x18000000,
  94. 0x00000000, 0x02000000, 0x00000000, 0x02000000,
  95. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  96. 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
  97. 0x00000000, 0x02000000, 0x00000000, 0xff000000,
  98. 0x10000000, 0x00000000, 0x00000080,
  99. };
  100. static inline void __iomem *
  101. qla27xx_isp_reg(struct scsi_qla_host *vha)
  102. {
  103. return &vha->hw->iobase->isp24;
  104. }
  105. static inline void
  106. qla27xx_insert16(uint16_t value, void *buf, ulong *len)
  107. {
  108. if (buf) {
  109. buf += *len;
  110. *(__le16 *)buf = cpu_to_le16(value);
  111. }
  112. *len += sizeof(value);
  113. }
  114. static inline void
  115. qla27xx_insert32(uint32_t value, void *buf, ulong *len)
  116. {
  117. if (buf) {
  118. buf += *len;
  119. *(__le32 *)buf = cpu_to_le32(value);
  120. }
  121. *len += sizeof(value);
  122. }
  123. static inline void
  124. qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
  125. {
  126. if (buf && mem && size) {
  127. buf += *len;
  128. memcpy(buf, mem, size);
  129. }
  130. *len += size;
  131. }
  132. static inline void
  133. qla27xx_read8(void __iomem *window, void *buf, ulong *len)
  134. {
  135. uint8_t value = ~0;
  136. if (buf) {
  137. value = RD_REG_BYTE(window);
  138. }
  139. qla27xx_insert32(value, buf, len);
  140. }
  141. static inline void
  142. qla27xx_read16(void __iomem *window, void *buf, ulong *len)
  143. {
  144. uint16_t value = ~0;
  145. if (buf) {
  146. value = RD_REG_WORD(window);
  147. }
  148. qla27xx_insert32(value, buf, len);
  149. }
  150. static inline void
  151. qla27xx_read32(void __iomem *window, void *buf, ulong *len)
  152. {
  153. uint32_t value = ~0;
  154. if (buf) {
  155. value = RD_REG_DWORD(window);
  156. }
  157. qla27xx_insert32(value, buf, len);
  158. }
  159. static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *)
  160. {
  161. return
  162. (width == 1) ? qla27xx_read8 :
  163. (width == 2) ? qla27xx_read16 :
  164. qla27xx_read32;
  165. }
  166. static inline void
  167. qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
  168. uint offset, void *buf, ulong *len)
  169. {
  170. void __iomem *window = (void __iomem *)reg + offset;
  171. qla27xx_read32(window, buf, len);
  172. }
  173. static inline void
  174. qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
  175. uint offset, uint32_t data, void *buf)
  176. {
  177. __iomem void *window = (void __iomem *)reg + offset;
  178. if (buf) {
  179. WRT_REG_DWORD(window, data);
  180. }
  181. }
  182. static inline void
  183. qla27xx_read_window(__iomem struct device_reg_24xx *reg,
  184. uint32_t addr, uint offset, uint count, uint width, void *buf,
  185. ulong *len)
  186. {
  187. void __iomem *window = (void __iomem *)reg + offset;
  188. void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
  189. qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
  190. while (count--) {
  191. qla27xx_insert32(addr, buf, len);
  192. readn(window, buf, len);
  193. window += width;
  194. addr++;
  195. }
  196. }
  197. static inline void
  198. qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
  199. {
  200. if (buf)
  201. ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
  202. }
  203. static int
  204. qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
  205. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  206. {
  207. ql_dbg(ql_dbg_misc, vha, 0xd100,
  208. "%s: nop [%lx]\n", __func__, *len);
  209. qla27xx_skip_entry(ent, buf);
  210. return false;
  211. }
  212. static int
  213. qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
  214. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  215. {
  216. ql_dbg(ql_dbg_misc, vha, 0xd1ff,
  217. "%s: end [%lx]\n", __func__, *len);
  218. qla27xx_skip_entry(ent, buf);
  219. /* terminate */
  220. return true;
  221. }
  222. static int
  223. qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
  224. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  225. {
  226. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  227. ql_dbg(ql_dbg_misc, vha, 0xd200,
  228. "%s: rdio t1 [%lx]\n", __func__, *len);
  229. qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
  230. ent->t256.reg_count, ent->t256.reg_width, buf, len);
  231. return false;
  232. }
  233. static int
  234. qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
  235. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  236. {
  237. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  238. ql_dbg(ql_dbg_misc, vha, 0xd201,
  239. "%s: wrio t1 [%lx]\n", __func__, *len);
  240. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
  241. qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
  242. return false;
  243. }
  244. static int
  245. qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
  246. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  247. {
  248. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  249. ql_dbg(ql_dbg_misc, vha, 0xd202,
  250. "%s: rdio t2 [%lx]\n", __func__, *len);
  251. qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
  252. qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
  253. ent->t258.reg_count, ent->t258.reg_width, buf, len);
  254. return false;
  255. }
  256. static int
  257. qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
  258. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  259. {
  260. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  261. ql_dbg(ql_dbg_misc, vha, 0xd203,
  262. "%s: wrio t2 [%lx]\n", __func__, *len);
  263. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
  264. qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
  265. qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
  266. return false;
  267. }
  268. static int
  269. qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
  270. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  271. {
  272. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  273. ql_dbg(ql_dbg_misc, vha, 0xd204,
  274. "%s: rdpci [%lx]\n", __func__, *len);
  275. qla27xx_insert32(ent->t260.pci_offset, buf, len);
  276. qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
  277. return false;
  278. }
  279. static int
  280. qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
  281. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  282. {
  283. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  284. ql_dbg(ql_dbg_misc, vha, 0xd205,
  285. "%s: wrpci [%lx]\n", __func__, *len);
  286. qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
  287. return false;
  288. }
  289. static int
  290. qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
  291. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  292. {
  293. ulong dwords;
  294. ulong start;
  295. ulong end;
  296. ql_dbg(ql_dbg_misc, vha, 0xd206,
  297. "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
  298. start = ent->t262.start_addr;
  299. end = ent->t262.end_addr;
  300. if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
  301. ;
  302. } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
  303. end = vha->hw->fw_memory_size;
  304. if (buf)
  305. ent->t262.end_addr = end;
  306. } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
  307. start = vha->hw->fw_shared_ram_start;
  308. end = vha->hw->fw_shared_ram_end;
  309. if (buf) {
  310. ent->t262.start_addr = start;
  311. ent->t262.end_addr = end;
  312. }
  313. } else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
  314. start = vha->hw->fw_ddr_ram_start;
  315. end = vha->hw->fw_ddr_ram_end;
  316. if (buf) {
  317. ent->t262.start_addr = start;
  318. ent->t262.end_addr = end;
  319. }
  320. } else {
  321. ql_dbg(ql_dbg_misc, vha, 0xd022,
  322. "%s: unknown area %x\n", __func__, ent->t262.ram_area);
  323. qla27xx_skip_entry(ent, buf);
  324. goto done;
  325. }
  326. if (end < start || start == 0 || end == 0) {
  327. ql_dbg(ql_dbg_misc, vha, 0xd023,
  328. "%s: unusable range (start=%x end=%x)\n", __func__,
  329. ent->t262.end_addr, ent->t262.start_addr);
  330. qla27xx_skip_entry(ent, buf);
  331. goto done;
  332. }
  333. dwords = end - start + 1;
  334. if (buf) {
  335. buf += *len;
  336. qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
  337. }
  338. *len += dwords * sizeof(uint32_t);
  339. done:
  340. return false;
  341. }
  342. static int
  343. qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
  344. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  345. {
  346. uint count = 0;
  347. uint i;
  348. uint length;
  349. ql_dbg(ql_dbg_misc, vha, 0xd207,
  350. "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
  351. if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
  352. for (i = 0; i < vha->hw->max_req_queues; i++) {
  353. struct req_que *req = vha->hw->req_q_map[i];
  354. if (req || !buf) {
  355. length = req ?
  356. req->length : REQUEST_ENTRY_CNT_24XX;
  357. qla27xx_insert16(i, buf, len);
  358. qla27xx_insert16(length, buf, len);
  359. qla27xx_insertbuf(req ? req->ring : NULL,
  360. length * sizeof(*req->ring), buf, len);
  361. count++;
  362. }
  363. }
  364. } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
  365. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  366. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  367. if (rsp || !buf) {
  368. length = rsp ?
  369. rsp->length : RESPONSE_ENTRY_CNT_MQ;
  370. qla27xx_insert16(i, buf, len);
  371. qla27xx_insert16(length, buf, len);
  372. qla27xx_insertbuf(rsp ? rsp->ring : NULL,
  373. length * sizeof(*rsp->ring), buf, len);
  374. count++;
  375. }
  376. }
  377. } else if (QLA_TGT_MODE_ENABLED() &&
  378. ent->t263.queue_type == T263_QUEUE_TYPE_ATIO) {
  379. struct qla_hw_data *ha = vha->hw;
  380. struct atio *atr = ha->tgt.atio_ring;
  381. if (atr || !buf) {
  382. length = ha->tgt.atio_q_length;
  383. qla27xx_insert16(0, buf, len);
  384. qla27xx_insert16(length, buf, len);
  385. qla27xx_insertbuf(atr, length * sizeof(*atr), buf, len);
  386. count++;
  387. }
  388. } else {
  389. ql_dbg(ql_dbg_misc, vha, 0xd026,
  390. "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
  391. qla27xx_skip_entry(ent, buf);
  392. }
  393. if (buf) {
  394. if (count)
  395. ent->t263.num_queues = count;
  396. else
  397. qla27xx_skip_entry(ent, buf);
  398. }
  399. return false;
  400. }
  401. static int
  402. qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
  403. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  404. {
  405. ql_dbg(ql_dbg_misc, vha, 0xd208,
  406. "%s: getfce [%lx]\n", __func__, *len);
  407. if (vha->hw->fce) {
  408. if (buf) {
  409. ent->t264.fce_trace_size = FCE_SIZE;
  410. ent->t264.write_pointer = vha->hw->fce_wr;
  411. ent->t264.base_pointer = vha->hw->fce_dma;
  412. ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
  413. ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
  414. ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
  415. ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
  416. ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
  417. ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
  418. }
  419. qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
  420. } else {
  421. ql_dbg(ql_dbg_misc, vha, 0xd027,
  422. "%s: missing fce\n", __func__);
  423. qla27xx_skip_entry(ent, buf);
  424. }
  425. return false;
  426. }
  427. static int
  428. qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
  429. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  430. {
  431. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  432. ql_dbg(ql_dbg_misc, vha, 0xd209,
  433. "%s: pause risc [%lx]\n", __func__, *len);
  434. if (buf)
  435. qla24xx_pause_risc(reg, vha->hw);
  436. return false;
  437. }
  438. static int
  439. qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
  440. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  441. {
  442. ql_dbg(ql_dbg_misc, vha, 0xd20a,
  443. "%s: reset risc [%lx]\n", __func__, *len);
  444. if (buf)
  445. qla24xx_soft_reset(vha->hw);
  446. return false;
  447. }
  448. static int
  449. qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
  450. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  451. {
  452. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  453. ql_dbg(ql_dbg_misc, vha, 0xd20b,
  454. "%s: dis intr [%lx]\n", __func__, *len);
  455. qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
  456. return false;
  457. }
  458. static int
  459. qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
  460. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  461. {
  462. ql_dbg(ql_dbg_misc, vha, 0xd20c,
  463. "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
  464. if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
  465. if (vha->hw->eft) {
  466. if (buf) {
  467. ent->t268.buf_size = EFT_SIZE;
  468. ent->t268.start_addr = vha->hw->eft_dma;
  469. }
  470. qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
  471. } else {
  472. ql_dbg(ql_dbg_misc, vha, 0xd028,
  473. "%s: missing eft\n", __func__);
  474. qla27xx_skip_entry(ent, buf);
  475. }
  476. } else {
  477. ql_dbg(ql_dbg_misc, vha, 0xd02b,
  478. "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
  479. qla27xx_skip_entry(ent, buf);
  480. }
  481. return false;
  482. }
  483. static int
  484. qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
  485. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  486. {
  487. ql_dbg(ql_dbg_misc, vha, 0xd20d,
  488. "%s: scratch [%lx]\n", __func__, *len);
  489. qla27xx_insert32(0xaaaaaaaa, buf, len);
  490. qla27xx_insert32(0xbbbbbbbb, buf, len);
  491. qla27xx_insert32(0xcccccccc, buf, len);
  492. qla27xx_insert32(0xdddddddd, buf, len);
  493. qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
  494. if (buf)
  495. ent->t269.scratch_size = 5 * sizeof(uint32_t);
  496. return false;
  497. }
  498. static int
  499. qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
  500. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  501. {
  502. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  503. ulong dwords = ent->t270.count;
  504. ulong addr = ent->t270.addr;
  505. ql_dbg(ql_dbg_misc, vha, 0xd20e,
  506. "%s: rdremreg [%lx]\n", __func__, *len);
  507. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  508. while (dwords--) {
  509. qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
  510. qla27xx_insert32(addr, buf, len);
  511. qla27xx_read_reg(reg, 0xc4, buf, len);
  512. addr += sizeof(uint32_t);
  513. }
  514. return false;
  515. }
  516. static int
  517. qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
  518. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  519. {
  520. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  521. ulong addr = ent->t271.addr;
  522. ulong data = ent->t271.data;
  523. ql_dbg(ql_dbg_misc, vha, 0xd20f,
  524. "%s: wrremreg [%lx]\n", __func__, *len);
  525. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  526. qla27xx_write_reg(reg, 0xc4, data, buf);
  527. qla27xx_write_reg(reg, 0xc0, addr, buf);
  528. return false;
  529. }
  530. static int
  531. qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
  532. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  533. {
  534. ulong dwords = ent->t272.count;
  535. ulong start = ent->t272.addr;
  536. ql_dbg(ql_dbg_misc, vha, 0xd210,
  537. "%s: rdremram [%lx]\n", __func__, *len);
  538. if (buf) {
  539. ql_dbg(ql_dbg_misc, vha, 0xd02c,
  540. "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
  541. buf += *len;
  542. qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
  543. }
  544. *len += dwords * sizeof(uint32_t);
  545. return false;
  546. }
  547. static int
  548. qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
  549. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  550. {
  551. ulong dwords = ent->t273.count;
  552. ulong addr = ent->t273.addr;
  553. uint32_t value;
  554. ql_dbg(ql_dbg_misc, vha, 0xd211,
  555. "%s: pcicfg [%lx]\n", __func__, *len);
  556. while (dwords--) {
  557. value = ~0;
  558. if (pci_read_config_dword(vha->hw->pdev, addr, &value))
  559. ql_dbg(ql_dbg_misc, vha, 0xd02d,
  560. "%s: failed pcicfg read at %lx\n", __func__, addr);
  561. qla27xx_insert32(addr, buf, len);
  562. qla27xx_insert32(value, buf, len);
  563. addr += sizeof(uint32_t);
  564. }
  565. return false;
  566. }
  567. static int
  568. qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
  569. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  570. {
  571. uint count = 0;
  572. uint i;
  573. ql_dbg(ql_dbg_misc, vha, 0xd212,
  574. "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
  575. if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
  576. for (i = 0; i < vha->hw->max_req_queues; i++) {
  577. struct req_que *req = vha->hw->req_q_map[i];
  578. if (req || !buf) {
  579. qla27xx_insert16(i, buf, len);
  580. qla27xx_insert16(1, buf, len);
  581. qla27xx_insert32(req && req->out_ptr ?
  582. *req->out_ptr : 0, buf, len);
  583. count++;
  584. }
  585. }
  586. } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
  587. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  588. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  589. if (rsp || !buf) {
  590. qla27xx_insert16(i, buf, len);
  591. qla27xx_insert16(1, buf, len);
  592. qla27xx_insert32(rsp && rsp->in_ptr ?
  593. *rsp->in_ptr : 0, buf, len);
  594. count++;
  595. }
  596. }
  597. } else if (QLA_TGT_MODE_ENABLED() &&
  598. ent->t274.queue_type == T274_QUEUE_TYPE_ATIO_SHAD) {
  599. struct qla_hw_data *ha = vha->hw;
  600. struct atio *atr = ha->tgt.atio_ring_ptr;
  601. if (atr || !buf) {
  602. qla27xx_insert16(0, buf, len);
  603. qla27xx_insert16(1, buf, len);
  604. qla27xx_insert32(ha->tgt.atio_q_in ?
  605. readl(ha->tgt.atio_q_in) : 0, buf, len);
  606. count++;
  607. }
  608. } else {
  609. ql_dbg(ql_dbg_misc, vha, 0xd02f,
  610. "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
  611. qla27xx_skip_entry(ent, buf);
  612. }
  613. if (buf) {
  614. if (count)
  615. ent->t274.num_queues = count;
  616. else
  617. qla27xx_skip_entry(ent, buf);
  618. }
  619. return false;
  620. }
  621. static int
  622. qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
  623. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  624. {
  625. ulong offset = offsetof(typeof(*ent), t275.buffer);
  626. ql_dbg(ql_dbg_misc, vha, 0xd213,
  627. "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
  628. if (!ent->t275.length) {
  629. ql_dbg(ql_dbg_misc, vha, 0xd020,
  630. "%s: buffer zero length\n", __func__);
  631. qla27xx_skip_entry(ent, buf);
  632. goto done;
  633. }
  634. if (offset + ent->t275.length > ent->hdr.entry_size) {
  635. ql_dbg(ql_dbg_misc, vha, 0xd030,
  636. "%s: buffer overflow\n", __func__);
  637. qla27xx_skip_entry(ent, buf);
  638. goto done;
  639. }
  640. qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
  641. done:
  642. return false;
  643. }
  644. static int
  645. qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
  646. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  647. {
  648. ql_dbg(ql_dbg_misc, vha, 0xd2ff,
  649. "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
  650. qla27xx_skip_entry(ent, buf);
  651. return false;
  652. }
  653. struct qla27xx_fwdt_entry_call {
  654. uint type;
  655. int (*call)(
  656. struct scsi_qla_host *,
  657. struct qla27xx_fwdt_entry *,
  658. void *,
  659. ulong *);
  660. };
  661. static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
  662. { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
  663. { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
  664. { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
  665. { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
  666. { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
  667. { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
  668. { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
  669. { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
  670. { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
  671. { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
  672. { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
  673. { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
  674. { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
  675. { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
  676. { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
  677. { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
  678. { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
  679. { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
  680. { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
  681. { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
  682. { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
  683. { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
  684. { -1 , qla27xx_fwdt_entry_other }
  685. };
  686. static inline int (*qla27xx_find_entry(uint type))
  687. (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
  688. {
  689. struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
  690. while (list->type < type)
  691. list++;
  692. if (list->type == type)
  693. return list->call;
  694. return qla27xx_fwdt_entry_other;
  695. }
  696. static inline void *
  697. qla27xx_next_entry(void *p)
  698. {
  699. struct qla27xx_fwdt_entry *ent = p;
  700. return p + ent->hdr.entry_size;
  701. }
  702. static void
  703. qla27xx_walk_template(struct scsi_qla_host *vha,
  704. struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
  705. {
  706. struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
  707. ulong count = tmp->entry_count;
  708. ql_dbg(ql_dbg_misc, vha, 0xd01a,
  709. "%s: entry count %lx\n", __func__, count);
  710. while (count--) {
  711. if (buf && *len >= vha->hw->fw_dump_len)
  712. break;
  713. if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
  714. break;
  715. ent = qla27xx_next_entry(ent);
  716. }
  717. if (count)
  718. ql_dbg(ql_dbg_misc, vha, 0xd018,
  719. "%s: entry residual count (%lx)\n", __func__, count);
  720. if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
  721. ql_dbg(ql_dbg_misc, vha, 0xd019,
  722. "%s: missing end entry (%lx)\n", __func__, count);
  723. if (buf && *len != vha->hw->fw_dump_len)
  724. ql_dbg(ql_dbg_misc, vha, 0xd01b,
  725. "%s: length=%#lx residual=%+ld\n",
  726. __func__, *len, vha->hw->fw_dump_len - *len);
  727. if (buf) {
  728. ql_log(ql_log_warn, vha, 0xd015,
  729. "Firmware dump saved to temp buffer (%lu/%p)\n",
  730. vha->host_no, vha->hw->fw_dump);
  731. qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
  732. }
  733. }
  734. static void
  735. qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
  736. {
  737. tmp->capture_timestamp = jiffies;
  738. }
  739. static void
  740. qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
  741. {
  742. uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
  743. sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
  744. v+0, v+1, v+2, v+3, v+4, v+5);
  745. tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
  746. tmp->driver_info[1] = v[5] << 8 | v[4];
  747. tmp->driver_info[2] = 0x12345678;
  748. }
  749. static void
  750. qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
  751. struct scsi_qla_host *vha)
  752. {
  753. tmp->firmware_version[0] = vha->hw->fw_major_version;
  754. tmp->firmware_version[1] = vha->hw->fw_minor_version;
  755. tmp->firmware_version[2] = vha->hw->fw_subminor_version;
  756. tmp->firmware_version[3] =
  757. vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
  758. tmp->firmware_version[4] =
  759. vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
  760. }
  761. static void
  762. ql27xx_edit_template(struct scsi_qla_host *vha,
  763. struct qla27xx_fwdt_template *tmp)
  764. {
  765. qla27xx_time_stamp(tmp);
  766. qla27xx_driver_info(tmp);
  767. qla27xx_firmware_info(tmp, vha);
  768. }
  769. static inline uint32_t
  770. qla27xx_template_checksum(void *p, ulong size)
  771. {
  772. uint32_t *buf = p;
  773. uint64_t sum = 0;
  774. size /= sizeof(*buf);
  775. while (size--)
  776. sum += *buf++;
  777. sum = (sum & 0xffffffff) + (sum >> 32);
  778. return ~sum;
  779. }
  780. static inline int
  781. qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
  782. {
  783. return qla27xx_template_checksum(tmp,
  784. le32_to_cpu(tmp->template_size)) == 0;
  785. }
  786. static inline int
  787. qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
  788. {
  789. return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
  790. }
  791. static void
  792. qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
  793. {
  794. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  795. ulong len;
  796. if (qla27xx_fwdt_template_valid(tmp)) {
  797. len = le32_to_cpu(tmp->template_size);
  798. tmp = memcpy(vha->hw->fw_dump, tmp, len);
  799. ql27xx_edit_template(vha, tmp);
  800. qla27xx_walk_template(vha, tmp, tmp, &len);
  801. vha->hw->fw_dump_len = len;
  802. vha->hw->fw_dumped = 1;
  803. }
  804. }
  805. ulong
  806. qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
  807. {
  808. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  809. ulong len = 0;
  810. if (qla27xx_fwdt_template_valid(tmp)) {
  811. len = le32_to_cpu(tmp->template_size);
  812. qla27xx_walk_template(vha, tmp, NULL, &len);
  813. }
  814. return len;
  815. }
  816. ulong
  817. qla27xx_fwdt_template_size(void *p)
  818. {
  819. struct qla27xx_fwdt_template *tmp = p;
  820. return le32_to_cpu(tmp->template_size);
  821. }
  822. ulong
  823. qla27xx_fwdt_template_default_size(void)
  824. {
  825. return sizeof(ql27xx_fwdt_default_template);
  826. }
  827. const void *
  828. qla27xx_fwdt_template_default(void)
  829. {
  830. return ql27xx_fwdt_default_template;
  831. }
  832. int
  833. qla27xx_fwdt_template_valid(void *p)
  834. {
  835. struct qla27xx_fwdt_template *tmp = p;
  836. if (!qla27xx_verify_template_header(tmp)) {
  837. ql_log(ql_log_warn, NULL, 0xd01c,
  838. "%s: template type %x\n", __func__, tmp->template_type);
  839. return false;
  840. }
  841. if (!qla27xx_verify_template_checksum(tmp)) {
  842. ql_log(ql_log_warn, NULL, 0xd01d,
  843. "%s: failed template checksum\n", __func__);
  844. return false;
  845. }
  846. return true;
  847. }
  848. void
  849. qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
  850. {
  851. ulong flags = 0;
  852. #ifndef __CHECKER__
  853. if (!hardware_locked)
  854. spin_lock_irqsave(&vha->hw->hardware_lock, flags);
  855. #endif
  856. if (!vha->hw->fw_dump)
  857. ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
  858. else if (!vha->hw->fw_dump_template)
  859. ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
  860. else if (vha->hw->fw_dumped)
  861. ql_log(ql_log_warn, vha, 0xd300,
  862. "Firmware has been previously dumped (%p),"
  863. " -- ignoring request\n", vha->hw->fw_dump);
  864. else
  865. qla27xx_execute_fwdt_template(vha);
  866. #ifndef __CHECKER__
  867. if (!hardware_locked)
  868. spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
  869. #endif
  870. }