reset-socfpga.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158
  1. /*
  2. * Socfpga Reset Controller Driver
  3. *
  4. * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  5. *
  6. * based on
  7. * Allwinner SoCs Reset Controller driver
  8. *
  9. * Copyright 2013 Maxime Ripard
  10. *
  11. * Maxime Ripard <maxime.ripard@free-electrons.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. */
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/init.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reset-controller.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/types.h>
  26. #define BANK_INCREMENT 4
  27. #define NR_BANKS 8
  28. struct socfpga_reset_data {
  29. spinlock_t lock;
  30. void __iomem *membase;
  31. struct reset_controller_dev rcdev;
  32. };
  33. static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
  34. unsigned long id)
  35. {
  36. struct socfpga_reset_data *data = container_of(rcdev,
  37. struct socfpga_reset_data,
  38. rcdev);
  39. int reg_width = sizeof(u32);
  40. int bank = id / (reg_width * BITS_PER_BYTE);
  41. int offset = id % (reg_width * BITS_PER_BYTE);
  42. unsigned long flags;
  43. u32 reg;
  44. spin_lock_irqsave(&data->lock, flags);
  45. reg = readl(data->membase + (bank * BANK_INCREMENT));
  46. writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
  47. spin_unlock_irqrestore(&data->lock, flags);
  48. return 0;
  49. }
  50. static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
  51. unsigned long id)
  52. {
  53. struct socfpga_reset_data *data = container_of(rcdev,
  54. struct socfpga_reset_data,
  55. rcdev);
  56. int reg_width = sizeof(u32);
  57. int bank = id / (reg_width * BITS_PER_BYTE);
  58. int offset = id % (reg_width * BITS_PER_BYTE);
  59. unsigned long flags;
  60. u32 reg;
  61. spin_lock_irqsave(&data->lock, flags);
  62. reg = readl(data->membase + (bank * BANK_INCREMENT));
  63. writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
  64. spin_unlock_irqrestore(&data->lock, flags);
  65. return 0;
  66. }
  67. static int socfpga_reset_status(struct reset_controller_dev *rcdev,
  68. unsigned long id)
  69. {
  70. struct socfpga_reset_data *data = container_of(rcdev,
  71. struct socfpga_reset_data, rcdev);
  72. int reg_width = sizeof(u32);
  73. int bank = id / (reg_width * BITS_PER_BYTE);
  74. int offset = id % (reg_width * BITS_PER_BYTE);
  75. u32 reg;
  76. reg = readl(data->membase + (bank * BANK_INCREMENT));
  77. return !(reg & BIT(offset));
  78. }
  79. static const struct reset_control_ops socfpga_reset_ops = {
  80. .assert = socfpga_reset_assert,
  81. .deassert = socfpga_reset_deassert,
  82. .status = socfpga_reset_status,
  83. };
  84. static int socfpga_reset_probe(struct platform_device *pdev)
  85. {
  86. struct socfpga_reset_data *data;
  87. struct resource *res;
  88. struct device *dev = &pdev->dev;
  89. struct device_node *np = dev->of_node;
  90. u32 modrst_offset;
  91. /*
  92. * The binding was mainlined without the required property.
  93. * Do not continue, when we encounter an old DT.
  94. */
  95. if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
  96. dev_err(&pdev->dev, "%pOF missing #reset-cells property\n",
  97. pdev->dev.of_node);
  98. return -EINVAL;
  99. }
  100. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  101. if (!data)
  102. return -ENOMEM;
  103. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  104. data->membase = devm_ioremap_resource(&pdev->dev, res);
  105. if (IS_ERR(data->membase))
  106. return PTR_ERR(data->membase);
  107. if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
  108. dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
  109. modrst_offset = 0x10;
  110. }
  111. data->membase += modrst_offset;
  112. spin_lock_init(&data->lock);
  113. data->rcdev.owner = THIS_MODULE;
  114. data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
  115. data->rcdev.ops = &socfpga_reset_ops;
  116. data->rcdev.of_node = pdev->dev.of_node;
  117. return devm_reset_controller_register(dev, &data->rcdev);
  118. }
  119. static const struct of_device_id socfpga_reset_dt_ids[] = {
  120. { .compatible = "altr,rst-mgr", },
  121. { /* sentinel */ },
  122. };
  123. static struct platform_driver socfpga_reset_driver = {
  124. .probe = socfpga_reset_probe,
  125. .driver = {
  126. .name = "socfpga-reset",
  127. .of_match_table = socfpga_reset_dt_ids,
  128. },
  129. };
  130. builtin_platform_driver(socfpga_reset_driver);