reset-imx7.c 4.8 KB

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  1. /*
  2. * Copyright (c) 2017, Impinj, Inc.
  3. *
  4. * i.MX7 System Reset Controller (SRC) driver
  5. *
  6. * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset-controller.h>
  20. #include <linux/regmap.h>
  21. #include <dt-bindings/reset/imx7-reset.h>
  22. struct imx7_src {
  23. struct reset_controller_dev rcdev;
  24. struct regmap *regmap;
  25. };
  26. enum imx7_src_registers {
  27. SRC_A7RCR0 = 0x0004,
  28. SRC_M4RCR = 0x000c,
  29. SRC_ERCR = 0x0014,
  30. SRC_HSICPHY_RCR = 0x001c,
  31. SRC_USBOPHY1_RCR = 0x0020,
  32. SRC_USBOPHY2_RCR = 0x0024,
  33. SRC_MIPIPHY_RCR = 0x0028,
  34. SRC_PCIEPHY_RCR = 0x002c,
  35. SRC_DDRC_RCR = 0x1000,
  36. };
  37. struct imx7_src_signal {
  38. unsigned int offset, bit;
  39. };
  40. static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
  41. [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
  42. [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
  43. [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
  44. [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
  45. [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
  46. [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
  47. [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
  48. [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
  49. [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
  50. [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
  51. [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
  52. [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
  53. [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
  54. [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
  55. [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
  56. [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
  57. [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
  58. [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
  59. [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
  60. [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
  61. [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
  62. [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  63. [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  64. [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
  65. [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
  66. };
  67. static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
  68. {
  69. return container_of(rcdev, struct imx7_src, rcdev);
  70. }
  71. static int imx7_reset_set(struct reset_controller_dev *rcdev,
  72. unsigned long id, bool assert)
  73. {
  74. struct imx7_src *imx7src = to_imx7_src(rcdev);
  75. const struct imx7_src_signal *signal = &imx7_src_signals[id];
  76. unsigned int value = assert ? signal->bit : 0;
  77. switch (id) {
  78. case IMX7_RESET_PCIEPHY:
  79. /*
  80. * wait for more than 10us to release phy g_rst and
  81. * btnrst
  82. */
  83. if (!assert)
  84. udelay(10);
  85. break;
  86. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  87. value = (assert) ? 0 : signal->bit;
  88. break;
  89. }
  90. return regmap_update_bits(imx7src->regmap,
  91. signal->offset, signal->bit, value);
  92. }
  93. static int imx7_reset_assert(struct reset_controller_dev *rcdev,
  94. unsigned long id)
  95. {
  96. return imx7_reset_set(rcdev, id, true);
  97. }
  98. static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
  99. unsigned long id)
  100. {
  101. return imx7_reset_set(rcdev, id, false);
  102. }
  103. static const struct reset_control_ops imx7_reset_ops = {
  104. .assert = imx7_reset_assert,
  105. .deassert = imx7_reset_deassert,
  106. };
  107. static int imx7_reset_probe(struct platform_device *pdev)
  108. {
  109. struct imx7_src *imx7src;
  110. struct device *dev = &pdev->dev;
  111. struct regmap_config config = { .name = "src" };
  112. imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
  113. if (!imx7src)
  114. return -ENOMEM;
  115. imx7src->regmap = syscon_node_to_regmap(dev->of_node);
  116. if (IS_ERR(imx7src->regmap)) {
  117. dev_err(dev, "Unable to get imx7-src regmap");
  118. return PTR_ERR(imx7src->regmap);
  119. }
  120. regmap_attach_dev(dev, imx7src->regmap, &config);
  121. imx7src->rcdev.owner = THIS_MODULE;
  122. imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
  123. imx7src->rcdev.ops = &imx7_reset_ops;
  124. imx7src->rcdev.of_node = dev->of_node;
  125. return devm_reset_controller_register(dev, &imx7src->rcdev);
  126. }
  127. static const struct of_device_id imx7_reset_dt_ids[] = {
  128. { .compatible = "fsl,imx7d-src", },
  129. { /* sentinel */ },
  130. };
  131. static struct platform_driver imx7_reset_driver = {
  132. .probe = imx7_reset_probe,
  133. .driver = {
  134. .name = KBUILD_MODNAME,
  135. .of_match_table = imx7_reset_dt_ids,
  136. },
  137. };
  138. builtin_platform_driver(imx7_reset_driver);