pwm-imx.c 8.2 KB

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  1. /*
  2. * simple driver for PWM (Pulse Width Modulator) controller
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <linux/delay.h>
  17. #include <linux/io.h>
  18. #include <linux/pwm.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. /* i.MX1 and i.MX21 share the same PWM function block: */
  22. #define MX1_PWMC 0x00 /* PWM Control Register */
  23. #define MX1_PWMS 0x04 /* PWM Sample Register */
  24. #define MX1_PWMP 0x08 /* PWM Period Register */
  25. #define MX1_PWMC_EN (1 << 4)
  26. /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
  27. #define MX3_PWMCR 0x00 /* PWM Control Register */
  28. #define MX3_PWMSR 0x04 /* PWM Status Register */
  29. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  30. #define MX3_PWMPR 0x10 /* PWM Period Register */
  31. #define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
  32. #define MX3_PWMCR_DOZEEN (1 << 24)
  33. #define MX3_PWMCR_WAITEN (1 << 23)
  34. #define MX3_PWMCR_DBGEN (1 << 22)
  35. #define MX3_PWMCR_POUTC (1 << 18)
  36. #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  37. #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
  38. #define MX3_PWMCR_SWR (1 << 3)
  39. #define MX3_PWMCR_EN (1 << 0)
  40. #define MX3_PWMSR_FIFOAV_4WORDS 0x4
  41. #define MX3_PWMSR_FIFOAV_MASK 0x7
  42. #define MX3_PWM_SWR_LOOP 5
  43. struct imx_chip {
  44. struct clk *clk_per;
  45. void __iomem *mmio_base;
  46. struct pwm_chip chip;
  47. };
  48. #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
  49. static int imx_pwm_config_v1(struct pwm_chip *chip,
  50. struct pwm_device *pwm, int duty_ns, int period_ns)
  51. {
  52. struct imx_chip *imx = to_imx_chip(chip);
  53. /*
  54. * The PWM subsystem allows for exact frequencies. However,
  55. * I cannot connect a scope on my device to the PWM line and
  56. * thus cannot provide the program the PWM controller
  57. * exactly. Instead, I'm relying on the fact that the
  58. * Bootloader (u-boot or WinCE+haret) has programmed the PWM
  59. * function group already. So I'll just modify the PWM sample
  60. * register to follow the ratio of duty_ns vs. period_ns
  61. * accordingly.
  62. *
  63. * This is good enough for programming the brightness of
  64. * the LCD backlight.
  65. *
  66. * The real implementation would divide PERCLK[0] first by
  67. * both the prescaler (/1 .. /128) and then by CLKSEL
  68. * (/2 .. /16).
  69. */
  70. u32 max = readl(imx->mmio_base + MX1_PWMP);
  71. u32 p = max * duty_ns / period_ns;
  72. writel(max - p, imx->mmio_base + MX1_PWMS);
  73. return 0;
  74. }
  75. static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
  76. {
  77. struct imx_chip *imx = to_imx_chip(chip);
  78. u32 val;
  79. int ret;
  80. ret = clk_prepare_enable(imx->clk_per);
  81. if (ret < 0)
  82. return ret;
  83. val = readl(imx->mmio_base + MX1_PWMC);
  84. val |= MX1_PWMC_EN;
  85. writel(val, imx->mmio_base + MX1_PWMC);
  86. return 0;
  87. }
  88. static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
  89. {
  90. struct imx_chip *imx = to_imx_chip(chip);
  91. u32 val;
  92. val = readl(imx->mmio_base + MX1_PWMC);
  93. val &= ~MX1_PWMC_EN;
  94. writel(val, imx->mmio_base + MX1_PWMC);
  95. clk_disable_unprepare(imx->clk_per);
  96. }
  97. static void imx_pwm_sw_reset(struct pwm_chip *chip)
  98. {
  99. struct imx_chip *imx = to_imx_chip(chip);
  100. struct device *dev = chip->dev;
  101. int wait_count = 0;
  102. u32 cr;
  103. writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
  104. do {
  105. usleep_range(200, 1000);
  106. cr = readl(imx->mmio_base + MX3_PWMCR);
  107. } while ((cr & MX3_PWMCR_SWR) &&
  108. (wait_count++ < MX3_PWM_SWR_LOOP));
  109. if (cr & MX3_PWMCR_SWR)
  110. dev_warn(dev, "software reset timeout\n");
  111. }
  112. static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
  113. struct pwm_device *pwm)
  114. {
  115. struct imx_chip *imx = to_imx_chip(chip);
  116. struct device *dev = chip->dev;
  117. unsigned int period_ms;
  118. int fifoav;
  119. u32 sr;
  120. sr = readl(imx->mmio_base + MX3_PWMSR);
  121. fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
  122. if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
  123. period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
  124. NSEC_PER_MSEC);
  125. msleep(period_ms);
  126. sr = readl(imx->mmio_base + MX3_PWMSR);
  127. if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
  128. dev_warn(dev, "there is no free FIFO slot\n");
  129. }
  130. }
  131. static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
  132. struct pwm_state *state)
  133. {
  134. unsigned long period_cycles, duty_cycles, prescale;
  135. struct imx_chip *imx = to_imx_chip(chip);
  136. struct pwm_state cstate;
  137. unsigned long long c;
  138. int ret;
  139. u32 cr;
  140. pwm_get_state(pwm, &cstate);
  141. if (state->enabled) {
  142. c = clk_get_rate(imx->clk_per);
  143. c *= state->period;
  144. do_div(c, 1000000000);
  145. period_cycles = c;
  146. prescale = period_cycles / 0x10000 + 1;
  147. period_cycles /= prescale;
  148. c = (unsigned long long)period_cycles * state->duty_cycle;
  149. do_div(c, state->period);
  150. duty_cycles = c;
  151. /*
  152. * according to imx pwm RM, the real period value should be
  153. * PERIOD value in PWMPR plus 2.
  154. */
  155. if (period_cycles > 2)
  156. period_cycles -= 2;
  157. else
  158. period_cycles = 0;
  159. /*
  160. * Wait for a free FIFO slot if the PWM is already enabled, and
  161. * flush the FIFO if the PWM was disabled and is about to be
  162. * enabled.
  163. */
  164. if (cstate.enabled) {
  165. imx_pwm_wait_fifo_slot(chip, pwm);
  166. } else {
  167. ret = clk_prepare_enable(imx->clk_per);
  168. if (ret)
  169. return ret;
  170. imx_pwm_sw_reset(chip);
  171. }
  172. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  173. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  174. cr = MX3_PWMCR_PRESCALER(prescale) |
  175. MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
  176. MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
  177. MX3_PWMCR_EN;
  178. if (state->polarity == PWM_POLARITY_INVERSED)
  179. cr |= MX3_PWMCR_POUTC;
  180. writel(cr, imx->mmio_base + MX3_PWMCR);
  181. } else if (cstate.enabled) {
  182. writel(0, imx->mmio_base + MX3_PWMCR);
  183. clk_disable_unprepare(imx->clk_per);
  184. }
  185. return 0;
  186. }
  187. static const struct pwm_ops imx_pwm_ops_v1 = {
  188. .enable = imx_pwm_enable_v1,
  189. .disable = imx_pwm_disable_v1,
  190. .config = imx_pwm_config_v1,
  191. .owner = THIS_MODULE,
  192. };
  193. static const struct pwm_ops imx_pwm_ops_v2 = {
  194. .apply = imx_pwm_apply_v2,
  195. .owner = THIS_MODULE,
  196. };
  197. struct imx_pwm_data {
  198. bool polarity_supported;
  199. const struct pwm_ops *ops;
  200. };
  201. static struct imx_pwm_data imx_pwm_data_v1 = {
  202. .ops = &imx_pwm_ops_v1,
  203. };
  204. static struct imx_pwm_data imx_pwm_data_v2 = {
  205. .polarity_supported = true,
  206. .ops = &imx_pwm_ops_v2,
  207. };
  208. static const struct of_device_id imx_pwm_dt_ids[] = {
  209. { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
  210. { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
  211. { /* sentinel */ }
  212. };
  213. MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
  214. static int imx_pwm_probe(struct platform_device *pdev)
  215. {
  216. const struct of_device_id *of_id =
  217. of_match_device(imx_pwm_dt_ids, &pdev->dev);
  218. const struct imx_pwm_data *data;
  219. struct imx_chip *imx;
  220. struct resource *r;
  221. int ret = 0;
  222. if (!of_id)
  223. return -ENODEV;
  224. data = of_id->data;
  225. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  226. if (imx == NULL)
  227. return -ENOMEM;
  228. imx->clk_per = devm_clk_get(&pdev->dev, "per");
  229. if (IS_ERR(imx->clk_per)) {
  230. dev_err(&pdev->dev, "getting per clock failed with %ld\n",
  231. PTR_ERR(imx->clk_per));
  232. return PTR_ERR(imx->clk_per);
  233. }
  234. imx->chip.ops = data->ops;
  235. imx->chip.dev = &pdev->dev;
  236. imx->chip.base = -1;
  237. imx->chip.npwm = 1;
  238. if (data->polarity_supported) {
  239. dev_dbg(&pdev->dev, "PWM supports output inversion\n");
  240. imx->chip.of_xlate = of_pwm_xlate_with_flags;
  241. imx->chip.of_pwm_n_cells = 3;
  242. }
  243. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  244. imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  245. if (IS_ERR(imx->mmio_base))
  246. return PTR_ERR(imx->mmio_base);
  247. ret = pwmchip_add(&imx->chip);
  248. if (ret < 0)
  249. return ret;
  250. platform_set_drvdata(pdev, imx);
  251. return 0;
  252. }
  253. static int imx_pwm_remove(struct platform_device *pdev)
  254. {
  255. struct imx_chip *imx;
  256. imx = platform_get_drvdata(pdev);
  257. if (imx == NULL)
  258. return -ENODEV;
  259. return pwmchip_remove(&imx->chip);
  260. }
  261. static struct platform_driver imx_pwm_driver = {
  262. .driver = {
  263. .name = "imx-pwm",
  264. .of_match_table = imx_pwm_dt_ids,
  265. },
  266. .probe = imx_pwm_probe,
  267. .remove = imx_pwm_remove,
  268. };
  269. module_platform_driver(imx_pwm_driver);
  270. MODULE_LICENSE("GPL v2");
  271. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");